CN103943497A - Back surface formation method - Google Patents
Back surface formation method Download PDFInfo
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- CN103943497A CN103943497A CN201310023662.6A CN201310023662A CN103943497A CN 103943497 A CN103943497 A CN 103943497A CN 201310023662 A CN201310023662 A CN 201310023662A CN 103943497 A CN103943497 A CN 103943497A
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 238000002161 passivation Methods 0.000 claims abstract description 63
- 150000002500 ions Chemical class 0.000 claims abstract description 50
- 238000000137 annealing Methods 0.000 claims abstract description 27
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 239000011265 semifinished product Substances 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 9
- -1 boron ion Chemical class 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 11
- 230000004913 activation Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a back surface formation method, for processing a first semi-finished product of an insulated gate bipolar transistor device. The method comprises: depositing a passivation layer on at least one second area of the front surface of a first substrate and the front surfaces of M polysilicon gate electrodes, the at least one second area being an area which does not have M gate oxidation blocks deposited therein; thinning the thickness of the first substrate from the back surface of the first substrate so as to form a second substrate; injecting first ions to the back surface of the second substrate to form a P+ area; and performing annealing processing on the passivation layer and the P+ area so as to enable the first ions in the P+ area to be activated and enable backflow of the passivation layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of back of the body surface forming method.
Background technology
In current world overall semiconductor industry, power device is in occupation of very important position, insulated gate bipolar transistor (IGBT) is one of important representative in semiconductor power device, it not only has the plurality of advantages of other metal-oxide half field effect transistor, such as: switching speed is fast, more than switching speed can reach MHz, the features such as voltage driving; Also there is bipolar transistor, such as: conductivity modulation effect, current density is high, energy consumption is less, can be regarded as one " green energy conservation type " power device facing the future, and is also one of core technology of domestic each large key project at present.
For the manufacturing process of this structure various piece, the injection of back side P+ anode and annealing more receive publicity always.
The back process of insulated gate bipolar transistor of the prior art is to form BeiP+ district by Implantation again after front surface structure all completes, the back side of insulated gate bipolar transistor of the prior art forms technique as shown in Figure 1, specifically comprises the steps:
S101: the positive technique that completes insulated gate bipolar transistor, the structure forming comprises: the first substrate, the P type channel region forming in described the first substrate, the heavy doping N+ source region forming in described P type channel region, and M the gate oxidation piece forming at least one first area of described the first substrate front surface, M the polygate electrodes forming on described M gate oxidation piece, M is more than or equal to 1 integer;
S102: in the front surface deposit passivation layer of at least one second area and a described M polygate electrodes of described the first substrate front surface, wherein, described at least one second area is the region that does not deposit described M gate oxidation piece;
S103: to the passivation layer annealing in process forming, so that passivation layer refluxes;
S104: etched portions passivation layer, to form at least one metal aperture;
S105: carry out metal sputtering, so that at least metal aperture and the passivation layer surface that all do not etch away described in filling;
S106: the first substrate is carried out to reduction processing from the back side of the first substrate;
S107: inject ion from the back side and form p+ district;
S108: DuiP+ district annealing in process, to activate the ion in P+ district;
S109: back of the body gold.
But present inventor realizing in the process of invention technical scheme in the embodiment of the present application, finds that above-mentioned technology at least exists following technical problem:
After the positive technique of insulated gate bipolar transistor completes, carry out thinning back side and form P+ district by back side Implantation because prior art adopts, activate the ion in P+ district, now, front surface structure and metal level form, so existing the temperature of ion that activates P+ district to exceed 500 degrees Celsius will affect the front surface structure that formed and the technical problem of metal level;
After the positive technique of insulated gate bipolar transistor completes, carry out thinning back side and pass through back side Implantation because prior art adopts, activate the ion in P+ district, so, exist the activation of the backflow of passivation layer and the ion in P+ district, the back side will adopt the technical problem of twice annealing processing.
Summary of the invention
The application provides a kind of back of the body surface forming method by embodiment, and the temperature that activates the ion in P+ district for solving prior art exceedes 500 degrees Celsius will affect the front surface structure that formed and the technical problem of metal level.
The application provides a kind of back of the body surface forming method, for the first semi-finished product of insulated-gate bipolar transistor device are processed, described the first semi-finished product include the first substrate, the P type channel region forming in described the first substrate, the heavy doping N+ source region forming in described P type channel region, and M the gate oxidation piece forming at least one first area of described the first substrate front surface, M the polygate electrodes forming on described M gate oxidation piece, M is more than or equal to 1 integer, and described method comprises following technical scheme:
In the front surface deposit passivation layer of at least one second area and a described M polygate electrodes of described the first substrate front surface, wherein, described at least one second area is the region that does not deposit described M gate oxidation piece;
From the first substrate thickness described in the thinning back side of described the first substrate, so that form the second substrate;
Inject the first ion at the back side of described the second substrate, to form P+ district;
Described passivation layer and described P+ district are carried out to annealing in process, so that described first ion-activated in described P+ district, and make the backflow of described passivation layer.
Preferably, described from the first substrate thickness described in the thinning back side of described the first substrate, so that form the second substrate, specifically comprise:
Application pressure drop scope based on described insulated-gate bipolar transistor device, determines the second thickness of described the second substrate;
Based on described the second thickness, from the first substrate thickness described in the thinning back side of described the first substrate, to form described second substrate of described the second thickness.
Preferably, the first ion is injected at the described back side at described the second substrate, is specially:
Be e at the back side of described the second substrate implantation dosage
13cubic centimetre is to e
14the first ion of cubic centimetre.
Preferably, described the first ion is specifically as follows: boron ion or phosphonium ion.
Preferably, the thickness in described P+ district is 3um to 5um.
Preferably, described described passivation layer and described P+ district are carried out to annealing in process, so that described first ion-activated in described P+ district, and make the backflow of described passivation layer, be specially:
Be that described P+ district adopts the temperature of 900 degrees Celsius to 1000 degrees Celsius to carry out annealing in process to described passivation layer, so that described first ion-activated in described P+ district, and make the backflow of described passivation layer.
Preferably, described, described passivation layer and described P+ district are carried out to annealing in process, so that described first ion-activated in described P+ district, and after making the backflow of described passivation layer, described method also comprises:
Passivation layer described in etched portions in described at least one second area, to form front metal hole;
By sputter, in described front metal hole and remaining described passivation layer surface form metal level;
Surface in described P+ district forms metal covering.
The one or more technical schemes that provide in the embodiment of the present application, at least have following technique effect or advantage:
1, owing to having adopted after deposit passivation layer, carry out thinning back side and form P+ district by back side Implantation, then described passivation layer and described P+ district are carried out the technological means of annealing in process, so, efficiently solving the temperature that activates the ion in P+ district in prior art exceedes 500 degrees Celsius and will affect the front surface structure that formed and the technical problem of metal level, and then, realize the technique effect that improves the temperature that activates P+ ion, improve the ion-activated effect in LiaoP+ district, concrete, activate the temperature of P+ district ion and can bring up to 900 degrees Celsius to 1000 degrees Celsius,
2, owing to having adopted after deposit passivation layer, carry out thinning back side and form P+ district by back side Implantation, then described passivation layer and described P+ district are carried out the technological means of annealing in process, so, the activation that efficiently solves the backflow of passivation layer in prior art and the ion in P+ district, the back side will adopt the technical problem of twice annealing processing, and then, realize the technique effect of the activation of the backflow of the passivation layer of once having annealed and the ion in P+ district, the back side, and then reduced technological process and process costs.
Brief description of the drawings
Fig. 1 is the flow chart of the method that in prior art, the back side forms;
Fig. 2 is first half-finished structural representation in the embodiment of the present application;
Fig. 3 is the flow chart of the method that in the embodiment of the present application, the back side forms;
Fig. 4 is the structural representation forming after the step S301 in the embodiment of the present application;
Fig. 5 is the structural representation forming after the step S302 in the embodiment of the present application;
Fig. 6 is the structural representation forming after the step S304 in the embodiment of the present application.
Embodiment
The embodiment of the present application is carried on the back surface forming method activates the ion in P+ district temperature for solving prior art and is exceeded 500 degrees Celsius and will affect the front surface structure that formed and the technical problem of metal level by providing a kind of.
Technical scheme in the embodiment of the present application is for solving the problems of the technologies described above, and general thought is as follows:
The first semi-finished product to insulated-gate bipolar transistor device are processed, described the first semi-finished product as shown in Figure 2, specifically include the first substrate 201, the P type channel region 202 forming in described the first substrate 201, the heavy doping N+ source region 203 forming in described P type channel region 202, and M the gate oxidation piece 204 forming at least one first area of described the first substrate 201 front surfaces, M the polygate electrodes 205 forming on described M gate oxidation piece 204, M is more than or equal to 1 integer, described method comprises: in the front surface deposit passivation layer 206 of at least one second area and a described M polygate electrodes 205 of described the first substrate 201 front surfaces, wherein, described at least one second area is the region that does not deposit described M gate oxidation piece 204, from the first substrate 201 thickness described in the thinning back side of described the first substrate 201, so that form the second substrate 207, inject the first ion at the back side of described the second substrate 207, to form P+ district 208, described passivation layer 206 and described P+ district 208 are carried out to annealing in process, so that described first ion-activated in described P+ district 208, and make the backflow of described passivation layer 206.
After front surface deposit passivation layer 206 due at least one second area at described the first substrate 201 front surfaces and a described M polygate electrodes 205, also sputter does not form metal level, so continue from the first substrate 201 thickness described in the thinning back side of described the first substrate 201, so that form the second substrate 207; Inject the first ion at the back side of described the second substrate 207, in technique with formation P+ district 208, described passivation layer 206 and described P+ district 208 are carried out to annealing in process, can utilize the annealing steps of passivation layer 206 to realize the ion-activated of LiaoP+ district 208, so temperature can reach 900 degrees Celsius to 1000 degrees Celsius, exceed 500 degrees Celsius and will affect the front surface structure that formed and the technical problem of metal level so solved the temperature that activates the ion injecting in prior art.
In order better to understand technique scheme, below in conjunction with Figure of description and concrete execution mode, technique scheme is described in detail.
The embodiment of the present application is by a kind of method that provides back side to form, as shown in Figure 3, for the first semi-finished product of insulated-gate bipolar transistor device are processed, first half-finished structure as shown in Figure 2, described the first semi-finished product include the first substrate 201, the P type channel region 202 forming in described the first substrate 201, the heavy doping N+ source region 203 forming in described P type channel region 202, and M the gate oxidation piece 204 forming at least one first area of described the first substrate 201 front surfaces, M the polygate electrodes 205 forming on described M gate oxidation piece 204, M is more than or equal to 1 integer,
Described method specifically comprises the steps:
S301: in the front surface deposit passivation layer 206 of at least one second area and a described M polygate electrodes 205 of described the first substrate 201 front surfaces, wherein, described at least one second area is the region that does not deposit described M gate oxidation piece 204;
Concrete, because which kind of technological process not processed the first semi-finished product of this method specifically adopt form and be specially the impact of which kind of refined structure, so the application does not limit forming first half-finished technological process and refined structure.
In specific implementation process, passivation layer 206 can, for the silicon dioxide of boron-doping phosphorus, can be also the silicon dioxide of not boron-doping phosphorus.
After execution of step S301, form structure as shown in Figure 4, then, execution step S302, that is: from the first substrate 201 thickness described in the thinning back side of described the first substrate 201, so that form the second substrate 207;
In specific implementation process, from the first substrate 201 thickness described in the thinning back side of described the first substrate 201, so that form the second substrate 207, specifically comprise following two steps:
Step 1: the application pressure drop scope based on described insulated-gate bipolar transistor device, determine the second thickness of described the second substrate 207;
Concrete according to the application pressure drop scope of insulated-gate bipolar transistor device, the thickness of the second substrate 207 of determining can be between 80um to 250um, for example, final finished product insulated-gate bipolar transistor device is applied in the scope of 1200V, and the second thickness of determining can be 220um.
Step 2: based on described the second thickness, from the first substrate 201 thickness described in the thinning back side of described the first substrate 201, to form described second substrate 207 of described the second thickness.
Concrete, can carry out attenuate to the back side of the first substrate 201 by the method for machining or chemical reaction, to improve the radiating effect of chip, concrete, the technique that realizes attenuate is divided into attenuate, grind, polishing, clean, so that finally form the second thickness of the second substrate 207, the evenness at second substrate 207 back sides and roughness reach the predetermined standard of technique, because of different insulated gate bipolar transistors, different equipment all can make the evenness at second substrate 207 back sides, roughness difference, and it is concrete, the evenness at second substrate 207 back sides, the technological standards of roughness is known by those skilled in the art, so the application repeats no more.
The structure as shown in Figure 5 forming based on step S302, execution step S303 injects the first ion at the back side of described the second substrate 207, to form P+ district 208 that is:;
In specific implementation process, forming P+ district 208 is thinner than prior art and the first ion doping dosage Qing P+ district 208, concrete: the first ion is injected at the described back side at described the second substrate 207, be specifically as follows: boron ion or phosphonium ion, the scope of ion dose of injecting be e13 cubic centimetre between e14 cubic centimetre, energy range is between 100 to 200keV.
Based on forming P+ district 208 after step S303, execution step S304 carries out annealing in process to described passivation layer 206 and described P+ district 208 that is:, so that described first ion-activated in described P+ district 208, and makes the backflow of described passivation layer 206.
Concrete, described described passivation layer 206 and described P+ district 208 are carried out to annealing in process, so that described first ion-activated in described P+ district 208, and make the backflow of described passivation layer 206, be specially:
Adopt the temperature of 900 degrees Celsius to 1000 degrees Celsius to carry out annealing in process to described passivation layer 206 and described P+ district 208, so that described first ion-activated in described P+ district 208, and make the backflow of described passivation layer 206.
In specific implementation process, semi-finished product after execution step S303 are put into boiler tube, first, need to set the annealing temperature of boiler tube according to boiler tube device menus and technique, specifically can be set as between 900 degrees Celsius to 1000 degrees Celsius, because can not complete the effect of P+ district, the back side 208 knots lower than 900 degree, can have influence on the junction depth of surface texture higher than 1000 degree.Then, be heated to the temperature of setting, maintain the temperature regular hour of setting, finally cooling.
After execution of step S304, form structure as shown in Figure 6.
In specific implementation process, described, described passivation layer 206 and described P+ district 208 are carried out to annealing in process, so that described first ion-activated in described P+ district 208, and after making the backflow of described passivation layer 206, described method also comprises following three steps:
Step 1: passivation layer 206 described in etched portions in described at least one second area, to form front metal hole;
In specific implementation process, define and need etch areas at least one second area of passivation layer 206 through photoetching, the region that needs etching that adopts dry method or wet etching to define, all etches away the passivation layer in region 206, exposes the front surface of the second substrate 207.
Step 2: by sputter, in described front metal hole and remaining described passivation layer 206 forming metal layer on surfaces;
In specific implementation process, the metal level that sputter forms be specifically as follows aluminium, tungsten etc.
Step 3: the surface in described P+ district 208 forms metal covering.
In specific implementation process, can form layer of metal floor with the surface in the mode P+ district 208 of sputter or evaporation, metal level is specifically as follows aluminium lamination or tungsten layer etc.
The one or more technical schemes that provide in the embodiment of the present application, at least have following technique effect or advantage:
1, owing to having adopted after deposit passivation layer, carry out thinning back side and form P+ district by back side Implantation, then described passivation layer and described P+ district are carried out the technological means of annealing in process, so, efficiently solving the temperature that activates the ion in P+ district in prior art exceedes 500 degrees Celsius and will affect the front surface structure that formed and the technical problem of metal level, and then, realize the technique effect that improves the temperature that activates P+ ion, improve the ion-activated effect in LiaoP+ district, concrete, activate the temperature of P+ district ion and can bring up to 900 degrees Celsius to 1000 degrees Celsius,
2, owing to having adopted after deposit passivation layer, carry out thinning back side and form P+ district by back side Implantation, then described passivation layer and described P+ district are carried out the technological means of annealing in process, so, the activation that efficiently solves the backflow of passivation layer in prior art and the ion in P+ district, the back side will adopt the technical problem of twice annealing processing, and then, realize the technique effect of the activation of the backflow of the passivation layer of once having annealed and the ion in P+ district, the back side, and then reduced technological process and process costs.
Although described the preferred embodiments of the present invention, once those skilled in the art obtain the basic creative concept of cicada, can make other change and amendment to these embodiment.So affiliated claim is intended to be interpreted as comprising preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. a back of the body surface forming method, for the first semi-finished product of insulated-gate bipolar transistor device are processed, described the first semi-finished product include the first substrate, the P type channel region forming in described the first substrate, the heavy doping N+ source region forming in described P type channel region, and M the gate oxidation piece forming at least one first area of described the first substrate front surface, M the polygate electrodes forming on described M gate oxidation piece, M is more than or equal to 1 integer, it is characterized in that, described method comprises:
In the front surface deposit passivation layer of at least one second area and a described M polygate electrodes of described the first substrate front surface, wherein, described at least one second area is the region that does not deposit described M gate oxidation piece;
From the first substrate thickness described in the thinning back side of described the first substrate, so that form the second substrate;
Inject the first ion at the back side of described the second substrate, to form P+ district;
Described passivation layer and described P+ district are carried out to annealing in process, so that described first ion-activated in described P+ district, and make the backflow of described passivation layer.
2. the method for claim 1, is characterized in that, described from the first substrate thickness described in the thinning back side of described the first substrate, so that form the second substrate, specifically comprises:
Application pressure drop scope based on described insulated-gate bipolar transistor device, determines the second thickness of described the second substrate;
Based on described the second thickness, from the first substrate thickness described in the thinning back side of described the first substrate, to form described second substrate of described the second thickness.
3. the method for claim 1, is characterized in that, the first ion is injected at the described back side at described the second substrate, is specially:
Be e at the back side of described the second substrate implantation dosage
13cubic centimetre is to e
14the first ion of cubic centimetre.
4. method as claimed in claim 3, is characterized in that, described the first ion is specifically as follows: boron ion or phosphonium ion.
5. method as claimed in claim 4, is characterized in that, the thickness in described P+ district is 3um to 5um.
6. the method for claim 1, is characterized in that, described described passivation layer and described P+ district is carried out to annealing in process, so that described first ion-activated in described P+ district, and makes the backflow of described passivation layer, is specially:
Be that described P+ district adopts the temperature of 900 degrees Celsius to 1000 degrees Celsius to carry out annealing in process to described passivation layer, so that described first ion-activated in described P+ district, and make the backflow of described passivation layer.
7. the method as described in arbitrary claim in claim 1-6, it is characterized in that, described, described passivation layer and described P+ district are carried out to annealing in process, so that described first ion-activated in described P+ district, and after making the backflow of described passivation layer, described method also comprises:
Passivation layer described in etched portions in described at least one second area, to form front metal hole;
By sputter, in described front metal hole and remaining described passivation layer surface form metal level;
Surface in described P+ district forms metal covering.
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| CN201310023662.6A CN103943497B (en) | 2013-01-22 | 2013-01-22 | A kind of back side forming method |
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| CN201310023662.6A CN103943497B (en) | 2013-01-22 | 2013-01-22 | A kind of back side forming method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298535A (en) * | 2015-06-11 | 2017-01-04 | 北大方正集团有限公司 | Method, semi-conductor device manufacturing method |
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