CN103928510A - Silicon controlled rectifier and layout structure thereof - Google Patents
Silicon controlled rectifier and layout structure thereof Download PDFInfo
- Publication number
- CN103928510A CN103928510A CN201410139010.3A CN201410139010A CN103928510A CN 103928510 A CN103928510 A CN 103928510A CN 201410139010 A CN201410139010 A CN 201410139010A CN 103928510 A CN103928510 A CN 103928510A
- Authority
- CN
- China
- Prior art keywords
- injection region
- type injection
- region
- thyristor
- trap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract description 9
- 229910052710 silicon Inorganic materials 0.000 title abstract description 9
- 239000010703 silicon Substances 0.000 title abstract description 9
- 238000002347 injection Methods 0.000 claims abstract description 112
- 239000007924 injection Substances 0.000 claims abstract description 112
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052755 nonmetal Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 230000001960 triggered effect Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42308—Gate electrodes for thyristors
Abstract
The invention provides a silicon controlled rectifier and a layout structure of the silicon controlled rectifier. According to the silicon controlled rectifier and the layout structure of the silicon controlled rectifier, a gate structure, a second N-type injection region (as a source electrode) and a third N-type injection region (as a drain electrode) form an NMOS structure; when forward ESD happens, a positive potential will be coupled to the gate structure end through a capacitor; at the moment, electric leakage of the NMOS structure is increased, leak currents from a P trap to the second N-type injection region are increased, and as a result, the resistance drop of the P trap is increased, an emitter junction of an NPN transistor is switched on, and then the NPN transistor is switched on. Now, a PNP transistor is triggered and switched on, the silicon controlled rectifier is made to be turned on, and the turn-on voltage of the silicon controlled rectifier can be reduced. The capacitor and a resistor form an RC trigger circuit, and the delay time can be adjusted by controlling the resistance value and the capacitance value, so that the positive potential coupled to the gate structure end will not be grounded at once, the time of the positive potential at the gate structure end is prolonged, and then the NPN transistor is controlled to be switched on; consequently, the turn-on voltage of the silicon controlled rectifier is adjusted.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of thyristor and domain structure thereof.
Background technology
In integrated circuit fields, static is ubiquitous, static discharge (E1ectrostatic Discharge, ESD) phenomenon is embodied in, a large amount of electrostatic charge moments of external environment condition or chip internal accumulation enter by pin or flow out chip internal, this Transient Currents peak value can reach more than several amperes, is enough to cause the expendable damage such as gate oxide breakdown, metal fusing.According to statistics, the chip failure that ESD causes accounts for 30%～50% of chip failure sum.Along with constantly dwindling of integrated circuit characteristic size, gate oxide is more and more thinner, is more easily subject to electrostatic impact thus and loses efficacy, and the esd protection that strengthens integrated circuit (IC) chip has become research emphasis.
For esd protection device, on the one hand can not affect circuit and normally work, a low-resistance large current channel of releasing in the time that occurring, ESD phenomenon can be provided on the other hand in time.Thyristor (silicon controlled rectifier, SCR) is one of esd protection device of full blast, can bear larger transient current, and the esd protection ability of its unit are is the strongest.
Please refer to Fig. 1, it is traditional thyristor structure figure.As shown in Figure 1, described thyristor is made up of PNP transistor T 1 and NPN transistor T2.In the time that forward esd pulse occurs Vdd end, the p-n junction of N trap and P trap is reverse-biased, and in the time that voltage increase makes reverse biased junction generation avalanche breakdown, electric current, through the resistance of P trap, produces pressure drop, makes T2 conducting; T2 will cause N trap resistance drop to increase after opening, make T1 conducting.And the collector electrode of T1 is the base stage of T2, the collector electrode of T2 is the base stage of T1, and two transistors form positive feedbacks, in the time that the gain of thyristor is greater than unit gain, can form the lasting current path ESD that releases in thyristor.
Therefore, thyristor cut-in voltage depends primarily on the puncture voltage of the reverse p-n junction of N trap and P trap, cut-in voltage is too greatly a shortcoming of thyristor, if cut-in voltage is greater than the puncture voltage of gate oxide, to directly cause thyristor also not opened, but the breakdown result of gate oxide.Please refer to Fig. 2, it is the thyristor structure figure after traditional reduction cut-in voltage.As shown in Figure 2, (reducing after cut-in voltage) thyristor, also be called low trigger voltage SCR(LVSCR), in the middle of N trap in the thyristor shown in Fig. 1 and P trap, add a N-type injection region, and deposition one deck polysilicon layer in the middle of N-type injection region in this N-type injection region and P trap, described polysilicon layer ground connection, forms a grounded-grid NMOS(GGNMOS thus), now, the cut-in voltage of thyristor is close to the cut-in voltage of GGNMOS.In fact, another major issue that thyristor exists is that to maintain voltage low, in application, be easy to like this false triggering latch-up, therefore developed again the LVSCR of some high maintenance voltages and high maintenance electric current, but these technology all can cause cut-in voltage to increase, so it is just very important further to reduce the cut-in voltage of SCR.
Summary of the invention
The object of the present invention is to provide a kind of thyristor and domain structure thereof, further to reduce the cut-in voltage of SCR.
For solving the problems of the technologies described above, the invention provides a kind of thyristor, described thyristor comprises: substrate; Be arranged in N trap and the P trap of substrate; Be arranged in the first N-type injection region and a P type injection region of N trap; Be arranged in the second N-type injection region and the 2nd P type injection region of P trap; And the 3rd N-type injection region between N trap and P trap; Wherein, between described the second N-type injection region and the 3rd N-type injection region, be formed with grid structure, described grid structure is connected with the first level by electric capacity, and described grid structure is connected with second electrical level by resistance, and described the first level is higher than second electrical level.
Optionally, in described thyristor, described grid structure comprises oxide layer and is positioned at the polysilicon layer in described oxide layer.
Optionally, in described thyristor, described electric capacity is formed by described polysilicon layer and the metal level that is positioned on described polysilicon layer.
Optionally, in described thyristor, between described polysilicon layer and described metal level, be also formed with dielectric layer.
Optionally, in described thyristor, described metal level is copper metal layer or aluminum metal layer.
Optionally, in described thyristor, between described the first N-type injection region and a P type injection region, between a P type injection region and the 3rd N-type injection region and be all formed with isolation structure between the second N-type injection region and the 2nd P type injection region.
Optionally, in described thyristor, on described the first N-type injection region, on a P type injection region, on the second N-type injection region, be all formed with metal electrode on the 2nd P type injection region.
Optionally, in described thyristor, described the first N-type injection region and a P type injection region are connected with the first level by metal electrode, and described the second N-type injection region and the 2nd P type injection region are connected with second electrical level by metal electrode.
Optionally, in described thyristor, described second electrical level is earth potential.
The present invention also provides a kind of domain structure of thyristor, and the domain structure of described thyristor comprises: substrate zone; Be positioned at N well region and P well region on substrate zone; Be positioned at the region, five injection regions of arranging in turn on N well region and P well region; Wherein, between the 3rd region, injection region and the 4th region, injection region, have grid structure district, described grid structure is formed with nonmetal wire area in district.
In thyristor provided by the invention and domain structure thereof, grid structure, the second N-type injection region (as source electrode) and the 3rd N-type injection region (as drain electrode) have formed a NMOS structure, in the time that forward ESD occurs, grid structure end can be coupled out to a positive potential by electric capacity, the now electric leakage of NMOS structure increases, and P trap increases to the leakage current of the second N-type injection region, thereby causes P trap resistance drop to increase, promote the conducting of NPN transistor emitter junction, further make transistor NPN conducting.So far, will trigger PNP transistor turns, thyristor is opened, this operation principle can further reduce the cut-in voltage of thyristor.Further, form RC circuits for triggering by resistance and electric capacity, can carry out the control lag time by controlling resistance value and capacitance, make not ground connection at once of positive potential that grid structure end is coupled out, extend grid structure and rectify the time of current potential, further control the conducting of NPN transistor, thus the cut-in voltage of modulation thyristor.
Brief description of the drawings
Fig. 1 is traditional thyristor structure figure;
Fig. 2 is the thyristor structure figure after traditional reduction cut-in voltage;
Fig. 3 is the thyristor structure figure of the embodiment of the present invention;
Fig. 4 is the domain structure schematic diagram of the thyristor of the embodiment of the present invention.
Embodiment
The thyristor and the domain structure thereof that the present invention are proposed below in conjunction with the drawings and specific embodiments are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 3, the thyristor structure figure that it is the embodiment of the present invention.As shown in Figure 3, in the embodiment of the present application, described thyristor 1 comprises: substrate 10; Be arranged in N trap 11 and the P trap 12 of substrate 10; Be arranged in the first N-type injection region 13 and a P type injection region 14 of N trap 11; Be arranged in the second N-type injection region 15 and the 2nd P type injection region 16 of P trap 12; And the 3rd N-type injection region 17 between N trap 11 and P trap 12; Wherein, between described the second N-type injection region 15 and the 3rd N-type injection region 17, be formed with grid structure 18, described grid structure 18 is connected with the first level Vdd by electric capacity 19, and described grid structure 18 is connected with second electrical level Vss by resistance 20, and described the first level Vdd is higher than second electrical level Vss.Common, described the first level Vdd is power supply potential, and described second electrical level Vss is earth potential.
At this, described grid structure 18, the second N-type injection region 15(is as source electrode) and the 3rd N-type injection region 17(as drain electrode) formed a NMOS structure, in the time there is (forward esd pulse occurs the first level Vdd end) in forward ESD, grid structure 18 ends can be coupled out to a positive potential by electric capacity 19, the now electric leakage of NMOS structure increases, the leakage current of P trap 12 to second N-type injection regions 15 increases, thereby cause P trap 12 resistance drops to increase, promote that NPN transistor (is N trap 11, the transistor that P trap 12 and the second N-type injection region 15 form) conducting of emitter junction, further make transistor NPN conducting.So far, will trigger PNP transistor (transistor that a P type injection region 14, N trap 11 and P trap 12 form) conducting, thyristor 1 is opened, this operation principle can further reduce the cut-in voltage of thyristor 1.
Further, form RC circuits for triggering by resistance 20 and electric capacity 19, can carry out the control lag time by controlling resistance value and capacitance, make not ground connection at once of positive potential that grid structure 18 ends are coupled out, extend the time that grid structure 18 is rectified current potential, further control the conducting of NPN transistor, thus the cut-in voltage of modulation thyristor 1.
Further, described grid structure 18 comprises oxide layer and is positioned at the polysilicon layer in described oxide layer, and wherein, described oxide layer can be silicon dioxide layer.In the embodiment of the present application, described electric capacity 19 is formed by described polysilicon layer and the metal level that is positioned on described polysilicon layer.Wherein, between described polysilicon layer and described metal level, be also formed with dielectric layer.Thus, the electric capacity 19 forming need not additionally increase chip area, to this, the domain structure at thyristor be further described.Further, described metal level can be copper metal layer or aluminum metal layer.
In the embodiment of the present application, between described the first N-type injection region 13 and a P type injection region 14, between a P type injection region 14 and the 3rd N-type injection region 17 and be all formed with isolation structure between the second N-type injection region 15 and the 2nd P type injection region 16.Concrete, between the first N-type injection region 13 and a P type injection region 14, be formed with isolation structure 21; Between the one P type injection region 14 and the 3rd N-type injection region 17, be formed with isolation structure 22; And second be formed with isolation structure 23 between N-type injection region 15 and the 2nd P type injection region 16.Can better each injection region be kept apart by described isolation structure, thus the reliability of raising thyristor 1.
Further, on described the first N-type injection region 13, on a P type injection region 14, on the second N-type injection region 15 and on the 2nd P type injection region 16, be all formed with metal electrode (not shown in Fig. 3).Described the first N-type injection region 13 and a P type injection region 14 are connected with the first level Vdd by metal electrode, and described the second N-type injection region 15 and the 2nd P type injection region 16 are connected with second electrical level Vss by metal electrode.Can ensure the reliability of above-mentioned connection by described metal electrode.
Subsequent, please refer to Fig. 4, the domain structure schematic diagram of its thyristor that is the embodiment of the present invention.As shown in Figure 4, the domain structure 2 of described thyristor comprises: substrate zone (not shown in Fig. 4); Be arranged in N well region (Fig. 4 is not shown) and P well region (Fig. 4 is not shown) on substrate zone; Be positioned on N well region and P well region the region, five injection regions of arranging in turn, be respectively corresponding aforesaid the first N-type injection region 13 of the first region, injection region 35(), the corresponding aforesaid P type injection region 14 of the second region, injection region 36(), corresponding aforesaid the 3rd N-type injection region 17 of the 3rd region, injection region 37(), corresponding aforesaid the second N-type injection region 15 of the 4th region, injection region 38() and corresponding aforesaid the 2nd P type injection region 16 of the 5th region, injection region 39(); Wherein, in the first region, injection region 35, the second region, injection region 36, the 4th region, injection region 38 and the 5th region, injection region 39, be also formed with metal electric polar region; Wherein, between the 3rd region, injection region 32 and the 4th region, injection region 33, there is grid structure district 40, in described grid structure district 40, be formed with nonmetal wire area 41.Further, on N well region and P well region, be also arranged with in turn five oxide isolation regions, be respectively the first oxide isolation regions 30, the second oxide isolation regions 31, the 3rd oxide isolation regions 32, the 4th oxide isolation regions 33 and the 5th oxide isolation regions 34, so that the first region, injection region 35, the second region, injection region 36, the 3rd region, injection region 37, the 4th region, injection region 38 and the 5th region, injection region 39 are isolated.
In the domain structure 2 of the thyristor of the embodiment of the present application, in grid structure district 40, be formed with nonmetal wire area 41, be that grid structure district 40 is overlapping with nonmetal wire area 41, the electric capacity forming according to the domain structure 2 of described thyristor can be used the part polysilicon in grid structure, and the electric capacity that formed as can be seen here need not additionally increase chip area.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (10)
1. a thyristor, is characterized in that, comprising: substrate; Be arranged in N trap and the P trap of substrate; Be arranged in the first N-type injection region and a P type injection region of N trap; Be arranged in the second N-type injection region and the 2nd P type injection region of P trap; And the 3rd N-type injection region between N trap and P trap; Wherein, between described the second N-type injection region and the 3rd N-type injection region, be formed with grid structure, described grid structure is connected with the first level by electric capacity, and described grid structure is connected with second electrical level by resistance, and described the first level is higher than second electrical level.
2. thyristor as claimed in claim 1, is characterized in that, described grid structure comprises oxide layer and is positioned at the polysilicon layer in described oxide layer.
3. thyristor as claimed in claim 2, is characterized in that, described electric capacity is formed by described polysilicon layer and the metal level that is positioned on described polysilicon layer.
4. thyristor as claimed in claim 3, is characterized in that, between described polysilicon layer and described metal level, is also formed with dielectric layer.
5. thyristor as claimed in claim 3, is characterized in that, described metal level is copper metal layer or aluminum metal layer.
6. the thyristor as described in any one in claim 1～5, it is characterized in that, between described the first N-type injection region and a P type injection region, between a P type injection region and the 3rd N-type injection region and be all formed with isolation structure between the second N-type injection region and the 2nd P type injection region.
7. the thyristor as described in any one in claim 1～5, is characterized in that, on described the first N-type injection region, on a P type injection region, on the second N-type injection region, be all formed with metal electrode on the 2nd P type injection region.
8. thyristor as claimed in claim 7, is characterized in that, described the first N-type injection region and a P type injection region are connected with the first level by metal electrode, and described the second N-type injection region and the 2nd P type injection region are connected with second electrical level by metal electrode.
9. the thyristor as described in any one in claim 1～5, is characterized in that, described second electrical level is earth potential.
10. a domain structure for thyristor, is characterized in that, comprising: substrate zone; Be positioned at N well region and P well region on substrate zone; Be positioned at the region, five injection regions of arranging in turn on N well region and P well region; Wherein, between the 3rd region, injection region and the 4th region, injection region, have grid structure district, described grid structure is formed with nonmetal wire area in district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410139010.3A CN103928510A (en) | 2014-04-08 | 2014-04-08 | Silicon controlled rectifier and layout structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410139010.3A CN103928510A (en) | 2014-04-08 | 2014-04-08 | Silicon controlled rectifier and layout structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103928510A true CN103928510A (en) | 2014-07-16 |
Family
ID=51146671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410139010.3A Pending CN103928510A (en) | 2014-04-08 | 2014-04-08 | Silicon controlled rectifier and layout structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103928510A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332493A (en) * | 2014-09-03 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator device and electrostatic protection device structure formed thereby |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528188A (en) * | 1995-03-13 | 1996-06-18 | International Business Machines Corporation | Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier |
| US5907462A (en) * | 1994-09-07 | 1999-05-25 | Texas Instruments Incorporated | Gate coupled SCR for ESD protection circuits |
| US20030067039A1 (en) * | 2001-10-10 | 2003-04-10 | Shin Su | Electrostatic discharge protection structure |
| US6911679B1 (en) * | 2003-01-09 | 2005-06-28 | National Semiconductor Corp. | LVTSCR with compact design |
| CN103094322A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Groove type insulated gate field-effect tube structure capable of being used for electrostatic protection |
-
2014
- 2014-04-08 CN CN201410139010.3A patent/CN103928510A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5907462A (en) * | 1994-09-07 | 1999-05-25 | Texas Instruments Incorporated | Gate coupled SCR for ESD protection circuits |
| US5528188A (en) * | 1995-03-13 | 1996-06-18 | International Business Machines Corporation | Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier |
| US20030067039A1 (en) * | 2001-10-10 | 2003-04-10 | Shin Su | Electrostatic discharge protection structure |
| US6911679B1 (en) * | 2003-01-09 | 2005-06-28 | National Semiconductor Corp. | LVTSCR with compact design |
| CN103094322A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Groove type insulated gate field-effect tube structure capable of being used for electrostatic protection |
Non-Patent Citations (1)
| Title |
|---|
| MING-DOU KER ET AL: "Overview of On-Chip Electrostatic Discharge Protection Design With SCR-Based Devices in CMOS Integrated Circuits", 《IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332493A (en) * | 2014-09-03 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator device and electrostatic protection device structure formed thereby |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101290933B (en) | Electrostatic discharge protection device | |
| US10447033B2 (en) | High holding voltage clamp | |
| CN108701693A (en) | There is the embedded PMOS- triggering silicon controlled rectifier (SCR)s (SCR) for inhibiting ring for static discharge (ESD) protection | |
| KR101944189B1 (en) | Electrostatic Discharge Protection Device | |
| CN108807372B (en) | Low-voltage trigger high-holding-voltage silicon controlled rectifier electrostatic discharge device | |
| US8633543B2 (en) | Electro-static discharge protection circuit and semiconductor device | |
| CN108461491B (en) | Low-trigger bidirectional silicon controlled electrostatic protection device with high maintenance voltage | |
| CN110335866B (en) | Bidirectional low-trigger ESD (electro-static discharge) protection device based on nanoscale integrated circuit process | |
| CN105655325A (en) | Electrostatic discharge protection circuit, and electrostatic discharge protection structure and manufacturing method thereof | |
| TWI409938B (en) | Electrostatic discharge (esd) protection circuit | |
| CN110323207B (en) | SCR device for low-voltage protection | |
| CN103165600A (en) | Electro-static discharge (ESD) protective circuit | |
| TWI521824B (en) | Electrostatic discharge protection circuit and voltage regulator chip having the same | |
| US9991253B2 (en) | Protection element, protection circuit, and semiconductor integrated circuit | |
| CN108400578B (en) | High-voltage ESD protection circuit | |
| JP6398696B2 (en) | Electrostatic protection circuit and semiconductor integrated circuit device | |
| CN102315258B (en) | Parasitic thyristor and electrostatic protection circuit | |
| CN108987393B (en) | Bidirectional ESD structure for protecting power integrated circuit output LDMOS device | |
| CN103094278A (en) | Positive channel metal oxide semiconductor (PMOS) embedded low-voltage trigger silicon controlled rectifier (SCR) device for electro-static discharge (ESD) protection | |
| Lai et al. | PNP-eSCR ESD protection device with tunable trigger and holding voltage for high voltage applications | |
| CN102693980A (en) | Silicon controlled rectifier electro-static discharge protection structure with low trigger voltage | |
| CN102938403B (en) | Low-voltage trigger SCR (silicon controlled rectifier) device used for ESD (electron static discharge) protection | |
| KR20110097506A (en) | Hybride protection device for esd and eos | |
| CN103928510A (en) | Silicon controlled rectifier and layout structure thereof | |
| CN102315259B (en) | Parasitic thyristor and electrostatic protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140716 |
|
| RJ01 | Rejection of invention patent application after publication |