CN103928306A - Forming method of double-metal grid structure, and CMOS transistor - Google Patents
Forming method of double-metal grid structure, and CMOS transistor Download PDFInfo
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- CN103928306A CN103928306A CN201310009244.1A CN201310009244A CN103928306A CN 103928306 A CN103928306 A CN 103928306A CN 201310009244 A CN201310009244 A CN 201310009244A CN 103928306 A CN103928306 A CN 103928306A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 137
- 239000002184 metal Substances 0.000 title claims abstract description 137
- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000011248 coating agent Substances 0.000 claims description 41
- 238000000576 coating method Methods 0.000 claims description 41
- 230000009977 dual effect Effects 0.000 claims description 40
- 230000015572 biosynthetic process Effects 0.000 claims description 31
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 19
- 239000000243 solution Substances 0.000 claims description 17
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 12
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 9
- 239000000428 dust Substances 0.000 claims description 9
- 239000011259 mixed solution Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 8
- 229910004200 TaSiN Inorganic materials 0.000 claims description 6
- 229910010037 TiAlN Inorganic materials 0.000 claims description 5
- 229910008482 TiSiN Inorganic materials 0.000 claims description 5
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 abstract description 32
- 230000004888 barrier function Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 217
- 229910004166 TaN Inorganic materials 0.000 description 21
- 239000000463 material Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 11
- 230000007547 defect Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 9
- 229910021645 metal ion Inorganic materials 0.000 description 9
- 239000007800 oxidant agent Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 230000001590 oxidative effect Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 230000002000 scavenging effect Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910004129 HfSiO Inorganic materials 0.000 description 3
- 229910006501 ZrSiO Inorganic materials 0.000 description 3
- WOIHABYNKOEWFG-UHFFFAOYSA-N [Sr].[Ba] Chemical compound [Sr].[Ba] WOIHABYNKOEWFG-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052593 corundum Inorganic materials 0.000 description 3
- 238000001764 infiltration Methods 0.000 description 3
- 230000008595 infiltration Effects 0.000 description 3
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- 229910017150 AlTi Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- -1 high gate resistance Inorganic materials 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000016507 interphase Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001460 tantalum ion Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a forming method of a double-metal grid structure, and a CMOS transistor. After an etching barrier layer on a semiconductor substrate is formed, an oxide layer of the etching barrier layer is formed on the surface of the etching barrier layer, and then a first metal layer is deposited. The oxide layer of the etching barrier layer can effectively prevent mutual effects such as atom diffusion and the like between the first metal layer and the etching barrier layer, it is ensured that the portion of the first metal layer disposed at a second area can be depleted without taking an over-etching mode, at the time when an etching step is simplified, the thickness of the etching barrier layer can be ensured in subsequently formed PMOS and NMOS metal gates, the possibility that metal gate ions filter into a high-K dielectric layer and even a transistor FET area of the substrate is reduced, and the electrical performance of an integrated circuit is guaranteed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the formation method of dual metal gate structure and the CMOS transistor that utilizes the method to form in a kind of CMOS of being applied in transistor.
Background technology
Develop rapidly along with integrated circuit (be called for short IC) manufacturing technology, especially enters behind sub-micro characteristic size field, and traditional integrated circuit size is constantly dwindled, and (is generally SiO as channel length in MOS transistor and gate oxide
2) after thickness is scaled, aggravated the loss of polysilicon, high gate resistance, and alloy (such as boron) is penetrated into the channel region of device and causes the defects such as grid leakage current increase.Some high K(dielectric constant for this reason) dielectric substance replaces traditional SiO
2can effectively reduce grid and reveal, but polysilicon and high-k dielectrics material and polysilicon are incompatible, therefore in present integrated circuit, mostly adopt metal gate electrode to replace polygate electrodes, and obtain good effect.
In dual metal gate structure, NMOS and the different metal gates of the general employing of PMOS, PMOS adopts the metal (being called for short PMOS workfunction metal) have close to the work function of the valence band of silicon, and NMOS adopts the metal (being called for short NMOS workfunction metal) having close to the work function of the conduction band of silicon.In dual metal gate structure preparation process, generally, after having deposited high K dielectric layer, cover one deck etch stop layer and carry out successively again PMOS workfunction metal deposition, etching, NMOS workfunction metal deposition, to form NMOS grid and PMOS grid.If international publication number is the formation technique that application documents that WO2004/095527, China Patent Publication No. are CN101661904A have all been introduced different dual metal gate structures.
In practical operation technique, after having deposited at PMOS workfunction metal, in order to ensure the PMOS workfunction metal of removing completely on territory, substrate nmos area, in the PMOS workfunction metal etching process on territory, substrate nmos area, mostly adopt over etching technique, so directly reduced etch stop layer thickness, thereby may cause in the infiltration high k dielectric layer of NMOS workfunction metal ion, even infiltrate in transistor FET region, thereby cause grid leakage current and power consumption to increase.
For this reason, the metal nitride that generally selection and PMOS workfunction metal and NMOS workfunction metal etching selectivity are larger is as the etch stop layer of their bottoms, to guarantee the integrality of etch stop layer.Yet, even if find to adopt similar etch stop layer to be still difficult to guarantee the performance of device in actual production, such as the excessive defect of grid leakage current still often occurs.
Summary of the invention
In order to address the above problem, the invention provides a kind of formation method and COMS transistor of dual metal gate structure, it can effectively reduce grating of semiconductor element leakage current and increase defect, thereby improves the electrical properties of semiconductor device.
The formation method of a kind of dual metal gate structure provided by the present invention, comprising:
The Semiconductor substrate with first area and second area is provided, in described Semiconductor substrate, covers successively from the bottom to top high k dielectric matter layer and etch stop layer;
On described etch stop layer surface, form the oxide skin(coating) of etch stop layer;
On the oxide skin(coating) of described etch stop layer, deposit the first metal layer;
Removal is positioned at the described the first metal layer of described second area;
On remaining described the first metal layer and second area, deposit the second metal level.
Alternatively, described first area is PMOS region, and described second area is territory, nmos area.
Alternatively, described etch stop layer is TaN layer or TaSiN layer.
Alternatively, the thickness of described etch stop layer is 10 ~ 50 dusts.
Alternatively, described the first metal layer is PMOS workfunction layers.
Alternatively, described PMOS workfunction layers is TiN layer, TiAlN layer or TiSiN layer.
Alternatively, the thickness of described the first metal layer is 10 ~ 100 dusts.
Alternatively, the oxide skin(coating) that forms described etch stop layer comprises, adopts ozone solution or hydrogen peroxide solution to clean described etch stop layer surface, forms the oxide skin(coating) of described etch stop layer to be oxidized described etch stop layer surface.
Alternatively, described ozone solution or the concentration of hydrogen peroxide solution are 20 ~ 100ppm.
Alternatively, adopt described ozone solution or hydrogen peroxide solution to continue to clean described etch stop layer 10 ~ 100s.
Alternatively, adopt described ozone solution or hydrogen peroxide solution to clean described etch stop layer at 20 ℃ ~ 100 ℃ temperature.
Alternatively, the thickness of the oxide skin(coating) of described etch stop layer is 1 ~ 6 dust.
Alternatively, adopt wet chemical etch method to remove the described the first metal layer that is positioned at described second area.
Alternatively, adopt NH
3.H
2o and H
2o
2mixed solution implement described wet chemical etch.
Alternatively, in described mixed solution, V (NH
3.H
2o): V (H
2o
2): V (H
2o) be 1:2:50 to 1: 1:5.
Alternatively, described wet chemical etch is carried out at 25 ℃ ~ 100 ℃.
The present invention provides again a kind of CMOS transistor, comprising: build on PMOS transistor and nmos pass transistor on same substrate;
Described PMOS transistor comprises high k dielectric matter layer, etch stop layer, the oxide skin(coating) that is positioned at the etch stop layer on described etch stop layer surface, PMOS workfunction layers from the bottom to top successively;
Described nmos pass transistor comprises high k dielectric matter layer, etch stop layer, the oxide skin(coating) that is positioned at the etch stop layer on described etch stop layer surface, NMOS workfunction layers from the bottom to top successively.
Alternatively, described etch stop layer is TaN layer or TaSiN layer.
Alternatively, described PMOS workfunction layers is TiN layer, TiAlN layer or TiSiN layer.
Alternatively, the thickness of described PMOS workfunction layers is 10 ~ 100 dusts; The thickness of the oxide skin(coating) of described etch stop layer is 1 ~ 6 dust.
Compared with prior art, the present invention mainly has the following advantages:
The formation method of a kind of dual metal gate structure of the present invention is after described etch stop layer forms, on described etch stop layer surface, form the oxide skin(coating) of one deck etch stop layer, deposit again afterwards one deck the first metal layer, the oxide skin(coating) of described etch stop layer can effectively stop between the first metal layer and described etch stop layer and occur the interactions such as atom diffusion, not only guarantee without taking the just divisible the first metal layer that is positioned at second area part of over etching mode, simplify etching step simultaneously, in the PMOS and NMOS metal gates of follow-up formation, guarantee the thickness of etch stop layer, reduce metal gate ion and infiltrate the even possibility in the transistor FET region of substrate of high k dielectric matter layer, and cause making the defect that integrated circuit electricity leakage stream and power consumption sharply increase, guarantee integrated circuit electric property.
And in CMOS transistor provided by the invention, the oxide skin(coating) of the etch stop layer between etch stop layer and PMOS/NMOS workfunction layers can effectively stop metal gate iontophoretic injection in PMOS/NMOS workfunction layers in the described infiltration high k dielectric matter layer possibility in the transistor FET region of substrate even, and cause making the defect that integrated circuit electricity leakage flows and power consumption sharply increases, guarantee integrated circuit electric property.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately by actual size equal proportion convergent-divergent, do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the schematic flow sheet of the formation method of existing a kind of dual metal gate structure;
Fig. 2 a ~ 2d is the schematic flow sheet of the formation method of embodiments of the invention dual metal gate structure;
Fig. 3 is electric capacity (C) ~ voltage (V) resolution chart of the dual metal gate structure that forms of the formation method of embodiments of the invention dual metal gate structure;
Fig. 4 is electric current (A) ~ voltage (V) resolution chart of the dual metal gate structure that forms of the formation method of embodiments of the invention dual metal gate structure;
Fig. 5 is the structural representation of CMOS transistor embodiment of the present invention.
Embodiment
From background technology, in semiconductor alloy preparation technology, even if select and PMOS workfunction metal and the larger metal nitride of the NMOS workfunction metal etching selectivity etch stop layer as their bottoms, as common, take TiN during as PMOS workfunction metal, TaN or TaSiN are conventional barrier material, in the hope of guaranteeing to retain after PMOS workfunction metal and the etching of NMOS workfunction metal the etch stop layer of adequate thickness, still can be difficult to avoid occurring the excessive phenomenon of grid leakage current occurs, thereby cause the defect of the electric property of semiconductor device.
Inventor finds after further investigation, and in semiconductor preparing process, PMOS workfunction metal (with NMOS workfunction metal) easily and metal nitride effect, and forms the doped layer of metal between both interfaces.Its particularly can with reference to figure 1 for example shown in, in Semiconductor substrate 10, form successively high k dielectric layer 11 and TaN layer 12, and after the TiN layer 13 covering as PMOS workfunction metal at TaN layer 12, on TiN layer 13 and the stacked interface of TaN layer 12, be prone to atom diffusion phenomena, form metal-doped layer 14(TaTiN layer).And at the PMOS workfunction metal of removing territory, Semiconductor substrate nmos area part during with deposition NOMS workfunction layers 15, described metal-doped layer 14 is less with the etching selectivity of described PMOS workfunction metal, it can be completely removed, and in actual etch process, also cannot stop etched carrying out.Thereby TaN layer 12 thickness as etch stop layer have been reduced in fact equally.And after follow-up PMOS and NMOS metal gates form, workfunction metal in PMOS in metal gates and NMOS grid continues to occur to interact and reduced etch stop layer thickness at the interface of itself and etch stop layer, therefore and occur that PMOS and NMOS workfunction metal ion infiltrate high k dielectric matter layer even in the transistor FET region of substrate, cause leakage current and integrated circuit work function sharply to increase, and cause the electric property defect of integrated circuit.
For above-mentioned defect, the invention provides a kind of formation method of dual metal gate structure.Shown in figure 2a ~ 2d, the formation method of described dual metal gate structure comprises, semi-conductive substrate 100 is first provided, and described Semiconductor substrate 100 can be the silicon substrate on silicon substrate, silicon-containing substrate or insulator.In the surperficial predefine of described Semiconductor substrate 100, be used to form first area and the second area of PMOS transistor and nmos pass transistor, in described Semiconductor substrate, between described first area and second area correspondence position, be formed for the shallow trench (STI) 101 of electrical isolation first area and second area.For convenience of description, now described first area is defined as to PMOS region corresponding to the follow-up PMOS transistor of making, and second area is corresponding territory, nmos area.
In described Semiconductor substrate 100, cover successively from the bottom to top high k dielectric matter layer 110 and etch stop layer 120.Afterwards, adopt the etch stop layer 120 as described in the oxidizing agent solution oxidations such as ozone solution or hydrogen peroxide solution of debita spissitudo, to form the oxide skin(coating) 121 of one deck etch stop layer on described etch stop layer 120 surfaces.And at oxide skin(coating) 121 surface deposition one deck PMOS workfunction metals (i.e. the first workfunction metal) of described etch stop layer.And then adopt the techniques such as etching to remove after the PMOS workfunction metal in territory, nmos area, at nmos area area deposition NMOS workfunction metal (i.e. the second workfunction metal).Carry out again afterwards as to PMOS workfunction metal, the further etching of NMOS workfunction metal, and the side wall of PMOS, NMOS grid the subsequent handling such as prepares to complete PMOS, the preparation of NMOS grid.
Described high k dielectric matter layer 11 can comprise alundum (Al2O3) (Al
2o
3), barium strontium (BST), lead zirconate titanate (PZT), ZrSiO
2, HfSiO
2, HfSiON, TaO
2and HfO
2deng the material with high dielectric constant.Described PMOS workfunction layers comprises having close to the work function of the valence band of silicon, as the material of the metal ions such as hafnium, zirconium, tantalum, titanium; NMOS workfunction layers comprises having close to the work function of the conduction band of silicon, as platinum, nickel, ruthenium, pan, aluminium with and the material of the metal ion such as combination.In the existing preparation technology of double-metal grid system, described etch stop layer is arranged at described PMOS workfunction layers and NMOS workfunction layers below, described barrier material has higher etching ratio with PMOS workfunction layers and NMOS workfunction layers, if TiN is the PMOS workfunction metal layer material generally using now, and NH
3.H
2o and H
2o
2mixed solution be conventional Wet-etching agent, the TaN that corresponding and TiN have a larger etching ratio is that the most frequently used barrier material is (at normal temperatures, with NH
3.H
2o and H
2o
2mixed solution be etchant, the etch-rate ratio of TiN and TaN is over 30 times), after etching PMOS workfunction layers and NMOS workfunction layers complete, etch stop layer can stop used etchant further to permeate etching, thereby each layer of structure of over etching PMOS workfunction layers and NMOS workfunction layers below, destroys integrated circuit chip structure and destroys.
Yet in actual use, in metal ion in PMOS workfunction layers (titanium ion in as TiN) and etch stop layer, metal ion (as the tantalum ion in TaN) forms the doped layer of metal in the combination interface interphase interaction of TiN layer and TaN layer.And before NMOS workfunction layers deposition, while removing this PMOS workfunction layers in territory, nmos area, need the excessive PMOS workfunction metal (and the etch-rate of the doped layer of described metal is really also very large, it cannot stop that etch process carries out) that eliminates this part that be etched with.So directly reduced the thickness of etch stop layer.And at the PMOS in PMOS region workfunction layers and etch stop layer interface, form equally the doped layer of metal, it has reduced etch stop layer thickness equally, thereby may cause in the infiltration high k dielectric layer of the PMOS workfunction metal of PMOS and nmos pass transistor and the ion of NMOS workfunction metal, even infiltrate in transistor FET region, thereby cause gate leakage currents and power consumption to increase.And in the present invention, on described etch stop layer surface, form after the oxide skin(coating) of one deck etch stop layer, can effectively stop between PMOS workfunction layers and NMOS workfunction layers and described etch stop layer and occur the interactions such as atom diffusion, not only guarantee without taking over etching mode just divisible as in the PMOS of NOMS area part metal work function, simplify etching step simultaneously, in the PMOS and NMOS metal gates of follow-up formation, guarantee the thickness of etch stop layer, reduce PMOS and NMOS workfunction metal and infiltrate the even possibility in the transistor FET region of substrate of high k dielectric matter layer, thereby the defect that the integrated circuit electricity leakage that overcomes so cause stream and power consumption sharply increase, guarantee integrated circuit electric property.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the profile that represents device architecture can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
For ease of describing, in the present embodiment, using PMOS region as first area, territory, nmos area is as second area, and corresponding PMOS workfunction layers is as the first metal layer, and NMOS workfunction layers is as the second metal level.And in practical operation; also can territory, nmos area as first area, PMOS region is as second area, and corresponding PMOS workfunction layers is as the second metal level; and NMOS workfunction layers is as the first metal layer, these simply change all in protection scope of the present invention.
The forming process of dual metal gate structure:
Shown in figure 2a, the formation method of a kind of dual metal gate structure of the present embodiment comprises:
Step S1, first provides the Semiconductor substrate 100 with PMOS region and territory, nmos area, and covers successively from the bottom to top one deck high k dielectric matter layer 110 and etch stop layer 120 in described Semiconductor substrate 100.
Described high k dielectric layer 110 comprises alundum (Al2O3) (Al
2o
3), barium strontium (BST), lead zirconate titanate (PZT), ZrSiO
2, HfSiO
2, HfSiON, TaO
2and HfO
2in any.Described etch stop layer 120 preferably adopts TaN.The thickness of the described TaN as etch stop layer is 10 ~ 50 dusts.As 10 dusts, 15 dusts, 20 dusts, 30 dusts, 40 dusts, 50 dusts.If described TaN layer is blocked up, it can affect the size of integrated circuit, and if described TaN layer is excessively thin, cannot effectively play and stop that etching and follow-up prevention PMOS and NMOS workfunction metal infiltrate through the effect of described high k dielectric matter layer 110.Specifically big or small as for it, can determine according to technique actual needs.
Step S2, in conjunction with reference to shown in figure 2a, cleans described etch stop layer 120 surfaces with oxidant, is oxidized described etch stop layer 120, to form the oxide skin(coating) 121 of one deck etch stop layer on described etch stop layer 120 surfaces.
Particularly, take the ozone (O that concentration is 20 ~ 100ppm
3) solution cleans described 10 ~ 100 seconds, 120 surface of etch stop layer (s) at 20 ℃ ~ 100 ℃ temperature, thereby form thickness, is the oxide skin(coating) 121(TaON layer of the etch stop layer of 1 ~ 6 dust), as 1 dust, 2 dusts, 3 dusts, 4 dusts, 5 dusts and 6 dusts.
If described TaN120 is excessively oxidated, the oxide skin(coating) 121 of the etch stop layer forming is blocked up, reduce accordingly TaN layer 120 thickness, if oxidation dynamics is inadequate, cannot form the TaON layer 121 of suitable thickness effectively to stop the interaction of TaN layer and TiN interlayer.In actual mechanical process, the concentration of oxidant, the temperature of cleaning and scavenging period are corresponding.The concentration of described ozone solution is specially 20,25,30,35 ... 90,95, the numerical value within the scope of the 20 ~ 100ppm such as 100ppm, temperature comprises 20,25,30,35 ... 90, the numerical value within the scope of 95,100 ℃ etc. 20 ~ 100 ℃, and the time of cleaning also can be as 10,20,30 ... 10 ~ the 100s such as 100s any point.In practical operation, as at identical temperature, if oxidant concentration is higher, its scavenging period is corresponding reducing; During the oxidant of same concentrations is used, cleaning temperature is higher, and scavenging period is corresponding reduces; Under identical scavenging period is set, cleaning temperature is higher, corresponding the reducing of oxidant concentration of selecting.
Step S3 in conjunction with reference to shown in figure 2b, deposits PMOS workfunction layers 130 on the oxide skin(coating) 121 of described etch stop layer.Described PMOS workfunction layers 130 covers described PMOS region and territory, nmos area simultaneously.
Particularly, described PMOS workfunction layers 130 is TiN layer, its can by adopt technique as applicable in chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic deposition (ALD) or spin-on dielectric technique (SOD) etc. as described in form TiN layer on the oxide skin(coating) 121 of etch stop layer.The thickness of described TiN layer is 10 ~ 100 dusts, as 10,15,20,25,30 ... 90,95,100 dusts.
Step S4, in conjunction with reference to shown in figure 2c, removes all described PMOS workfunction layers that are positioned at territory, described nmos area part.
Particularly, can above described PMOS workfunction layers 130, form one deck and cover layer 150, as PR(photo resist, photoresists) and take that it carries out etching as mask, retain the described PMOS workfunction layers 1301 that is positioned at described PMOS region, remove the described PMOS workfunction layers that is positioned at territory, described nmos area part.And etch process preferably adopts with NH
3.H
2o and H
2o
2mixed solution be etchant, at 25 ℃ ~ 100 ℃ temperature, carry out wet chemical etch technique, to remove, be positioned at the described PMOS workfunction layers of territory, described nmos area part, until expose the oxide skin(coating) 121 of the described etch stop layer that is positioned at territory, described nmos area part.
NH
3.H
2o and H
2o
2mixed solution in, V (NH
3.H
2o): V (H
2o
2): V (H
2o) between between 1:2:50 ~ 1:1:5, as 1:1:5,1:1:10,1:1.30,1:1.3:5,1:1.5:10,1:1.8.10,1:2:20,1:2:40,1:2:45,1:2:50 etc.The experiment proved that, adopt in the etch process of above-mentioned condition, the oxide skin(coating) 121(TaON of described etch stop layer) with described PMOS workfunction layers 130 for the NH of above-mentioned concentration proportioning
3.H
2o and H
2o
2mixed solution there is very high etching selectivity; thereby in etch process; when the described PMOS workfunction layers of guaranteeing territory, described nmos area part is removed completely; needn't worry the problem of over etching, it has intactly retained the oxide skin(coating) 121(TaON of described etch stop layer) (as shown in Figure 2 c) its protected equally the thickness of the etch stop layer 120 of oxide skin(coating) 121 belows that are positioned at described etch stop layer.
Step S5, in conjunction with reference to shown in figure 2d, after eliminating the described PMOS workfunction layers of territory, described nmos area part, removal is positioned at the coverage layer 150 of remaining PMOS workfunction layers 1301 tops, and deposits one deck NMOS workfunction layers 160 on remaining described PMOS workfunction layers (being positioned at the described PMOS workfunction layers 1301 of described PMOS area part) top and territory, nmos area.
The material of described NMOS workfunction layers 160 specifically can be AlTi.And described depositing operation can adopt technique as applicable in chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic deposition (ALD) or spin-on dielectric technique (SOD) etc. to realize equally.
After described NMOS workfunction layers 160 has deposited, again adopt the techniques such as wet etching as required etching remove unnecessary described PMOS workfunction layers 1301 and NMOS workfunction layers 160 and form PMOS transistor gate pattern and nmos pass transistor gate patterns, and carry out grid curb wall and set up technique, to form corresponding PMOS grid and NMOS grid.These subsequent techniques all can adopt existing technique to realize, and do not repeat them here.
CMOS transistor examples
The present invention also provides a kind of CMOS transistor that comprises above-mentioned dual metal gate structure, and its specific embodiment structure can be in conjunction with reference to shown in figure 5.
Described CMOS transistor comprises PMOS transistor 200 and the nmos pass transistor 300 building in same semi-conductive substrate 100.
Described PMOS transistor 200 comprises successively from the bottom to top high k dielectric matter layer 201, etch stop layer 202, is positioned at oxide skin(coating) 203 and the PMOS workfunction layers 204 of the etch stop layer on described etch stop layer 202 surfaces.Described nmos pass transistor 300 comprises successively from the bottom to top high k dielectric matter layer 301, etch stop layer 302, is positioned at oxide skin(coating) 303, the NMOS workfunction layers 304 of the etch stop layer on described etch stop layer 302 surfaces.
Described high k dielectric matter layer 201 and 202 can be alundum (Al2O3) (Al
2o
3), barium strontium (BST), lead zirconate titanate (PZT), ZrSiO
2, HfSiO
2, HfSiON, TaO
2and HfO
2in any, and described high k dielectric matter layer 201 and high k dielectric matter layer 202 can be that same material also can make material in difference.Described PMOS workfunction metal adopts different materials to make from NMOS workfunction metal, and described PMOS workfunction metal preferably adopts TiN, and described NMOS workfunction metal can adopt the materials such as AlTiN, AlTi.The thickness of described PMOS workfunction layers 204 and NMOS workfunction layers 304 is 10 ~ 100 dusts.
And described etch stop layer 202 and 302 preferably with PMOS workfunction metal and the larger metal nitride of NMOS workfunction metal employing etching selectivity, be wherein particularly preferably TaN.Now, the oxide skin(coating) (TaON) that the oxide skin(coating) 203 of the etch stop layer of described PMOS transistor 200 and nmos pass transistor 300 and 303 are TaN, its thickness is 1 ~ 6 dust, as 1 dust, 2 dusts, 3 dusts, 4 dusts, 5 dusts and 6 dusts.
The oxide skin(coating) 203 of the described etch stop layer of PMOS transistor 200 and nmos pass transistor 300 and 303 can adopt oxidant in specific condition (temperature and scavenging period) thereby the described etch stop layer of lower cleaning obtains, this step is described emphatically in above-mentioned " forming process of dual metal gate structure ", does not repeat them here.
Oxide skin(coating) 203 and 303 metal ions that can effectively intercept PMOS workfunction metal and NMOS workfunction metal of the etch stop layer of the described CMOS transistor that the present embodiment provides between PMOS workfunction metal and NMOS workfunction metal and etch stop layer separately 202 and 302 infiltrate through the high k dielectric matter layer 201 and 301 below being positioned at separately, and the possibility in the transistor FET region of substrate, thereby and inhibition integrated circuit electricity leakage flows and the increase of power consumption, guarantees integrated circuit electric property.It should be noted that described PMOS and nmos pass transistor also comprise grid curb wall, each self-corresponding source, drain electrode structure and well region structure etc., these structures are all the technology of knowing of this area, do not repeat them here.
The performance test of the dual metal gate structure forming:
Embodiment: the dual metal gate structure that adopts the oxide skin(coating) that has comprised etch stop layer prepared by above-mentioned " forming process of dual metal gate structure ".
Comparative example: comprise substrate same as the previously described embodiments, high k dielectric matter layer, PMOS workfunction layers and NMOS workfunction layers and identical preparation technology, but do not comprise the dual metal gate structure of the oxide skin(coating) of above-mentioned etch stop layer.
Under identical experiment condition, carry out the test of electric capacity (C) ~ voltage (V) and leakage current (A) ~ voltage (V), its test pattern is as shown in reference to figure 3 and Fig. 4, shown in (data and curves that wherein triangle number is comparative example according to (w/o03treatment), the data and curves that rhombus data (w/i03treatment) are embodiment) its data result reference table 1.
The test result of table 1. electric capacity (C) ~ voltage (V), leakage current (A) ~ voltage (V)
| ? | Embodiment | Comparative example |
| EOT(A) | 8.70 | 11.56 |
| Leakage(A/um 2)@-1V | 4.31E-11 | 2.16E-10 |
Test condition: test voltage :-2 ~+1v; Frequency: 1 megahertz
EOT(A): equivalent oxide thickness, full name: equipment oxide thickness, the A of unit: dust Leakage(A)@-1V: leakage current-voltage, unit: electric current A/um
2: ampere; Voltage V: volt
As shown in Table 1, in the present embodiment, between described PMOS workfunction metal (NMOS workfunction metal) and etch stop layer, form after the oxide skin(coating) of etch stop layer, can effectively reduce leakage phenomenon occurs, analyze its reason mainly: the oxide skin(coating) of etch stop layer has effectively reduced metal ion in PMOS workfunction metal (NMOS workfunction metal) and diffused into the transistor FET region of described high k dielectric matter layer and substrate downwards, thereby has effectively reduced phenomenon of gate leakage.
In conventional technology, can be by increasing etch stop layer thickness, (now EOT raises, and consequence is increase process complexity and increased integrated circuit yardstick) spreads downwards to have reduced metal ion in PMOS workfunction metal (NMOS workfunction metal).But as shown in Table 1,, than comparative example, the present embodiment, reducing leakage phenomenon appearance simultaneously, also effectively reduces EOT numerical value.Thereby its protection for leakage current and the downsizing of semiconductor preparation size all significant.
It should be noted that in the above-described embodiments, take TiN as PMOS workfunction metal, TaN is barrier material, and take ozone solution as oxidant, and it has comparatively typical effect, thereby can set forth better technical scheme of the present invention, not the present invention is done to any pro forma restriction.In the present invention, described PMOS workfunction metal is not limited to TiN, and as also having TiAlN, TiSiN etc., and etch stop layer is also not limited to TaN, also as TaSiN etc.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (20)
1. a formation method for dual metal gate structure, is characterized in that, comprising:
The Semiconductor substrate with first area and second area is provided, in described Semiconductor substrate, covers successively from the bottom to top high k dielectric matter layer and etch stop layer;
On described etch stop layer surface, form the oxide skin(coating) of etch stop layer;
On the oxide skin(coating) of described etch stop layer, deposit the first metal layer;
Removal is positioned at the described the first metal layer of described second area;
On remaining described the first metal layer and second area, deposit the second metal level.
2. the formation method of dual metal gate structure according to claim 1, is characterized in that, described first area is PMOS region, and described second area is territory, nmos area.
3. the formation method of dual metal gate structure according to claim 1, is characterized in that, described etch stop layer is TaN layer or TaSiN layer.
4. the formation method of dual metal gate structure according to claim 1, is characterized in that, the thickness of described etch stop layer is 10 ~ 50 dusts.
5. the formation method of dual metal gate structure according to claim 2, is characterized in that, described the first metal layer is PMOS workfunction layers.
6. the formation method of dual metal gate structure according to claim 5, is characterized in that, described PMOS workfunction layers is TiN layer, TiAlN layer or TiSiN layer.
7. the formation method of dual metal gate structure according to claim 1, is characterized in that, the thickness of described the first metal layer is 10 ~ 100 dusts.
8. the formation method of dual metal gate structure according to claim 1, it is characterized in that, the oxide skin(coating) that forms described etch stop layer comprises, adopt ozone solution or hydrogen peroxide solution to clean described etch stop layer surface, to be oxidized described etch stop layer surface, form the oxide skin(coating) of described etch stop layer.
9. the formation method of dual metal gate structure according to claim 8, is characterized in that, the concentration of described ozone solution or hydrogen peroxide solution is 20 ~ 100ppm.
10. the formation method of dual metal gate structure according to claim 9, is characterized in that, adopts described ozone solution or hydrogen peroxide solution to continue to clean described etch stop layer 10 ~ 100s.
The formation method of 11. dual metal gate structures according to claim 10, is characterized in that, adopts described ozone solution or hydrogen peroxide solution to clean described etch stop layer at 20 ℃ ~ 100 ℃ temperature.
The formation method of 12. dual metal gate structures according to claim 11, is characterized in that, the thickness of the oxide skin(coating) of described etch stop layer is 1 ~ 6 dust.
The formation method of 13. dual metal gate structures according to claim 1, is characterized in that, adopts wet chemical etch method to remove the described the first metal layer that is positioned at described second area.
The formation method of 14. dual metal gate structures according to claim 13, is characterized in that, adopts NH
3.H
2o and H
2o
2mixed solution implement described wet chemical etch.
The formation method of 15. dual metal gate structures according to claim 14, is characterized in that, in described mixed solution, and V (NH
3.H
2o): V (H
2o
2): V (H
2o) be 1:2:50 to 1:1:5.
The formation method of 16. dual metal gate structures according to claim 15, is characterized in that, described wet chemical etch is carried out at 25 ℃ ~ 100 ℃.
17. 1 kinds of CMOS transistors, is characterized in that, comprise the PMOS transistor and the nmos pass transistor that build on same substrate;
Described PMOS transistor comprises high k dielectric matter layer, etch stop layer, the oxide skin(coating) that is positioned at the etch stop layer on described etch stop layer surface, PMOS workfunction layers from the bottom to top successively;
Described nmos pass transistor comprises high k dielectric matter layer, etch stop layer, the oxide skin(coating) that is positioned at the etch stop layer on described etch stop layer surface, NMOS workfunction layers from the bottom to top successively.
18. CMOS transistors according to claim 17, is characterized in that, described etch stop layer is TaN layer or TaSiN layer.
19. CMOS transistors according to claim 17, is characterized in that, described PMOS workfunction layers is TiN layer, TiAlN layer or TiSiN layer.
20. CMOS transistors according to claim 17, is characterized in that, the thickness of described PMOS workfunction layers is 10 ~ 100 dusts; The thickness of the oxide skin(coating) of described etch stop layer is 1 ~ 6 dust.
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