CN103915049A - Amorphous silicon gate drive scanning circuit and circuit unit thereof, and flat panel display - Google Patents
Amorphous silicon gate drive scanning circuit and circuit unit thereof, and flat panel display Download PDFInfo
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- CN103915049A CN103915049A CN201310178786.1A CN201310178786A CN103915049A CN 103915049 A CN103915049 A CN 103915049A CN 201310178786 A CN201310178786 A CN 201310178786A CN 103915049 A CN103915049 A CN 103915049A
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Abstract
The invention discloses an ASG scanning circuit unit, an ASG scanning circuit and a flat panel display in order to achieve the purposes of automatically resetting the ASG scanning circuit unit, reducing the area of the ASG scanning circuit unit, and improving stability of the scanning circuit. The ASG scanning circuit unit comprises an automatic reset signal generating unit, a pull-down control signal generating unit, a pull-down output unit, a pull-up control signal generating unit and a pull-up output unit. The automatic reset signal generating unit is used for generating reset signals through a thin film transistor; the pull-down control signal generating unit receives the reset signals and generates pull-down control signals according to the reset signals; the pull-down output unit receives the control signals and enables output signals of the circuit unit to be in low level according to control of the pull-down control signals; the pull-up control signal generating unit generates pull-up control signals according to control of the pull-down control signals; the pull-up output unit receives the pull-up control signals and enables the output signals of the circuit unit to be in high level according to control of the pull-up control signals.
Description
Technical field
The present invention relates to sweep circuit technical field, relate in particular to a kind of amorphous silicon gate could and drive (Amorphous Silicon Gate, ASG) sweep circuit unit, ASG sweep circuit and flat-panel monitor.
Background technology
The 7T2C amorphous silicon gate could being made up of 7 transistor Ts 0, T1, T2, T3, T4, T5, T6 and 2 electric capacity in prior art drives ASG sweep circuit as shown in Figure 1, Figure 2 shows that each signal sequence graph of a relation of this circuit.This circuit is realized the function of displacement scanning by upper rubbish (PU) signal, drop-down (PD) signal and clock signal cooperation.Wherein, PU signal is from the input of Q node, and PD signal is that described clock signal comprises inversion clock signal (CKB) and positive clock signal (CK) from the input of QB node.And in prior art there are two shortcomings below in ASG sweep circuit:
1. available circuit not only needs higher level's input signal to trigger but also need subordinate's output signal to reset, and there is no auto-reset function, thereby it is more to cause going between.
2. available circuit needs a larger coupling capacitance C1 to produce pulldown signal PD.Increase circuit area, improve circuit design difficulty.Another kind of the prior art is realized shift LD functionality scan circuit as shown in Figure 3 by transistor completely, and its each signal sequence relation as shown in Figure 4.Also there are two shortcomings below in this circuit:
1. not only need higher level's input signal to trigger but also need subordinate's input signal to reset, there is no auto-reset function, thereby it is more to cause going between.
Though 2., without electric capacity, need 17 transistor Ts 1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, too complicated.
In sum, ASG sweep circuit of the prior art does not have auto-reset function, goes between more.Need larger coupling capacitance to produce the circuit area of pulldown signal larger, circuit design acquires a certain degree of difficulty, and it is more complicated to realize the circuit design of shift LD function by transistor completely.
Summary of the invention
The embodiment of the present invention provides a kind of amorphous silicon gate could to drive ASG sweep circuit unit, ASG sweep circuit and flat-panel monitor, in order to realize automatically reseting of ASG sweep circuit unit, and reduces the area of ASG sweep circuit unit, improves sweep circuit stability.
A kind of ASG sweep circuit unit that the embodiment of the present invention provides comprises:
The signal generation unit that automatically resets, for by thin film transistor (TFT) generating reset signal;
Drop-down control signal generation unit, receives described reset signal, and according to the control of reset signal, generates drop-down control signal;
Drop-down output unit, receives described drop-down control signal, and according to the control of drop-down control signal, the output signal of described circuit unit is pulled to low level;
On draw control signal generation unit, for according to the control of described drop-down control signal, in generation, draw control signal;
On draw output unit, receive on described and draw control signal, and according to the control of above drawing control signal, the output signal of described circuit unit is pulled to high level.
A kind of amorphous silicon gate could that the embodiment of the present invention provides drives ASG sweep circuit, and this circuit comprises the foregoing circuit unit of multiple cascades, and wherein, the signal output part OUT of each circuit unit is connected with the signal input part IN of next stage circuit unit.
A kind of flat-panel monitor that the embodiment of the present invention provides, comprises above-mentioned ASG sweep circuit.
The ASG sweep circuit unit that the embodiment of the present invention provides comprises: for by the signal generation unit that automatically resets of thin film transistor (TFT) generating reset signal; Be used for receiving described reset signal, and according to the control of reset signal, generate the drop-down control signal generation unit of drop-down control signal; Be used for receiving described drop-down control signal, and according to the control of drop-down control signal, the output signal of described circuit unit be pulled to low level drop-down output unit; For according to the control of described drop-down control signal, in generation, draw control signal on draw control signal generation unit; Be used for receiving on described and draw control signal, and according to the control of above drawing control signal, by the output signal of described circuit unit be pulled to high level on draw output unit.Therefore, this ASG sweep circuit unit has auto-reset function, and can reduce the quantity of lead-in wire.This ASG sweep circuit unit produces drop-down control signal by the control of reset signal, does not need larger coupling capacitance to produce pulldown signal, thereby can reduce circuit area, reduces the design difficulty of circuit.In addition, with respect to the ASG sweep circuit unit being made up of 17 transistors in prior art, the embodiment of the present invention has reduced transistorized quantity in ASG sweep circuit unit, has simplified circuit design.
Accompanying drawing explanation
Fig. 1 is existing 7T2C ASG sweep circuit schematic diagram;
Fig. 2 is the work schedule schematic diagram of existing 7T2C ASG sweep circuit;
Fig. 3 is existing 16T ASG sweep circuit schematic diagram;
Fig. 4 is the work schedule schematic diagram of existing 16T ASG sweep circuit;
A kind of 9T3C ASG sweep circuit cell schematics that Fig. 5 provides for the embodiment of the present invention;
The work schedule schematic diagram of circuit unit shown in Fig. 5 that Fig. 6 provides for the embodiment of the present invention;
The work schedule schematic diagram of circuit unit shown in Fig. 5 that Fig. 7 provides for the embodiment of the present invention;
The another kind of 9T3C ASG sweep circuit cell schematics that Fig. 8 provides for the embodiment of the present invention;
The work schedule schematic diagram of circuit unit shown in Fig. 8 that Fig. 9 provides for the embodiment of the present invention;
Figure 10 adds the simulation result schematic diagram after load for the ASG sweep circuit unit of Fig. 5 that the embodiment of the present invention provides;
The ASG sweep circuit schematic diagram that Figure 11 provides for the embodiment of the present invention;
The ASG sweep circuit analog result schematic diagram that Figure 12 provides for the embodiment of the present invention.
Embodiment
The embodiment of the present invention provides a kind of amorphous silicon gate could to drive ASG sweep circuit unit, ASG sweep circuit and flat-panel monitor, in order to realize automatically reseting of ASG sweep circuit unit, and reduces the area of ASG sweep circuit unit, improves sweep circuit stability.
The technical scheme embodiment of the present invention being provided below in conjunction with accompanying drawing is described.
A kind of amorphous silicon gate could that the embodiment of the present invention provides drives ASG sweep circuit unit, and this circuit unit comprises:
The signal generation unit that automatically resets, for by thin film transistor (TFT) generating reset signal;
Drop-down control signal generation unit, receives described reset signal, and according to the control of reset signal, generates drop-down control signal;
Drop-down output unit, receives described drop-down control signal, and according to the control of drop-down control signal, the output signal of described circuit unit is pulled to low level;
On draw control signal generation unit, for according to the control of described drop-down control signal, in generation, draw control signal;
On draw output unit, receive on described and draw control signal, and according to the control of above drawing control signal, the output signal of described circuit unit is pulled to high level.
Wherein, all described thin film transistor (TFT)s are N-type thin film transistor (TFT) or P type thin film transistor (TFT).
In the time that all described thin film transistor (TFT)s are N-type thin film transistor (TFT), referring to Fig. 5, a kind of ASG sweep circuit unit that the embodiment of the present invention provides comprises: for by the signal generation unit 50 that automatically resets of thin film transistor (TFT) generating reset signal; Receive described reset signal, and according to the control of reset signal, generate the drop-down control signal generation unit 51 of drop-down control signal; Receive described drop-down control signal, and according to the control of drop-down control signal, the output signal of described ASG sweep circuit unit is pulled to low level drop-down output unit 52; For according to the control of described drop-down control signal, in generation, draw control signal on draw control signal generation unit 53; Receive on described and draw control signal, and according to the control of above drawing control signal, by the output signal of described ASG sweep circuit unit be pulled to high level on draw output unit 54.
Wherein, described in the signal generation unit 50 that automatically resets, comprising: the first film transistor M1, the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3 and the first capacitor C 1; Wherein, the grid of the first film transistor M1 is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth (source, drain electrode) connects respectively low level input end VEE and the first node N1 of described ASG sweep circuit unit; The grid of the second thin film transistor (TFT) M2 is connected with the inversion clock signal CKB input end of described ASG sweep circuit unit, and its other the two poles of the earth connect respectively high level input end VDD and the described first node N1 of described ASG sweep circuit unit; The grid of the 3rd thin film transistor (TFT) M3 connects described first node N1, and its other the two poles of the earth connect respectively clock signal C K input end and the Section Point N2 of described ASG sweep circuit unit; Described the first capacitor C 1 is connected between described first node N1 and described Section Point N2.
Described drop-down control signal generation unit 51, comprising: the 4th thin film transistor (TFT) M4 and the 5th thin film transistor (TFT) M5; Wherein, the grid of the 4th thin film transistor (TFT) M4 is connected with the signal input part IN of described ASG sweep circuit unit, and its other the two poles of the earth connect respectively low level input end VEE and the drop-down control signal QB output terminal of described ASG sweep circuit unit; The grid of the 5th thin film transistor (TFT) M5 connects described Section Point N2, and its other the two poles of the earth connect respectively high level input end VDD and the drop-down control signal QB output terminal of described ASG sweep circuit unit.
On described, draw control signal generation unit 53, comprising: the 6th thin film transistor (TFT) M6 and the 7th thin film transistor (TFT) M7; Wherein, the grid of described the 6th thin transistor M6 connects described drop-down control signal QB output terminal, its other the two poles of the earth connect respectively institute's film state ASG sweep circuit unit low level input end VEE and on draw control signal Q output terminal; The grid of described the 7th thin film transistor (TFT) M7 connects the signal input part IN of described ASG sweep circuit unit, its other the two poles of the earth connect respectively described ASG sweep circuit unit high level input end VDD and on draw control signal Q output terminal.
Described drop-down output unit 52, comprising: the 8th thin film transistor (TFT) M8 and the second capacitor C 2; Wherein, the grid of described the 8th thin film transistor (TFT) M8 connects described drop-down control signal QB output terminal, and its other the two poles of the earth connect respectively the low level input end VEE of described ASG sweep circuit unit and the signal output part OUT of described circuit unit; Described the second capacitor C 2 is connected between described drop-down control signal QB output terminal and the low level input end VEE of described ASG sweep circuit unit.
On described, draw output unit 54, comprising: the 9th thin film transistor (TFT) M9 and the 3rd capacitor C 3; Wherein, on the grid connection of described the 9th thin film transistor (TFT) M9 is described, draw control signal Q output terminal, its other the two poles of the earth connect respectively the inversion clock signal CKB input end of described ASG sweep circuit unit and the signal output part OUT of described ASG sweep circuit unit; Described the 3rd capacitor C 3 is connected on described and draws between control signal Q output terminal and the signal output part OUT of described ASG sweep circuit unit.
The technical scheme that the embodiment of the present invention provides is used 9T3C ASG sweep circuit unit to realize displacement scan function, and in circuit, drop-down control signal QB is produced rather than produced by capacitive coupling by transistor M4 and M5, thereby without large coupling capacitance.And circuit can be realized and being automatically reset by the logical relation between transistor M1, M2 and M3, the reseting signal reset importing into without next stage.
The sequential relationship of the working signal of sweep circuit shown in Fig. 5 as shown in Figure 6.Signal CK in figure and signal CKB are the clock signal of phase place phase difference of pi; IN is trigger pip, an impulsive synchronization of he and CK signal; OUT is the output signal with respect to IN trigger pip time delay half period.
Referring to Fig. 7, in the signal generation unit 50 that automatically resets in the ASG sweep circuit unit in Fig. 5, in the time that input signal IN is high level, the level of the signal of first node N1 is negative value, and now the signal of Section Point N2 is low level.Because the signal of Section Point N2 is connected with clock signal C K by transistor M3, so this reset signal generation unit 50 by transistor M1, M2, M3 produce similar to clock signal C K, be to keep low level signal, the signal of exporting by Section Point N2 during for high level at input signal (signal of inputting by signal input part IN).Drop-down control signal generation unit 51 is by the drop-down control signal QB in signal and transistor M4 and the M5 generation ASG sweep circuit of Section Point N2.Drop-down control signal QB is connected with the grid of the transistor M6 that above draws control signal generation unit 53, be high level at input signal IN, when output signal OUT is high level, above draw control signal generation unit 53 to draw control signal Q in transistor M6 and M7 generation ASG sweep circuit unit.The last drop-down control signal QB of ASG sweep circuit unit by using by output transistor M8, on draw control signal Q to produce sweep signal by output transistor M9.In this sweep signal cycle, rise and fall are along the control of subject clock signal CK and CKB.
In the time that all described thin film transistor (TFT)s are P type thin film transistor (TFT), referring to Fig. 8, a kind of ASG sweep circuit unit that the embodiment of the present invention provides comprises: for by the signal generation unit 80 that automatically resets of thin film transistor (TFT) generating reset signal; Receive described reset signal, and according to the control of reset signal, generate the drop-down control signal generation unit 81 of drop-down control signal; Receive described drop-down control signal, and according to the control of drop-down control signal, the output signal of described ASG sweep circuit unit is pulled to low level drop-down output unit 82; For according to the control of described drop-down control signal, in generation, draw control signal on draw control signal generation unit 83; Receive on described and draw control signal, and according to the control of above drawing control signal, by the output signal of described ASG sweep circuit unit be pulled to high level on draw output unit 84.
Wherein, described in the signal generation unit 80 that automatically resets, comprising: the first film transistor M1, the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3 and the first capacitor C 1; Wherein, the grid of the first film transistor M1 is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth connect respectively high level input end VDD and the first node N1 of described circuit unit; The grid of the second thin film transistor (TFT) M2 is connected with the inversion clock signal CKB input end of described circuit unit, and its other the two poles of the earth connect respectively low level input end VEE and the described first node N1 of described circuit unit; The grid of the 3rd thin film transistor (TFT) M3 connects described first node N1, and its other the two poles of the earth connect respectively clock signal input terminal CK and the Section Point N2 of described circuit unit; Described the first capacitor C 1 is connected between described first node N1 and described Section Point N2.
Described drop-down control signal generation unit 81, comprising: the 4th thin film transistor (TFT) M4 and the 5th thin film transistor (TFT) M5; Wherein, the grid of the 4th thin film transistor (TFT) M4 is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth connect respectively high level input end VDD and the drop-down control signal QB output terminal of described circuit unit; The grid of the 5th thin film transistor (TFT) M5 connects described Section Point N2, and its other the two poles of the earth connect respectively low level input end VEE and the drop-down control signal QB output terminal of described circuit unit.
On described, draw control signal generation unit 83, comprising: the 6th thin film transistor (TFT) M6 and the 7th thin film transistor (TFT) M7; Wherein, the grid of described the 6th thin film transistor (TFT) M6 connects described drop-down control signal QB output terminal, its other the two poles of the earth connect respectively described circuit unit high level input end VDD and on draw control signal Q output terminal; The grid of described the 7th thin film transistor (TFT) M7 connects the signal input part IN of described circuit unit, its other the two poles of the earth connect respectively described circuit unit low level input end VEE and on draw control signal Q output terminal.
Described drop-down output unit 82, comprising: the 8th thin film transistor (TFT) M8 and the second capacitor C 2; Wherein, the grid of described the 8th thin film transistor (TFT) M8 connects described drop-down control signal QB output terminal, and its other the two poles of the earth connect respectively the high level input end VDD of described circuit unit and the signal output part OUT of described circuit unit; Described the second capacitor C 2 is connected between the high level input end VDD of described drop-down control signal QB output terminal and described circuit unit.
On described, draw output unit 84, comprising: the 9th thin film transistor (TFT) M9 and the 3rd capacitor C 3; Wherein, on the grid connection of described the 9th thin film transistor (TFT) M9 is described, draw control signal Q output terminal, its other the two poles of the earth connect respectively the inversion clock signal CKB input end of described circuit unit and the signal output part OUT of described circuit unit; Described the 3rd capacitor C 3 is connected on described and draws between the signal output part OUT of control signal Q output terminal and described circuit unit.
Referring to Fig. 9, in the signal generation unit 80 that automatically resets in the ASG sweep circuit unit in Fig. 8 in the time that input signal IN is low level, the level of the signal of first node N1 be on the occasion of, now the signal of Section Point N2 is high level.Because the signal of Section Point N2 is connected with clock signal C K by transistor M3, so this reset signal generation unit 80 by transistor M1, M2, M3 produce similar to clock signal C K, be the signal that keeps high level at input signal (signal of inputting by signal input part IN) during for low level, the signal of exporting by Section Point N2.Drop-down control signal generation unit 81 is by the drop-down control signal QB in signal and transistor M4 and the M5 generation ASG sweep circuit of Section Point N2.Drop-down control signal QB is connected with the grid of the transistor M6 that above draws control signal generation unit 83, be low level at input signal IN, when output signal OUT is low level, above draw control signal generation unit 83 to draw control signal Q in transistor M6 and M7 generation ASG sweep circuit unit.The last drop-down control signal QB of ASG sweep circuit unit by using by output transistor M8, on draw control signal Q to produce sweep signal by output transistor M9.In this sweep signal cycle, rise and fall are along the control of subject clock signal CK and CKB.
After Figure 10 is the output terminal access load in 9T3C ASG sweep circuit unit, the analog result of the each node voltage signal intensity obtaining by a-Si modeling.Can find by analog result, the variation of each node voltage signal is with consistent shown in Fig. 7.Analog result is consistent with content mentioned above.
A kind of amorphous silicon gate could that the embodiment of the present invention provides drives ASG sweep circuit, and this circuit comprises the above-mentioned 9T3C ASG sweep circuit unit of multiple cascades, and wherein, the signal output part OUT of each circuit unit is connected with the signal input part IN of next stage circuit unit.
The ASG sweep circuit being formed by ASG sweep circuit unit combination is referring to Figure 11, and ASG sweep circuit unit connects display panel is lined by line scan by this figure.Wherein each ASG sweep circuit unit need to be connected with high level input end VDD, and VEE is connected with low level input end, and wants input clock signal CK and inversion clock signal CKB.The signal output part OUT of each ASG sweep circuit unit is connected with the signal input part IN of next stage ASG sweep circuit unit, and wherein the output signal OUT of upper level ASG sweep circuit unit is as the trigger pip IN of ASG sweep circuit at the corresponding levels unit.In addition, the signal output part out1 of first order ASG sweep circuit unit Cell is connected with load Loading; The signal output part out2 of ASG sweep circuit unit, second level Cell1 is connected with load Loading1; The signal output part out3 of third level ASG sweep circuit unit Cell2 is connected with load Loading2; The signal output part out4 of fourth stage ASG sweep circuit unit Cell3 is connected with load Loading3; The signal output part out5 of level V ASG sweep circuit unit Cell4 is connected with load Loading4; The signal output part out6 of the 6th grade of ASG sweep circuit unit Cell5 is connected with load Loading5.Clock signal C K input end (hereinafter referred to as the first clock signal input terminal) in Fig. 9 in first order ASG sweep circuit unit Cell connects clock signal C K line, and the inversion clock signal CKB input end (hereinafter referred to as second clock signal input part) in first order ASG sweep circuit unit Cell connects inversion clock signal CKB line.The first clock signal input terminal in ASG sweep circuit unit, second level Cell1 connects inversion clock signal CKB line, and the second clock signal input part in ASG sweep circuit unit, second level Cell1 connects clock signal C K line.Third level ASG sweep circuit unit Cell2 is identical with the connected mode of second clock signal input part with connected mode and first clock signal input terminal of first order ASG sweep circuit unit Cell of second clock signal input part with the first clock signal input terminal in level V ASG sweep circuit unit Cell4.Fourth stage ASG sweep circuit unit Cell3 is identical with the connected mode of second clock signal input part with connected mode and first clock signal input terminal of ASG sweep circuit unit, second level Cell1 of second clock signal input part with the first clock signal input terminal in the 6th grade of ASG sweep circuit unit Cell5.By above connection, this sweep circuit can be realized lining by line scan to display panel.Due to the signal generation unit that automatically resets of the ASG sweep circuit unit in this ASG sweep circuit, so this ASG sweep circuit is without reset signal.
Figure 12 is the analog result of the ASG sweep circuit shown in Figure 11.Figure 12 simulates the signal output waveform of ASG sweep circuit output node out1, out2, out3, out4 and out5.Can see from analog result, half clock signal C K of time delay or CKB cycle are exported trigger pip to the ASG sweep circuit unit in ASG sweep circuit successively.
A kind of flat-panel monitor that the embodiment of the present invention provides, this flat-panel monitor comprises that above-described amorphous silicon gate could drives ASG sweep circuit.
In sum, the embodiment of the present invention provides a kind of amorphous silicon gate could to drive ASG sweep circuit and element circuit thereof, and this circuit unit comprises: for by the signal generation unit that automatically resets of thin film transistor (TFT) generating reset signal; Be used for receiving described reset signal, and according to the control of reset signal, generate the drop-down control signal generation unit of drop-down control signal; Be used for receiving described drop-down control signal, and according to the control of drop-down control signal, the output signal of described circuit unit be pulled to low level drop-down output unit; For according to the control of described drop-down control signal, in generation, draw control signal on draw control signal generation unit; Be used for receiving on described and draw control signal, and according to the control of above drawing control signal, by the output signal of described circuit unit be pulled to high level on draw output unit.This ASG sweep circuit can produce auto-reset function, thereby can reduce the quantity of lead-in wire.This ASG sweep circuit unit produces drop-down control signal by the control of reset signal, does not need larger coupling capacitance to produce pulldown signal, thereby can reduce circuit area, reduces the design difficulty of circuit.In addition, with respect to the circuit being made up of 17 transistors, the embodiment of the present invention has reduced transistorized quantity, has simplified circuit design.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (15)
1. amorphous silicon gate could drives an ASG sweep circuit unit, it is characterized in that, this circuit unit comprises:
The signal generation unit that automatically resets, for by thin film transistor (TFT) generating reset signal;
Drop-down control signal generation unit, receives described reset signal, and according to the control of reset signal, generates drop-down control signal;
Drop-down output unit, receives described drop-down control signal, and according to the control of drop-down control signal, the output signal of described circuit unit is pulled to low level;
On draw control signal generation unit, for according to the control of described drop-down control signal, in generation, draw control signal;
On draw output unit, receive on described and draw control signal, and according to the control of above drawing control signal, the output signal of described circuit unit is pulled to high level.
2. circuit unit according to claim 1, is characterized in that, described in the signal generation unit that automatically resets, comprising: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the first electric capacity; Wherein, the transistorized grid of the first film is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth connect respectively low level input end VEE and the first node of described circuit unit; The grid of the second thin film transistor (TFT) is connected with the inversion clock signal CKB input end of described circuit unit, and its other the two poles of the earth connect respectively high level input end VDD and the described first node of described circuit unit; The grid of the 3rd thin film transistor (TFT) connects described first node, and its other the two poles of the earth connect respectively clock signal input terminal CK and the Section Point of described circuit unit; Described the first electric capacity is connected between described first node and described Section Point.
3. circuit unit according to claim 2, is characterized in that, described drop-down control signal generation unit, comprising: the 4th thin film transistor (TFT) and the 5th thin film transistor (TFT); Wherein, the grid of the 4th thin film transistor (TFT) is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth connect respectively low level input end VEE and the drop-down control signal QB output terminal of described circuit unit; The grid of the 5th thin film transistor (TFT) connects described Section Point, and its other the two poles of the earth connect respectively high level input end VDD and the drop-down control signal QB output terminal of described circuit unit.
4. circuit unit according to claim 3, is characterized in that, draws control signal generation unit on described, comprising: the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT); Wherein, the grid of described the 6th thin film transistor (TFT) connects described drop-down control signal QB output terminal, its other the two poles of the earth connect respectively described circuit unit low level input end VEE and on draw control signal Q output terminal; The grid of described the 7th thin film transistor (TFT) connects the signal input part IN of described circuit unit, its other the two poles of the earth connect respectively described circuit unit high level input end VDD and on draw control signal Q output terminal.
5. circuit unit according to claim 4, is characterized in that, described drop-down output unit, comprising: the 8th thin film transistor (TFT) and the second electric capacity; Wherein, the grid of described the 8th thin film transistor (TFT) connects described drop-down control signal QB output terminal, and its other the two poles of the earth connect respectively the low level input end VEE of described circuit unit and the signal output part OUT of described circuit unit; Described the second electric capacity is connected between the low level input end VEE of described drop-down control signal QB output terminal and described circuit unit.
6. circuit unit according to claim 5, is characterized in that, draws output unit on described, comprising: the 9th thin film transistor (TFT) and the 3rd electric capacity; Wherein, on the grid connection of described the 9th thin film transistor (TFT) is described, draw control signal Q output terminal, its other the two poles of the earth connect respectively the inversion clock signal CKB input end of described circuit unit and the signal output part OUT of described circuit unit; Described the 3rd electric capacity is connected on described and draws between the signal output part OUT of control signal Q output terminal and described circuit unit.
7. according to the circuit unit described in the arbitrary claim of claim 1-6, it is characterized in that, all described thin film transistor (TFT)s are N-type thin film transistor (TFT).
8. circuit unit according to claim 1, is characterized in that, described in the signal generation unit that automatically resets, comprising: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the first electric capacity; Wherein, the transistorized grid of the first film is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth connect respectively high level input end VDD and the first node of described circuit unit; The grid of the second thin film transistor (TFT) is connected with the inversion clock signal CKB input end of described circuit unit, and its other the two poles of the earth connect respectively low level input end VEE and the described first node of described circuit unit; The grid of the 3rd thin film transistor (TFT) connects described first node, and its other the two poles of the earth connect respectively clock signal input terminal CK and the Section Point of described circuit unit; Described the first electric capacity is connected between described first node and described Section Point.
9. circuit unit according to claim 8, is characterized in that, described drop-down control signal generation unit, comprising: the 4th thin film transistor (TFT) and the 5th thin film transistor (TFT); Wherein, the grid of the 4th thin film transistor (TFT) is connected with the signal input part IN of described circuit unit, and its other the two poles of the earth connect respectively high level input end VDD and the drop-down control signal QB output terminal of described circuit unit; The grid of the 5th thin film transistor (TFT) connects described Section Point, and its other the two poles of the earth connect respectively low level input end VEE and the drop-down control signal QB output terminal of described circuit unit.
10. circuit unit according to claim 9, is characterized in that, draws control signal generation unit on described, comprising: the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT); Wherein, the grid of described the 6th thin film transistor (TFT) connects described drop-down control signal QB output terminal, its other the two poles of the earth connect respectively described circuit unit high level input end VDD and on draw control signal Q output terminal; The grid of described the 7th thin film transistor (TFT) connects the signal input part IN of described circuit unit, its other the two poles of the earth connect respectively described circuit unit low level input end VEE and on draw control signal Q output terminal.
11. circuit units according to claim 10, is characterized in that, described drop-down output unit, comprising: the 8th thin film transistor (TFT) and the second electric capacity; Wherein, the grid of described the 8th thin film transistor (TFT) connects described drop-down control signal QB output terminal, and its other the two poles of the earth connect respectively the high level input end VDD of described circuit unit and the signal output part OUT of described circuit unit; Described the second electric capacity is connected between the high level input end VDD of described drop-down control signal QB output terminal and described circuit unit.
12. circuit units according to claim 11, is characterized in that, draw output unit on described, comprising: the 9th thin film transistor (TFT) and the 3rd electric capacity; Wherein, on the grid connection of described the 9th thin film transistor (TFT) is described, draw control signal Q output terminal, its other the two poles of the earth connect respectively the inversion clock signal CKB input end of described circuit unit and the signal output part OUT of described circuit unit; Described the 3rd electric capacity is connected on described and draws between the signal output part OUT of control signal Q output terminal and described circuit unit.
Circuit unit described in 13. according to Claim 8-12 arbitrary claims, is characterized in that, all described thin film transistor (TFT)s are P type thin film transistor (TFT).
14. 1 kinds of amorphous silicon gate could drive ASG sweep circuit, it is characterized in that, this circuit comprises the circuit unit described in the arbitrary claim of the claim 1-13 of multiple cascades, and wherein, the signal output part OUT of each circuit unit is connected with the signal input part IN of next stage circuit unit.
15. 1 kinds of flat-panel monitors, is characterized in that, this flat-panel monitor comprises the circuit described in claim 14.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310178786.1A CN103915049B (en) | 2013-05-14 | 2013-05-14 | Amorphous silicon gate could drives scanning circuit and circuit unit, flat faced display |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310178786.1A CN103915049B (en) | 2013-05-14 | 2013-05-14 | Amorphous silicon gate could drives scanning circuit and circuit unit, flat faced display |
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| CN103915049A true CN103915049A (en) | 2014-07-09 |
| CN103915049B CN103915049B (en) | 2016-08-10 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110228893A1 (en) * | 2010-03-18 | 2011-09-22 | Mitsubishi Electric Corporation | Shift register circuit |
| CN102237062A (en) * | 2010-04-29 | 2011-11-09 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN102789757A (en) * | 2011-05-18 | 2012-11-21 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| US20130027378A1 (en) * | 2011-07-25 | 2013-01-31 | Samsung Electronics Co., Ltd. | Display panel and integrated driving apparatus thereon |
-
2013
- 2013-05-14 CN CN201310178786.1A patent/CN103915049B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110228893A1 (en) * | 2010-03-18 | 2011-09-22 | Mitsubishi Electric Corporation | Shift register circuit |
| CN102237062A (en) * | 2010-04-29 | 2011-11-09 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN102789757A (en) * | 2011-05-18 | 2012-11-21 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| US20130027378A1 (en) * | 2011-07-25 | 2013-01-31 | Samsung Electronics Co., Ltd. | Display panel and integrated driving apparatus thereon |
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| CN103915049B (en) | 2016-08-10 |
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