CN103914434A - Partial parallel input right shift accumulation quasi-cyclic matrix multiplier in DTMB - Google Patents

Abstract

The invention provides a partial parallel input right shift accumulation quasi-cyclic matrix multiplier in DTMB. The partial parallel input right shift accumulation quasi-cyclic matrix multiplier is used for realizing multiplication of a vector m and a quasi-cyclic matrix F in DTMB standard multi-code-rate QC-LDPC approximate lower triangular coding. The multiplier comprises a 127-bit shifting register for performing vector section cyclic right shift, three generating polynomial searching tables, three 127-bit binary multipliers, three 127-bit binary adders, and three 127-bit accumulators. The generating polynomial searching tables pre-store all cyclic matrix generating polynomials in the matrix F. The 127-bit binary multipliers perform scalar multiplication on the contents of the shifting register and generating polynomial bits. The 127-bit binary adders perform xor operation on product sums and the contents of the accumulators. The partial parallel input multiplier is compatible with all code rates, few in register, simple in structure, low in power consumption, low in cost, high in work frequency, large in throughput, and the like.

Description

The cumulative quasi-cyclic matrix multiplier that moves to right of part parallel input in DTMB

Technical field

The present invention relates to field of channel coding, particularly the cumulative quasi-cyclic matrix multiplier that moves to right of part parallel input in a kind of DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code is one of efficient channel coding technology, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.Generator matrix G and the check matrix H of QC-LDPC code are all the arrays being made up of circular matrix, have the feature of segmentation circulation, therefore be called as QC-LDPC code.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip completely.Conventionally, the first trip of circular matrix is called as its generator polynomial.

In the time adopting near lower triangular coding method to encode to QC-LDPC code, exchange by ranks, check matrix H is transformed near lower triangular shape H _aLT, it is composed as follows by 6 sub-matrixes:

$H_{\mathrm{ALT}}=\left[\begin{array}{ccc}A& B& L\\ C& D& E\end{array}\right]---\left(1\right)$

Wherein, L is lower triangular matrix.H _aLTcorresponding code word v _aLT=(s, p, q), the corresponding vectorial s of matrix A and C, the corresponding a part of verification vector of matrix B and D p, matrix L and E be corresponding remaining verification vector q.The method of calculating section verification vector p is as follows:

p＝s(C+EL ^-1A) ^Τ((D+EL ^-1B) ^-1) ^Τ (2)

Wherein, subscript ^-1with ^Τrepresent respectively matrix inversion and transposition.Order

m＝s(C+EL ^-1A) ^Τ (3)

F＝((D+EL ^-1B) ^-1) ^Τ (4)

Vectorial m and matrix F meet following relation:

p＝mF (5)

Matrix F is by following u × u b × b rank circular matrix F _i,jthe quasi-cyclic matrix that (0≤i<u, 0≤j<u) forms:

Capable and the b row of the continuous b of F are called as respectively the capable and piece row of piece.From formula (6), F has the capable and u piece of u piece row.Make f _i,jcircular matrix F _i,jgenerator polynomial.

Make vectorial m=(e ₀, e ₁..., e _{u × b-1}), part verification vector p=(d ₀, d ₁..., d _{u × b-1}).Take b bit as one section, vectorial m and part verification vector p are all divided into u section, i.e. m=(m ₀, m ₁..., m _u-1) and p=(p ₀, p ₁..., p _u-1).From formula (5), the j section p of part verification vector _jmeet

p _j＝m ₀F _0,j+m ₁F _1,j+...+m _iF _i,j+...+m _u-1F _u-1,j (7)

Wherein, 0≤i<u, 0≤j<u.Order with respectively generator polynomial f _i,jthe result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (7) equal sign the right is deployable is

$m_i{F}_{i,j}=e_{i\&times;b}{f}_{i,j}^{r\left(0\right)}+e_{i\&times;b+1}{f}_{i,j}^{r\left(1\right)}+...+e_{i\&times;b+b-1}{f}_{i,j}^{r(b-1)}---\left(8\right)$

Formula (5) relates to the multiplication of vector and quasi-cyclic matrix, and what extensively adopt at present is the scheme that adds totalizer (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit based on u I type shift register.Fig. 1 is the functional block diagram of single SRAA-I circuit, and vectorial m by turn serial sends into this circuit.When using SRAA-I circuit calculation check section p _jwhen (0≤j<u), all generator polynomials of the j piece row of the pre-stored quasi-cyclic matrix F of generator polynomial look-up table, totalizer is cleared initialization.In the time that the 0th clock period arrives, shift register loads the 0th row of F, the generator polynomial of j piece row from generator polynomial look-up table bit e ₀move into circuit, and with the content of shift register carry out scalar multiplication, product add with content 0 mould 2 of totalizer, and deposit back totalizer.In the time that the 1st clock period arrives, 1 of shift register ring shift right, content becomes bit e ₁move into circuit, and with the content of shift register carry out scalar multiplication, product content with totalizer mould 2 adds, and deposit back totalizer.Above-mentionedly move to right-take advantage of-Jia-storing process proceeds down.In the time that b-1 clock period finishes, bit e _b-1moved into circuit, now that cumulative adder stores is part and m ₀f ₀, _j, this is array section m ₀to p _jcontribution.In the time that b clock period arrives, shift register loads the 1st row of F, the generator polynomial of j piece row from generator polynomial look-up table repeat above-mentionedly to move to right-take advantage of-Jia-storing process.As array section m ₁while moving into circuit completely, cumulative adder stores be part and m ₀f _{0, j}+ m ₁f _{1, j}.Repeat said process, until the whole serials of whole vectorial m move into circuit.Now, that cumulative adder stores is verification section p _j.Use u the quasi-cyclic matrix serial multiplier shown in SRAA-I circuit energy pie graph 2, it obtains u verification section within u × b clock period simultaneously.This scheme needs 2 × u × b register, u × b two input and door and u × b two input XOR gate, also needs the generator polynomial of u u × b bit ROM storage circular matrix.

DTMB standard has adopted code check η=0.4,0.6 and 0.8 3 kind of QC-LDPC code, all has b=127.For code check η=0.4,0.6 and 0.8, u be respectively 3,2 and 2.

For compatible 3 kinds of code checks, in DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, the existing solution of quasi-cyclic matrix multiplication is based on 3 SRAA-I circuit.This scheme has two shortcomings: the one, need 762 registers, and cause the power consumption of circuit large, cost is high; The 2nd, serial input vector bit, loaded in parallel generator polynomial, needs 382 connecting lines.So many line can cause that circuit structure complexity, the frequency of operation of multiplier is low, handling capacity is little.

Summary of the invention

In DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding there is the shortcoming that power consumption is large, cost is high, circuit structure is complicated, frequency of operation is low, handling capacity is little in the existing implementation of quasi-cyclic matrix multiplication, for these technical matterss, the invention provides a kind of part parallel input multiplier based on moving to right cumulative.

As shown in Figure 4, in DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, the cumulative quasi-cyclic matrix multiplier that moves to right of part parallel input is mainly made up of 5 parts: shift register, generator polynomial look-up table, b position binary multiplier, b position binary adder and totalizer.Multiplication process divides 5 steps to complete: the 1st step, zero clearing totalizer R ₀, R ₁, R ₂; The 2nd step, shift register input vector section m _i(0≤i<u); The 3rd step, generator polynomial look-up table L ₀, L ₁, L ₂the generator polynomial bit of the 0th, 1,2 row during difference bit rate output η quasi-cyclic matrix F i piece is capable, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁, M ₂carry out scalar multiplication with the content of shift register, b position binary multiplier M ₀, M ₁, M ₂product respectively by b position binary adder A ₀, A ₁, A ₂with totalizer R ₀, R ₁, R ₂content be added, b position binary adder A ₀, A ₁, A ₂with deposit respectively totalizer R in ₀, R ₁, R ₂; The 4th step, one of shift register ring shift right, repeats the 3rd step b time; The 5th step, changes the value of i take 1 as step-length increases progressively, and repeats 2nd～4 step u time, until that whole vectorial m inputs is complete, now, totalizer R ₀, R ₁..., R _u-1that store is respectively verification section p ₀, p ₁..., p _u-1, they have formed part verification vector p=(p ₀, p ₁..., p _u-1).

Part parallel input quasi-cyclic matrix multiplier architecture provided by the invention is simple, and the QC-LDPC code of all code checks in compatible DTMB standard can, keeping, under the condition of speed, reducing register and line, reduce power consumption and cost, improves frequency of operation and handling capacity.

Can be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Accompanying drawing explanation

Fig. 1 is the functional block diagram that I type shift register adds totalizer SRAA-I circuit;

Fig. 2 is the quasi-cyclic matrix multiplier being made up of u SRAA-I circuit;

Fig. 3 is the functional block diagram that II type shift register adds totalizer SRAA-II circuit;

Fig. 4 is a kind of part parallel input quasi-cyclic matrix multiplier based on moving to right cumulative being made up of 3 SRAA-II circuit.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that, protection scope of the present invention is made to more explicit defining.

Make generator polynomial f _i,j=(f _{i, j, 0}, f _{i, j, 1}..., f _{i, j, b-1}), F _i,jcan be considered the weighted sum of unit matrix ring shift right version,

F _i,j＝f _i,j,0I ^r(0)+f _i,j,1I ^r(1)+...+f _i,j,b-1I ^r(b-1) (9)

So, the i item on formula (7) equal sign the right is deployable is

$\begin{array}{c}{m}_i{F}_{i,j}=m_i(f_{i,j,0}{I}^{r\left(0\right)}+f_{i,j,1}{I}^{r\left(1\right)}+...+f_{i,j,b-1}{I}^{r(b-1)})\\ =f_{i,j,0}{m}_i{I}^{r\left(0\right)}+f_{i,j,1}{m}_i{I}^{r\left(1\right)}+...+f_{i,j,b-1}{m}_i{I}^{r(b-1)}\\ =f_{i,j,0}{m}_i^{r\left(0\right)}+f_{i,j,1}{m}_i^{r\left(1\right)}+...+f_{i,j,b-1}{m}_i^{r(b-1)}\end{array}---\left(10\right)$

Compared with formula (8), the remarkable advantage of formula (10) is the parallel input vector m of segmentation, and serial loads generator polynomial f _i,j.Formula (10) is one and moves to right-take advantage of-process of Jia-storage, and it is realized and adds totalizer (Type-II Shift-Register-Adder-Accumulator, SRAA-II) circuit with II type shift register.Fig. 3 is the functional block diagram of SRAA-II circuit, and vectorial m is take b bit as one section of parallel this circuit of sending into.When using SRAA-II circuit calculation check section p _jwhen (0≤j<u), all generator polynomials of the j piece row of the pre-stored quasi-cyclic matrix F of generator polynomial look-up table, totalizer is cleared initialization.In the time that the 0th clock period arrives, array section m ₀move into shift register, the 0th row of generator polynomial look-up table output F, the generator polynomial f of j piece row _{0, j}the 0th bit f _{0, j, 0}, and with the content of shift register carry out scalar multiplication, product add with content 0 mould 2 of totalizer, and deposit back totalizer.In the time that the 1st clock period arrives, 1 of shift register ring shift right, content becomes generator polynomial look-up table output f _{0, j}the 1st bit f _{0, j, 1}, and with the content of shift register carry out scalar multiplication, product content with totalizer mould 2 adds, and deposit back totalizer.Above-mentionedly move to right-take advantage of-Jia-storing process proceeds down.In the time that b-1 clock period finishes, generator polynomial look-up table has been exported f _{0, j}last bit f _{0, j, b-1}, now that cumulative adder stores is part and m ₀f _{0, j}, this is array section m ₀to p _jcontribution.In the time that b clock period arrives, array section m ₁move into shift register, repeat above-mentionedly to move to right-take advantage of-Jia-storing process.When generator polynomial look-up table has been exported f _{1, j}last bit f _{1, j, b-1}time, cumulative adder stores be part and m ₀f _{0, j}+ m ₁f _{1, j}.Repeat said process, until all parallel circuit that moves into of whole vectorial m.Now, that cumulative adder stores is verification section p _j.

Fig. 4 has provided a kind of part parallel input quasi-cyclic matrix multiplier based on moving to right cumulative being made up of 3 SRAA-II circuit, is made up of shift register, generator polynomial look-up table, b position binary multiplier, b position binary adder and totalizer five functions module.Shift register is to array section m _i(0≤i<u) ring shift right.Generator polynomial look-up table L ₀, L ₁, L ₂all code check quasi-cyclic matrix F the 0th that prestore respectively, all circular matrix generator polynomials in 1,2 row.Generator polynomial look-up table L ₀, L ₁, L ₂the generator polynomial bit of output carries out scalar multiplication with the content of shift register respectively, and these 3 scalar multiplications are respectively by b position binary multiplier M ₀, M ₁, M ₂complete.B position binary multiplier M ₀, M ₁, M ₂product respectively with totalizer R ₀, R ₁, R ₂content be added, these 3 nodulo-2 additions are respectively by b position binary adder A ₀, A ₁, A ₂complete.B position binary adder A ₀, A ₁, A ₂with deposit respectively totalizer R in ₀, R ₁, R ₂.

Generator polynomial look-up table L ₀, L ₁, L ₂store the circular matrix generator polynomial in all code check quasi-cyclic matrix F.L ₀, L ₁store respectively all generator polynomials in the 0th, 1 row of three kinds of code check F, for arbitrary row, store successively the 0th, 1 ..., the capable corresponding generator polynomial of u-1 piece.L ₂all generator polynomials in the 2nd row of storage η=0.4 code check F, store the 0th, 1 successively ..., the capable corresponding generator polynomial of u-1 piece.

The invention provides a kind of part parallel input quasi-cyclic matrix multiplication based on moving to right cumulative, 3 kinds of code check QC-LDPC codes in its compatible DTMB standard, its multiplication step is described below:

The 1st step, zero clearing totalizer R ₀, R ₁, R ₂;

The 2nd step, shift register input vector section m _i(0≤i<u);

The 3rd step, generator polynomial look-up table L ₀, L ₁, L ₂the generator polynomial bit of the 0th, 1,2 row during difference bit rate output η quasi-cyclic matrix F i piece is capable, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁, M ₂carry out scalar multiplication with the content of shift register, b position binary multiplier M ₀, M ₁, M ₂product respectively by b position binary adder A ₀, A ₁, A ₂with totalizer R ₀, R ₁, R ₂content be added, b position binary adder A ₀, A ₁, A ₂with deposit respectively totalizer R in ₀, R ₁, R ₂;

The 4th step, one of shift register ring shift right, repeats the 3rd step b time;

The 5th step, changes the value of i take 1 as step-length increases progressively, and repeats 2nd～4 step u time, until that whole vectorial m inputs is complete, now, totalizer R ₀, R ₁..., R _u-1that store is respectively verification section p ₀, p ₁..., p _u-1, they have formed part verification vector p=(p ₀, p ₁..., p _u-1).

Be not difficult to find out from above step, whole computation process needs u × b clock period altogether, identical with the existing multiplication scheme based on 3 SRAA-I circuit.

In DTMB standard, the existing solution of quasi-cyclic matrix multiplier needs 762 registers, 381 two inputs and door and 381 two input XOR gate, and the present invention needs 509 registers, 381 two inputs and door and 381 two input XOR gate.Two kinds of multiplication scheme expend equal number with door and XOR gate, but the present invention has saved 33% register.

Existing solution needs 382 lines to connect shift register and generator polynomial look-up table, and the present invention only needs 130 connecting lines.

As fully visible, for the quasi-cyclic matrix multiplier in DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, compared with existing solution, the present invention has kept identical speed, save 33% register, greatly simplify circuit connection, there is the advantages such as simple in structure, power consumption is little, cost is low, frequency of operation is high, handling capacity is large.

The above; it is only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited to this; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; the variation that can expect without creative work or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain that claims were limited.

Claims (4)

1. the cumulative quasi-cyclic matrix multiplier that moves to right of part parallel input in a DTMB, in the time adopting near lower triangular coding method to encode to DTMB standard multi code Rate of Chinese character QC-LDPC code, relate to the multiplying of vectorial m and quasi-cyclic matrix F, matrix F is divided into the capable and u piece of u piece row, is by u × u b × b rank circular matrix F _i,jthe array forming, f _i,jcircular matrix F _i,jgenerator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i<u, 0≤j<u, DTMB standard has adopted the QC-LDPC code of 3 kinds of different code check η, and η is respectively 0.4,0.6,0.8, for these 3 kinds different code check QC-LDPC codes, all have b=127,3 kinds of parameters u corresponding to different code checks are respectively 3,2,2, take b bit as one section, vector m is divided into u section, i.e. m=(m ₀, m ₁..., m _u-1), part verification vector p is divided into u section, i.e. p=(p ₀, p ₁..., p _u-1), it is characterized in that, described multiplier comprises with lower member:

B bit shift register is carried out ring shift right to array section;

Generator polynomial look-up table L ₀, L ₁, L ₂, in all code check quasi-cyclic matrix F that prestore respectively the 0th, the circular matrix generator polynomial of 1,2 row;

B position binary multiplier M ₀, M ₁, M ₂, the content to shift register and generator polynomial look-up table L respectively ₀, L ₁, L ₂output bit carry out scalar multiplication;

B position binary adder A ₀, A ₁, A ₂, respectively to b position binary multiplier M ₀, M ₁, M ₂sum of products totalizer R ₀, R ₁, R ₂content carry out mould 2 and add;

Totalizer R ₀, R ₁, R ₂, store respectively b position binary adder A ₀, A ₁, A ₂result and final verification section p ₀, p ₁, p ₂.

2. the cumulative quasi-cyclic matrix multiplier that moves to right of part parallel input in a kind of DTMB according to claim 1, is characterized in that described generator polynomial look-up table L ₀, L ₁store respectively all generator polynomials in the 0th, 1 row of three kinds of code check F, for arbitrary row, store successively the 0th, 1 ..., the capable corresponding generator polynomial of u-1 piece.

3. the cumulative quasi-cyclic matrix multiplier that moves to right of part parallel input in a kind of DTMB according to claim 1, is characterized in that described generator polynomial look-up table L ₂all generator polynomials in the 2nd row of storage η=0.4 code check F, store the 0th, 1 successively ..., the capable corresponding generator polynomial of u-1 piece.

4. the cumulative quasi-cyclic matrix serial multiplication method that moves to right of part parallel input in a DTMB, in the time adopting near lower triangular coding method to encode to DTMB standard multi code Rate of Chinese character QC-LDPC code, relate to the multiplying of vectorial m and quasi-cyclic matrix F, matrix F is divided into the capable and u piece of u piece row, is by u × u b × b rank circular matrix F _i,jthe array forming, f _i,jcircular matrix F _i,jgenerator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i<u, 0≤j<u, DTMB standard has adopted the QC-LDPC code of 3 kinds of different code check η, and η is respectively 0.4,0.6,0.8, for these 3 kinds different code check QC-LDPC codes, all have b=127,3 kinds of parameters u corresponding to different code checks are respectively 3,2,2, take b bit as one section, vector m is divided into u section, i.e. m=(m ₀, m ₁..., m _u-1), part verification vector p is divided into u section, i.e. p=(p ₀, p ₁..., p _u-1), it is characterized in that, described multiplication method comprises the following steps:

The 1st step, zero clearing totalizer R ₀, R ₁, R ₂;

The 2nd step, shift register input vector section m _i(0≤i<u);

The 3rd step, generator polynomial look-up table L ₀, L ₁, L ₂the generator polynomial bit of the 0th, 1,2 row during difference bit rate output η quasi-cyclic matrix F i piece is capable, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁, M ₂carry out scalar multiplication with the content of shift register, b position binary multiplier M ₀, M ₁, M ₂product respectively by b position binary adder A ₀, A ₁, A ₂with totalizer R ₀, R ₁, R ₂content be added, b position binary adder A ₀, A ₁, A ₂with deposit respectively totalizer R in ₀, R ₁, R ₂;

The 4th step, one of shift register ring shift right, repeats the 3rd step b time;

The 5th step, changes the value of i take 1 as step-length increases progressively, and repeats 2nd～4 step u time, until that whole vectorial m inputs is complete, now, totalizer R ₀, R ₁..., R _u-1that store is respectively verification section p ₀, p ₁..., p _u-1, they have formed part verification vector p=(p ₀, p ₁..., p _u-1).