CN103906305A - Drive circuit and drive method - Google Patents
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- CN103906305A CN103906305A CN201210587364.5A CN201210587364A CN103906305A CN 103906305 A CN103906305 A CN 103906305A CN 201210587364 A CN201210587364 A CN 201210587364A CN 103906305 A CN103906305 A CN 103906305A
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Abstract
The invention provides a drive circuit and a drive method. The drive circuit comprises a first PWM drive module and a second PWM drive module. The first PWM drive module generates a first square wave signal according to a first data signal of a data stream, and the first square wave signal is used for driving a first light-emitting unit. The first square wave signal represents the light-emitting time of the first light-emitting unit in a display period. A rising edge of the first square wave signal is located at the start point in the display period. The second PWM drive module generates a second square wave signal according to a second data signal of the data stream, and the second square wave signal is used for driving a second light-emitting unit. The second square wave signal represents the light-emitting time of the second light-emitting unit in the display period. A falling edge of the second square wave signal is located at the end point in the display period. The rising edge of the second square wave signal is later than the rising edge of the first square wave signal. By the adoption of the drive circuit and the drive method, the probabilities of generation of currents of all time points in the display period are average, so that an instant load caused on a power line when the light-emitting units are powered on at the same time is reduced.
Description
Technical field
The present invention has about a kind of luminescent system, relates to especially a kind of drive circuit.
Background technology
Figure 1A is the schematic diagram of a luminescent system.As shown in Figure 1A, luminescent system 100 has drive circuit 110 and light emitting module 120.Drive circuit 110 has n channel and drives luminescence unit ED1 ~ EDn, and each luminescence unit ED1 ~ EDn receives power line Vp in succession.
Figure 1B is the online electric current of power supply and the graph of a relation of time.As shown in Figure 1B, waveform Cv1 represents the electric current of the 1st passage, and waveform Cv2 represents the electric current of the 2nd passage, and waveform Cv3 represents the electric current of the 3rd passage, and waveform Cvn represents the electric current of n passage.Waveform Cvs represents the total current of waveform Cv1 to waveform Cvn, is also the electric current on power line Vp.
Significantly, due to n channel each display cycle DP at the beginning time simultaneously conducting, the electric current on power line Vp by zero moment increase sharply to the n of the current value of single channel doubly, this measure will cause noise concentrations in display cycle DP at the beginning.Therefore, need a kind of drive circuit and driving method badly, by the On current mean allocation on power line Vp to display cycle DP.
Summary of the invention
In view of this, the invention provides a kind of drive circuit, comprise: one the one PWM driver module, produce one first square-wave signal according to one first data-signal of a data flow, in order to drive one first luminescence unit, wherein above-mentioned the first square-wave signal represents that above-mentioned the first luminescence unit is in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned the first square-wave signal is positioned at the starting point of above-mentioned display cycle; And one the 2nd PWM driver module, produce one second square-wave signal according to one second data-signal of above-mentioned data flow, in order to drive one second luminescence unit, wherein above-mentioned the second square-wave signal represents that above-mentioned the second luminescence unit is in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned the second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned the second square-wave signal is later than the rising edge of above-mentioned the first square-wave signal.
The present invention also provides a kind of driving method, be applicable to drive one first luminescence unit and one second luminescence unit, above-mentioned driving method comprises: produce one first square-wave signal according to one first data-signal of a data flow, wherein above-mentioned the first square-wave signal represents that above-mentioned the first luminescence unit is in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned the first square-wave signal is positioned at the starting point of a display cycle; According to above-mentioned the first luminescence unit of above-mentioned the first square wave signal driver; Produce one second square-wave signal according to one second data-signal of above-mentioned data flow, wherein above-mentioned the second square-wave signal represents that above-mentioned the first luminescence unit is in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned the second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned the second square-wave signal is later than the rising edge of above-mentioned the first square-wave signal; And according to above-mentioned the second luminescence unit of above-mentioned the second square wave signal driver.
The invention enables in the display cycle probability of each time point generation current comparatively average, thereby can be reduced at luminescence unit the momentary load causing on power line during in same unit interval conducting.
Accompanying drawing explanation
Figure 1A is the schematic diagram of a luminescent system.
Figure 1B is the online electric current of power supply and the graph of a relation of time.
Fig. 2 is a schematic diagram of drive circuit of the present invention.
Fig. 3 is an embodiment of driver module of the present invention.
Fig. 4 is the online electric current of power supply and the graph of a relation of time.
Fig. 5 is the online electric current of power supply and the graph of a relation of time according to another embodiment of the present invention.
Fig. 6 is the online electric current of power supply and the graph of a relation of time according to another embodiment of the present invention.
Fig. 7 is electric current Probability Distribution figure.
Fig. 8 is a schematic diagram of drive circuit of the present invention.
Fig. 9 is a flow chart of the driving method of luminescence unit of the present invention.
Being simply described as follows of symbol in accompanying drawing:
100: luminescent system; Id: electric current; 110,210,310,810: drive circuit; 120,220,320,820: light emitting module; DM1 ~ DMn: driver module; ED1 ~ EDn: luminescence unit; Vp: power line; 330,830:PWM generation unit; 331,831: counter; 332,832: comparator; 340,840: driver element; DP: display cycle; 833:PWM buffer; 850: buffer unit; Sct: count signal; Sdt: data-signal; Ssq: square-wave signal; CLK: clock signal; DL: data wire; Cv1, Cv2, Cvs, Cv2 ', Cvs ': waveform; Cp1, Cp2, Cps, Cp2 ', Cps ': waveform.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate appended graphicly, be described in detail below.
Below explanation is to carry out optimal mode of the present invention.Those skilled in the art should be able to know and do not departing under the prerequisite of spirit of the present invention and framework, when doing a little change, replacement and displacement.Category of the present invention is worked as depending on appended claim.
Fig. 2 is a schematic diagram of drive circuit of the present invention.As shown in Figure 2, drive circuit 210 comprises multiple PWM driver module DM1 ~ DMn, in order to drive respectively the multiple luminescence unit ED1 ~ EDn in light emitting module 220, wherein luminescence unit ED1 ~ EDn coupled in parallel, and each luminescence unit ED1 ~ EDn has, and first end is coupled to a power line Vp and the second end is coupled to corresponding PWM driver module DM1 ~ DMn.According to another embodiment of the present invention, the multiple luminescence unit ED1 ~ EDn in light emitting module 220 can be coupled to corresponding PWM driver module DM1 ~ DMn by above-mentioned first end, and the second end is coupled to earth terminal.
Fig. 3 is an embodiment of driver module of the present invention.PWM driver module 330 is the fluorescent lifetime in a display cycle according to the luminescence unit ED1 ~ EDn of data-signal Sdt decision light emitting module 320.Luminescence unit ED1 ~ EDn coupled in parallel luminescence unit ED1 ~ EDn can be light-emitting diode (light emitting diode, LED).Specifically, as shown in Figure 3, each PWM driver module DM1 ~ DMn at least comprises pulse width modulation (Pulse-width modulation, PWM) generation unit 330 (hereinafter to be referred as PWM generation unit) and driver element 340.PWM generation unit 330 is in order to export a square-wave signal Ssq according to data-signal Sdt.Driver element 340 is coupled to PWM generation unit 330, in order to drive luminescence unit ED1 according to square-wave signal Ssq.The duty ratio (ratio of fluorescent lifetime and display cycle) that wherein data-signal Sdt comprises the display cycle.
When counter 331 is for lower numerical expression counter and while receiving the 1st pulse of clock signal CLK, the value of count signal Sct is 255.Similarly, in the time that counter 331 is received the 2nd pulse of clock signal CLK, the value of count signal Sct is 254.Similarly, in the time that counter 331 is received the 255th pulse of clock signal CLK, the value of count signal Sct is 1, and in the time that counter 331 is received the 256th pulse of clock signal CLK, counter 331 is reset and the value of count signal Sct is 0.
Take data-signal Sdt as 04, and to have 255 unit interval UT1 ~ UT255 be example the display cycle.In the time of unit interval UT1 ~ UT4, the count signal Sct of upper numerical expression counter was 001 ~ 004 (being not more than 004), and therefore square-wave signal Ssq is low voltage level.In the time of unit interval UT5 ~ UT255, the count signal Sct of upper numerical expression counter was 005 ~ 255 (being greater than 004), and therefore square-wave signal Ssq is high-voltage level.On the contrary, in the time of unit interval UT1 ~ UT251, the count signal Sct of lower numerical expression counter was 255 ~ 005 (being greater than 004), and therefore square-wave signal Ssq is high-voltage level.In the time of unit interval UT252 ~ UT255, the count signal Sct of lower numerical expression counter was 004 ~ 001 (being not more than 004), and therefore square-wave signal Ssq is low voltage level.
Therefore, when counter 331 is upper numerical expression counter, and in the time of the unit interval of each display cycle UT1, nearly all luminescence unit all can be switched on, and makes power line Vp can produce maximum current.But, when all luminescence unit ED1 ~ EDn conducting simultaneously during all in the unit interval of each display cycle UT1, power line Vp must provide maximum current, and now electric current is increased to maximum current by zero and will circuit be caused to bad impact, even thereby produce noise.Therefore, in embodiments of the present invention, PWM driver module DM1 ~ DMn is divided into multiple set, described set at least has the first set and the second set, and drive the square-wave signal of the first set reverse each other with the square-wave signal of driving the first set, make the luminescence unit of the first set by chance contrary with ON time and the shut-in time of the luminescence unit of the second set, and then the maximum current that script power line Vp must be born is shared out equally each unit interval to the display cycle.
According to one embodiment of the invention, wherein first to gather the counter comprising be upper numerical expression counter, and second to gather the counter comprising be lower numerical expression counter, part luminescence unit ED1 ~ EDn can be unlocked at unit interval UT1, reduce luminescence unit ED1 ~ EDn and cause the burden on power line Vp in same unit interval conducting.
For instance, light emitting module 220 has luminescence unit ED1 ~ ED16 (n=16), and drive circuit 100 has 16 channels (being driver module DM1 ~ DM16).Driver module DM1 ~ DM16 can be divided into 2 set, and the 1st set is driver module DM1 ~ DM8, and the 2nd set is driver module DM9 ~ DM16.Wherein the counter of driver module DM1 ~ DM8 is upper numerical expression counter, and the counter of driver module DM9 ~ DM16 is lower numerical expression counter.The use that is grouped into explanation of driver module, but be not limited to this.For example, also DMi (i is odd number) can be used as to the 1st set, DMj (j is even number) is used as to the 2nd set.
Fig. 4 is the online electric current of power supply and the graph of a relation of time.According to the type of drive of PWM, the current waveform shown in Fig. 4 is by identical with the square-wave signal of PWM or be reverse.The embodiment of Fig. 3 according to the present invention, the waveform of electric current and square-wave signal Ssq are just reverse.According to another embodiment of the present invention, multiple luminescence unit ED1 ~ EDn can be coupled to corresponding PWM driver module DM1 ~ DMn by first end, and the second end is coupled to earth terminal, and current waveform is wherein identical with square-wave signal Ssq.
As shown in Figure 4, the 1st gathers the electric current producing in power line Vp as shown in waveform Cv1, waveform Cv2 is integrated into the electric current producing on power line Vp for the 2nd, waveform Cvs is for the 1st set and the 2nd be integrated into the electric current producing on power line Vp, and wherein the 1st set is all numerical expression counter with the counter of the 2nd set.Waveform Cv2 ' is integrated into the electric current producing on power line Vp for the 2nd, and wherein the counter of the 2nd set is lower numerical expression counter, and waveform Cvs ' is the sum total of waveform Cv1 and waveform Cv2 '.Can see significantly, by luminescence unit being divided into the 1st set and the 2nd collection is incorporated in the ON time of the 1st set and the 2nd set that staggers in a turn-on cycle DP, on power line Vp, the electric current of institute's load is by certain part-time concentrating in turn-on cycle DP, then be dispersed to whole turn-on cycle DP, make comparatively average (waveform Cvs ' is compared with waveform Cvs) of CURRENT DISTRIBUTION.In this embodiment, the rising edge of waveform Cv1 is positioned at the starting point of display cycle DP, and the trailing edge of waveform Cv2 ' is positioned at the end point of display cycle DP, and the trailing edge of the rising edge of waveform Cv2 ' and waveform Cv1 occurs simultaneously.
Fig. 5 is the online electric current of power supply and the graph of a relation of time according to another embodiment of the present invention.According to the type of drive of PWM, the waveform of the electric current shown in Fig. 5 is by identical with the square-wave signal of PWM or be reverse.The embodiment of Fig. 3 according to the present invention, the waveform of electric current and square-wave signal Ssq are just reverse.According to another embodiment of the present invention, multiple luminescence unit ED1 ~ EDn can be coupled to corresponding PWM driver module DM1 ~ DMn by first end, and the second end is coupled to earth terminal, and current waveform is wherein identical with square-wave signal Ssq.
As shown in Figure 5, the 1st gathers the electric current producing in power line Vp as shown in waveform Cv1, waveform Cv2 ' is integrated into the electric current producing on power line Vp for the 2nd, waveform Cvs ' is for the 1st set and the 2nd be integrated into the electric current producing on power line Vp, and wherein the 1st set is all numerical expression counter with the counter of the 2nd set.In this embodiment, the rising edge of waveform Cv1 is positioned at the starting point of display cycle DP, the trailing edge of waveform Cv2 ' is positioned at the end point of display cycle DP, and the rising edge of waveform Cv2 ' is later than the rising edge of waveform Cv1, thereby causes the waveform of the waveform Cvs ' that represents total current.In addition, in the different display cycles, width (work period) can be different from Cv2 ' for waveform Cv1.
Fig. 6 online electric current of power supply and graph of a relation of time according to another embodiment of the present invention.According to the type of drive of PWM, the waveform of the electric current shown in Fig. 6 is by identical with the square-wave signal of PWM or be reverse.The embodiment of Fig. 3 according to the present invention, the waveform of electric current and square-wave signal Ssq are just reverse.According to another embodiment of the present invention, multiple luminescence unit ED1 ~ EDn can be coupled to corresponding PWM driver module DM1 ~ DMn by first end, and the second end is coupled to earth terminal, and current waveform is wherein identical with square-wave signal Ssq.
As shown in Figure 6, the 1st gathers the electric current producing in power line Vp as shown in waveform Cv1, waveform Cv2 ' is integrated into the electric current producing on power line Vp for the 2nd, waveform Cvs ' is for the 1st set and the 2nd be integrated into the electric current producing on power line Vp, and wherein the rising edge of waveform Cv2 ' is later than the trailing edge of waveform Cv1.In addition, in the different display cycles, width (work period) can be different from Cv2 ' for waveform Cv1.
Fig. 7 is electric current Probability Distribution figure.As shown in Figure 7, the 1st gathers the electric current Probability Distribution figure producing in power line Vp as shown in waveform Cp1, waveform Cp2 is integrated into the electric current Probability Distribution figure producing on power line Vp for the 2nd, and wherein the 1st set is all numerical expression counter with the counter of the 2nd set.Because waveform Cp1 and waveform Cp2 are started to drive corresponding luminescence unit by the starting point of display cycle DP, making electric current is all to start to produce in the starting point of display cycle DP, therefore the highest at the probability of the starting point generation current of display cycle DP.But, conventionally do not have electric current in the end point of display cycle DP, make at the probability of the end point generation current of display cycle DP almost nil.Waveform Cps is the 1st set and the 2nd Probability Distribution figure that is integrated into the total current producing on power line Vp.The electric current Probability Distribution that the 1st set of same phase and the 2nd set jointly produce on power line Vp is identical with waveform Cp1 and waveform Cp2, makes to represent that the 1st gathers and the 2nd to be integrated into the Probability Distribution figure waveform Cps of the total current producing on power line Vp also identical with the Probability Distribution of waveform Cp1 and waveform Cp2.
Waveform Cp2 ' is integrated into the electric current Probability Distribution figure producing on power line Vp for the 2nd, and wherein the counter of the 2nd set is lower numerical expression counter, and waveform Cps ' is integrated into the Probability Distribution figure of the total current producing on power line Vp for the 1st set and the 2nd.Can see significantly, gather and utilize numerical expression counter and lower numerical expression counter to change respectively starting point and the end point of the electric current that driver element exports by luminescence unit being divided into the 1st set and the 2nd, make the probability of each the time point generation current in display cycle DP can be comparatively average, to be reduced in the momentary load being caused on power line Vp.
Fig. 8 is a schematic diagram of drive circuit of the present invention.As shown in Figure 8, drive circuit 810 is similar to drive circuit 310, and difference is that each PWM driver module DM1 ~ DMn comprises buffer unit 850, in order to the data-signal Sdt on data cached line DL, and exports data-signal Sdt to PWM generation unit 830.In each PWM generation unit 830, comprise pulse width modulation buffer 833 (hereinafter to be referred as PWM buffer), come from the data-signal Sdt of buffer unit 850 in order to store, and data-signal Sdt is inputed to comparator 832.
In embodiments of the present invention, comparator 832 has that an anode is coupled to this counter and a negative terminal is coupled to this PWM buffer 833, makes in the time that count signal Sct is greater than data-signal Sdt, and square-wave signal Ssq is high-voltage level.In certain embodiments, comparator 832 has that an anode is coupled to PWM buffer 833 and a negative terminal is coupled to counter 831, makes in the time that data-signal Sdt is greater than count signal Sct, and square-wave signal Ssq is high-voltage level.
Fig. 9 is a flow chart of driving method of the present invention, and as shown in Figure 9, driving method comprises the following steps.
In step S91, described PWM driver module DM1 ~ DMn is at least divided into the first set and the second set, wherein the counter that comprises of PWM driver module in the first set is upper numerical expression counter, and the counter that PWM driver module in the second set comprises is lower numerical expression counter.In step S92, count clock signal CLK by the counter 831 in each PWM driver module from corresponding initial value, so that output count signal Sct.In step S93, the comparator 832 in each PWM driver module produces square-wave signal Ssq according to count signal Sct and corresponding data-signal Sdt.In step S94, drive respectively corresponding luminescence unit ED1 ~ EDn by the driver element 810 in each PWM driver module according to square-wave signal Ssq.
In sum, the count mode of the counter 331 of the counter 331 of the 1st set of the present invention and the 2nd set is not identical, therefore for example reduce luminescence unit ED1 ~ EDn, for example, in the initial unit interval of display cycle (UT1) or last unit interval (UT255) chance of conducting together, be reduced in the load causing on power line Vp.
The foregoing is only preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; anyone familiar with this technology; without departing from the spirit and scope of the present invention; can do on this basis further improvement and variation, therefore protection scope of the present invention is when being as the criterion with the application's the scope that claims were defined.
Claims (17)
1. a drive circuit, is characterized in that, comprising:
One the one PWM driver module, produce one first square-wave signal according to one first data-signal of a data flow, in order to drive one first luminescence unit, wherein above-mentioned the first square-wave signal represents that above-mentioned the first luminescence unit is in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned the first square-wave signal is positioned at the starting point of above-mentioned display cycle; And
One the 2nd PWM driver module, produce one second square-wave signal according to one second data-signal of above-mentioned data flow, in order to drive one second luminescence unit, wherein above-mentioned the second square-wave signal represents that above-mentioned the second luminescence unit is in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned the second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned the second square-wave signal is later than the rising edge of above-mentioned the first square-wave signal.
2. drive circuit according to claim 1, is characterized in that, the rising edge of above-mentioned the second square-wave signal is later than the trailing edge of above-mentioned the first square-wave signal.
3. drive circuit according to claim 1, is characterized in that, an above-mentioned PWM driver module comprises:
One the one PWM generation unit, in order to export above-mentioned the first square-wave signal according to above-mentioned the first data-signal, and
One first driver element, is coupled to an above-mentioned PWM generation unit, and according to above-mentioned the first luminescence unit of above-mentioned the first square wave signal driver, and above-mentioned the 2nd PWM driver module comprises;
One the 2nd PWM generation unit, in order to export above-mentioned the second square-wave signal according to above-mentioned the second data-signal, and
One second driver element, is coupled to above-mentioned the 2nd PWM generation unit, according to above-mentioned the second luminescence unit of above-mentioned the second square wave signal driver.
4. drive circuit according to claim 3, is characterized in that, an above-mentioned PWM generation unit comprises:
One first counter, in order to count a clock signal, so that output one first count signal; And
One first comparator, in order to produce above-mentioned the first square-wave signal according to above-mentioned the first count signal and above-mentioned the first data-signal, and above-mentioned the 2nd PWM generation unit comprises:
One second counter, in order to count above-mentioned clock signal, so that output one second count signal; And
One second comparator, in order to produce above-mentioned the second square-wave signal according to above-mentioned the second count signal and above-mentioned the second data-signal.
5. drive circuit according to claim 4, is characterized in that, above-mentioned the first counter is upper numerical expression counter, and above-mentioned the second counter is lower numerical expression counter.
6. drive circuit according to claim 4, it is characterized in that, above-mentioned the first luminescence unit and above-mentioned the second luminescence unit coupled in parallel, and the first end of above-mentioned the first luminescence unit and above-mentioned the second luminescence unit is coupled to a power line, the second end of above-mentioned the first luminescence unit is coupled to an above-mentioned PWM driver module, and the second end of above-mentioned the second luminescence unit is coupled to above-mentioned the 2nd PWM driver module.
7. drive circuit according to claim 4, is characterized in that, an above-mentioned PWM driver module also comprises:
One first buffer unit, in order to receive above-mentioned the first data-signal, and export above-mentioned the first data-signal to an above-mentioned PWM driver module, and above-mentioned the 2nd PWM driver module also comprises:
One second buffer unit, in order to receive above-mentioned the second data-signal, and exports above-mentioned the second data-signal to above-mentioned the 2nd PWM driver module.
8. drive circuit according to claim 7, is characterized in that, an above-mentioned PWM generation unit also comprises:
One the one PWM buffer, is coupled between above-mentioned the first buffer unit and above-mentioned the first comparator, and in order to store above-mentioned the first data-signal, and above-mentioned the 2nd PWM generation unit also comprises:
One the 2nd PWM buffer, is coupled between above-mentioned the second buffer unit and above-mentioned the second comparator, in order to store above-mentioned the second data-signal.
9. drive circuit according to claim 8, it is characterized in that, above-mentioned the first comparator has an anode and is coupled to above-mentioned the first counter, and one negative terminal be coupled to an above-mentioned PWM buffer, make in the time that above-mentioned the first count signal is greater than above-mentioned the first data-signal, above-mentioned the first square-wave signal is high-voltage level, and above-mentioned the second comparator has an anode and is coupled to above-mentioned the second counter, and a negative terminal is coupled to above-mentioned the 2nd PWM buffer, make in the time that above-mentioned the second count signal is greater than above-mentioned the second data-signal, above-mentioned the second square-wave signal is high-voltage level.
10. drive circuit according to claim 8, it is characterized in that, above-mentioned the first comparator has an anode and is coupled to an above-mentioned PWM buffer, and one negative terminal be coupled to above-mentioned the first counter, make in the time that above-mentioned data-signal is greater than above-mentioned the first count signal, above-mentioned the first square-wave signal is high-voltage level, and above-mentioned the second comparator has an anode and is coupled to above-mentioned the 2nd PWM buffer, and one negative terminal be coupled to above-mentioned the second counter, make in the time that above-mentioned data-signal is greater than above-mentioned the second count signal, above-mentioned the second square-wave signal is high-voltage level.
11. drive circuits according to claim 1, is characterized in that, above-mentioned the first luminescence unit and above-mentioned the second luminescence unit are light-emitting diode.
12. 1 kinds of driving methods, is characterized in that, are applicable to drive one first luminescence unit and one second luminescence unit, and above-mentioned driving method comprises:
Produce one first square-wave signal according to one first data-signal of a data flow, wherein above-mentioned the first square-wave signal represents that above-mentioned the first luminescence unit is in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned the first square-wave signal is positioned at the starting point of a display cycle;
According to above-mentioned the first luminescence unit of above-mentioned the first square wave signal driver;
Produce one second square-wave signal according to one second data-signal of above-mentioned data flow, wherein above-mentioned the second square-wave signal represents that above-mentioned the first luminescence unit is in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned the second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned the second square-wave signal is later than the rising edge of above-mentioned the first square-wave signal; And
According to above-mentioned the second luminescence unit of above-mentioned the second square wave signal driver.
13. driving methods according to claim 12, is characterized in that, the rising edge of above-mentioned the second square-wave signal is later than the trailing edge of above-mentioned the first square-wave signal.
14. driving methods according to claim 12, is characterized in that, the step that produces above-mentioned the first square-wave signal and above-mentioned the second square-wave signal comprises:
By numerical expression rolling counters forward one clock signal on, so that output one first count signal;
By the above-mentioned clock signal of numerical expression rolling counters forward once, so that output one second count signal;
More above-mentioned the first count signal and above-mentioned the first data-signal, to produce above-mentioned the first square-wave signal; And
More above-mentioned the second count signal and above-mentioned the second data-signal, to produce above-mentioned the second square-wave signal.
15. driving methods according to claim 14, it is characterized in that, in the time that above-mentioned the first count signal is greater than above-mentioned the first data-signal, above-mentioned the first square-wave signal is high-voltage level, and in the time that above-mentioned the second count signal is greater than above-mentioned the second data-signal, above-mentioned the second square-wave signal is high-voltage level.
16. driving methods according to claim 14, it is characterized in that, in the time that above-mentioned the first data-signal is greater than above-mentioned the first count signal, above-mentioned the first square-wave signal is high-voltage level, and in the time that above-mentioned the second data-signal is greater than above-mentioned the second count signal, above-mentioned the second square-wave signal is high-voltage level.
17. driving methods according to claim 12, is characterized in that, above-mentioned the first luminescence unit and above-mentioned the second luminescence unit are light-emitting diode.
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| TW247359B (en) * | 1993-08-30 | 1995-05-11 | Hitachi Seisakusyo Kk | Liquid crystal display and liquid crystal driver |
| US20010052827A1 (en) * | 1999-12-22 | 2001-12-20 | Yukio Sugita | Multi-channel pulse width modulation apparatus and down counter |
| CN1758306A (en) * | 2004-06-30 | 2006-04-12 | 佳能株式会社 | Driving circuit of display element, image display apparatus, and television apparatus |
| US20070273678A1 (en) * | 2006-05-29 | 2007-11-29 | Mitsutaka Okita | Liquid crystal display device, light source device, and light source control method |
-
2012
- 2012-12-28 CN CN201210587364.5A patent/CN103906305B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW247359B (en) * | 1993-08-30 | 1995-05-11 | Hitachi Seisakusyo Kk | Liquid crystal display and liquid crystal driver |
| US20010052827A1 (en) * | 1999-12-22 | 2001-12-20 | Yukio Sugita | Multi-channel pulse width modulation apparatus and down counter |
| CN1758306A (en) * | 2004-06-30 | 2006-04-12 | 佳能株式会社 | Driving circuit of display element, image display apparatus, and television apparatus |
| US20070273678A1 (en) * | 2006-05-29 | 2007-11-29 | Mitsutaka Okita | Liquid crystal display device, light source device, and light source control method |
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| CN103906305B (en) | 2016-06-15 |
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