CN103904173A - Epitaxial wafer growing method capable of reducing direct working voltage of chip - Google Patents
Epitaxial wafer growing method capable of reducing direct working voltage of chip Download PDFInfo
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- CN103904173A CN103904173A CN201410110159.9A CN201410110159A CN103904173A CN 103904173 A CN103904173 A CN 103904173A CN 201410110159 A CN201410110159 A CN 201410110159A CN 103904173 A CN103904173 A CN 103904173A
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- growth
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
Abstract
The invention discloses an epitaxial wafer growing method capable of reducing the direct working voltage of a chip, and belongs to semiconductor device processing methods. The greatest difference between the epitaxial wafer growing method and an existing epitaxial wafer growing method lies in that, during growing of a multi-quantum-well luminous layer, a barrier layer is thinned. The method is realized by using one of the following three processing modes or by using more than one of the following three processing modes in cooperation. The three processing modes comprise (1) shortening growing time of the barrier layer, (2) reducing the flow of a III-group source during growing of the barrier layer and (3) increasing the flow of the III-group source during growing of the barrier layer. By means of the epitaxial wafer growing method, the direct working voltage of the LED chip manufactured on an epitaxial wafer formed through the method can be reduced, energy consumption and optical attenuation can be reduced, the service life of the chip can be prolonged, the I-V property of the chip can be improved and the internal quantum efficiency can be increased; meanwhile, partial raw materials can further be saved, the production cost can be lowered and a good reference is provided for industrialization.
Description
Technical field
The invention belongs to manufacture or the process field of semiconductor device or its parts.
Background technology
At present, high brightness blue light-emitting diode (LED) develops very fast, its electric property as brightness, operating voltage, antistatic effect etc. be the index that people pay close attention to and improve always, wherein forward operating voltage Vf is an important parameter judging blue-ray LED electric property.The forward operating voltage of the blue-ray LED conventionally providing is to obtain under given forward current, is generally to record under the forward current of 20mA.The forward operating voltage of blue light InGaN LED is about 3.0～3.5V.The size of forward operating voltage depends primarily on characteristic, chip size and device and the Fabrication Technology of Electrode of semi-conducting material.Forward operating voltage is little, and whole blue-ray LED is low-power, low energy consumption, heat energy is little, light decay is low, the life-span is of a specified duration, and user is wanted to safety relatively.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of epitaxial wafer growth method that reduces chip forward operating voltage, the method can be reduced in the forward operating voltage of the LED chip of making on epitaxial wafer, reduce energy consumption and light decay, extend its life-span, and improve its I-V characteristic, improve internal quantum efficiency; Also can save part raw material simultaneously, reduce manufacturing cost, industrialization is played to good reference value.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of epitaxial wafer growth method that reduces chip forward operating voltage, comprises the steps: epitaxial substrate prebake conditions, GaN buffer growth, U-shaped GaN layer growth, N-type GaN layer growth, multiple quantum well light emitting layer Optimal Growing, P type GaN layer growth; Described multiple quantum well light emitting layer Optimal Growing comprises the operation of attenuate barrier layer thickness, and one or one in this operation is in the following way combined with realization above: the growth time that 1) reduces barrier layer; 2) reduce the flow of III clan source when barrier layer in growth; 3) strengthen the flow of V clan source when barrier layer in growth.
While use separately, 1) concrete operations that reduce the growth time of barrier layer in are: the reduction of the growth time of barrier layer is primary long 1/2-1/3.
While use separately, 2) concrete operations that reduce the flow of III clan source in the time of growth barrier layer are: the 1/4-1/5 that the reduction of III clan source flow is former flow.
While use separately, 3) concrete operations that strengthen the flow of V clan source in are: the 1/8-1/11 that the recruitment of V clan source flow is former flow.
When two kinds of modes are combined with, the concrete operations of variety of way are: 1) reduction of the growth time of barrier layer is primary long 1/4-1/6; 2) 1/7-1/8 that the reduction of III clan source flow is former flow; 3) recruitment of V clan source flow is 1/13-1/15.
When three kinds of modes are combined with, the concrete operations of variety of way are: 1) reduction of the growth time of barrier layer is primary long 1/6-1/8; 2) reduction of the flow of III clan source is 1/10-1/12; 3) recruitment of V clan source flow is 1/16-1/20.
The beneficial effect that adopts technique scheme to produce is: method of the present invention is optimized the barrier layer thickness of quantum well in the time growing into luminescent layer with GaN base epitaxial wafer, and attenuate barrier layer thickness, is conducive to the generation of resonant-tunneling effect; Reducing of barrier layer thickness, reduced the operating voltage of the LED chip of making on epitaxial wafer, also reduce the energy consumption of LED chip and light decay simultaneously, and can extend its useful life, and internal quantum efficiency obtains certain raising, in the process of attenuate barrier layer, can also reduce the absorption of chip body material to photon, more photon can be overflowed from chip internal, improve stability and the light characteristic of chip; To sum up the present invention is by being optimized attenuate to potential barrier thickness, reduce the forward operating voltage of LED chip, not only improved the I-V characteristic of LED chip but also improved its internal quantum efficiency, and can save the raw material of part, reduce manufacturing cost, industrialization has been had to good reference value.Through many MOCVD, the LED that utilizes method of the present invention to prepare is tested, experimental result is that the method can reduce 0.1-0.2V by the forward operating voltage of the LED chip of existing same structure.
Embodiment
Below in conjunction with specific embodiment, the present invention is further detailed explanation.
Embodiment 1
Reduce an epitaxial wafer growth method for chip forward operating voltage, comprise the steps: epitaxial substrate prebake conditions, GaN buffer growth, U-shaped GaN layer growth, N-type GaN layer growth, multiple quantum well light emitting layer Optimal Growing, P type GaN layer growth; Described multiple quantum well light emitting layer Optimal Growing, concrete processing mode is: reduce the growth time of barrier layer, the reduction of the growth time of barrier layer is primary long 1/2-1/3, is preferably 1/2.The growth time of existing barrier layer is 200 ~ 300s, and now preferred growth time is 100 ~ 150s.
The main purpose of above-mentioned Optimal Growing is in the time that epitaxial wafer grows into luminescent layer, quantum well, barrier thickness to be optimized, and attenuate potential barrier is conducive to the generation of resonant-tunneling effect.Owing to building thick reducing, shorten the distance that charge carrier penetrates quantum well structure, make charge carrier ratio be easier to reach corresponding region through potential barrier, and the electron hole logarithm of the recombination luminescence that energy is close increases, improve the probability of electron-hole recombinations, this has not only reduced the operating voltage of LED, and internal quantum efficiency obtains certain raising.In the process of building at attenuate, also can reduce the absorption of chip body material to photon, more photon can be overflowed from chip internal, improve stability and the light characteristic of chip.Therefore by potential barrier thickness is optimized to attenuate, not only improved the I-V characteristic of LED chip but also improved its internal quantum efficiency, and can save the raw material of part, reduced cost, industrialization has been had to good reference value.
Utilize its chip forward operating voltage of finished product epitaxial wafer of the method growth can reduce about 0.15V.
Embodiment 2
As different from Example 1, the concrete processing mode of described multiple quantum well light emitting layer Optimal Growing is: reduce the flow of III clan source when barrier layer in growth, the 1/4-1/5 that the reduction of III clan source flow is former flow preferably 1/5.The MO of the III family source flux that existing barrier layer is selected is 100 ~ 200sccm, and the preferred flow of this method is 100 ~ 150sccm.
Utilize its chip forward voltage of finished product epitaxial wafer of the method growth can reduce about 0.15V.
Embodiment 3
As different from Example 1, the concrete processing mode of described multiple quantum well light emitting layer Optimal Growing is: strengthen the flow of V clan source, the 1/8-1/11 that the recruitment of V clan source flow is former flow, is preferably 1/10.
The existing V NH of family
3the flow in source is 30000 ~ 40000sccm, and the preferred flow of this method is 30000 ~ 35000sccm.
Utilize its chip forward voltage of finished product epitaxial wafer of the method growth can reduce about 0.2V.
Embodiment 4
As different from Example 1, the concrete processing mode of described multiple quantum well light emitting layer Optimal Growing is for adopting in two ways in conjunction with realizing: reduce the growth time of barrier layer, reduce the flow of III clan source simultaneously in the time of growth barrier layer.The reduction of the growth time of barrier layer is primary long 1/4-1/6, is preferably 1/5, the 1/7-1/8 that the reduction of the MO of III family source flux is former flow, preferably 1/8.
When two kinds of modes are used in conjunction with, the selection principle of every kind of mode can not according to independent use time principle, can select voluntarily according to actual needs.
Utilize its chip forward voltage of finished product epitaxial wafer of the method growth can reduce about 0.12V.
Embodiment 5
As different from Example 1, the concrete processing mode of described multiple quantum well light emitting layer Optimal Growing is for adopting in two ways in conjunction with realizing: reduce the growth time of barrier layer, strengthen the flow of V clan source simultaneously.The reduction of the growth time of barrier layer is primary long 1/4-1/6, is preferably 1/5; The NH of V family
3the recruitment of the flow in source is 1/13-1/15, is preferably 1/15.
When two kinds of modes are used in conjunction with, the selection principle of every kind of mode can not according to independent use time principle, can select voluntarily according to actual needs.
Utilize its chip forward voltage of finished product epitaxial wafer of the method growth can reduce about 0.1-0.2V.
Embodiment 6
As different from Example 1, the concrete processing mode of described multiple quantum well light emitting layer Optimal Growing is for adopting in two ways in conjunction with realizing: in the time of growth barrier layer, reduce the flow of III clan source, strengthen the flow of V clan source simultaneously.The 1/7-1/8 that the reduction of the MO of III family source flux is former flow, preferably 1/8.The NH of V family
3the recruitment of source flux is the 1/13-1/15 of former flow, is preferably 1/15.
When two kinds of modes are used in conjunction with, the selection principle of every kind of mode can not according to independent use time principle, can select voluntarily according to actual needs.
Utilize its chip forward voltage of finished product epitaxial wafer of the method growth can reduce about 0.15V.
Embodiment 7
As different from Example 1, the concrete processing mode of described multiple quantum well light emitting layer Optimal Growing is for adopting three kinds of modes in conjunction with realization: the growth time that reduces barrier layer, in the time of growth barrier layer, reduce the flow of III clan source simultaneously, and strengthen the flow of V clan source.The reduction of the growth time of barrier layer is primary long 1/6-1/8, is preferably 1/7; The reduction of the flow in the Mo of III family source is about 1/10-1/12, and preferably 1/11.The NH of V family
3the recruitment of the flow in source is 1/16-1/20, is preferably 1/20.
Utilize its chip forward voltage of finished product epitaxial wafer of the method growth can reduce about 0.1-0.2V.
When three kinds of modes are used in conjunction with, the selection principle of every kind of mode can not according to independent use time principle, can select voluntarily according to actual needs.
Known by above-described embodiment, three kinds of Optimal Growing modes, can select a use, also can select wherein two kinds to be used in conjunction with simultaneously, can also three kinds of modes use simultaneously, as long as tie in, can obtain good technique effect.The present invention is preferably a kind of mode and independently uses, by the reduced thickness of barrier layer to required thickness.Can certainly three kinds of modes be used in conjunction with, rationally adjust parameter, produce a desired effect.
The main creative part of the present invention is: in the time that GaN base epitaxial wafer grows into luminescent layer, the barrier layer thickness of quantum well being optimized to growth, is mainly attenuate barrier layer thickness.After the reduced thickness of barrier layer, be conducive to the generation of resonant-tunneling effect, and the attenuate of barrier layer thickness has reduced the operating voltage of the LED chip of making on this epitaxial wafer, also reduced the energy consumption of LED chip and light decay simultaneously, and can extend its useful life, and LED chip internal quantum efficiency obtains certain raising.
Utilize in the process of attenuate barrier layer of the present invention, can also reduce the absorption of chip body material to photon, more photon can be overflowed from chip internal, improve stability and the light characteristic of chip.
To sum up, the present invention is by being optimized attenuate to potential barrier thickness, reduced the forward operating voltage of the LED chip of making on this epitaxial wafer, not only improve the I-V characteristic of LED chip but also improved its internal quantum efficiency, and can save the raw material of part, reduce manufacturing cost, industrialization has been had to good reference value.
Through many MOCVD, the LED chip that utilizes method of the present invention to prepare is tested, experimental result is that the method can reduce 0.1-0.2V by the forward operating voltage of the LED chip of existing same structure.Compared with existing forward operating voltage, reduce about 3%-6%.
Claims (6)
1. reduce an epitaxial wafer growth method for chip forward operating voltage, it is characterized in that comprising the steps: epitaxial substrate prebake conditions, GaN buffer growth, U-shaped GaN layer growth, N-type GaN layer growth, multiple quantum well light emitting layer Optimal Growing, P type GaN layer growth; Described multiple quantum well light emitting layer Optimal Growing comprises the operation of attenuate barrier layer thickness, and one or one in this operation is in the following way combined with realization above: the growth time that 1) reduces barrier layer; 2) reduce the flow of III clan source when barrier layer in growth; 3) strengthen the flow of V clan source when barrier layer in growth.
2. a kind of epitaxial wafer growth method that reduces chip forward operating voltage according to claim 1, while it is characterized in that using separately, 1) concrete operations that reduce the growth time of barrier layer in are: the reduction of the growth time of barrier layer is primary long 1/2-1/3.
3. a kind of epitaxial wafer growth method that reduces chip forward operating voltage according to claim 1, while it is characterized in that using separately, 2) concrete operations that reduce the flow of III clan source in the time of growth barrier layer are: the 1/4-1/5 that the reduction of III clan source flow is former flow.
4. the concrete operations that strengthen the flow of V clan source a kind of epitaxial wafer growth method that reduces chip forward operating voltage according to claim 1, while it is characterized in that using separately, 3) are: the 1/8-1/11 that the recruitment of V clan source flow is former flow.
5. a kind of epitaxial wafer growth method that reduces chip forward operating voltage according to claim 1, is characterized in that when two kinds of modes are combined with, the concrete operations of variety of way are: 1) reduction of the growth time of barrier layer is primary long 1/4-1/6; 2) 1/7-1/8 that the reduction of III clan source flow is former flow; 3) recruitment of V clan source flow is 1/13-1/15.
6. a kind of epitaxial wafer growth method that reduces chip forward operating voltage according to claim 1, is characterized in that when three kinds of modes are combined with, the concrete operations of variety of way are: 1) reduction of the growth time of barrier layer is primary long 1/6-1/8; 2) reduction of the flow of III clan source is 1/10-1/12; 3) recruitment of V clan source flow is 1/16-1/20.
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