CN103904034A - P-BiCS structure and formation method thereof - Google Patents
P-BiCS structure and formation method thereof Download PDFInfo
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- CN103904034A CN103904034A CN201410078622.6A CN201410078622A CN103904034A CN 103904034 A CN103904034 A CN 103904034A CN 201410078622 A CN201410078622 A CN 201410078622A CN 103904034 A CN103904034 A CN 103904034A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 79
- 239000002131 composite material Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 21
- 238000010276 construction Methods 0.000 claims description 19
- 238000005260 corrosion Methods 0.000 claims description 18
- 230000007797 corrosion Effects 0.000 claims description 18
- 239000007788 liquid Substances 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229960004643 cupric oxide Drugs 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 46
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- Semiconductor Memories (AREA)
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Abstract
The invention discloses a P-BiCS structure and a formation method of the P-BiCS structure. The formation method includes the steps that a substrate and a pad layer are provided; a tubular channel pattern is formed on the top of the pad layer in a photoetching mode, and a groove is etched in the top of the pad layer; a first material is deposited in the groove so that a tubular channel sacrificial layer can be formed; second materials and third materials are deposited on the pad layer alternately so that a laminated structure of an insulation layer and a control grid sacrificial layer can be formed; vertical etched holes are formed in the laminated structure; the bottom of each vertical etched hole makes contact with the end of the tubular channel sacrificial layer; the tubular channel sacrificial layer is removed so that the vertical etched holes in the two ends of the tubular channel sacrificial layer can be communicated; the vertical etched holes are filled with polycrystalline silicon so that a U-shaped electric conduction channel can be formed; a center groove is etched in the laminated structure so that the portions, surrounding the two vertical sections of the U-shaped electric conduction channel, of the laminated structure can be spaced; the control grid sacrificial layer is removed; an electric charge capture composite layer is deposited and formed; a control grid electrode is deposited and formed. The P-BiCS structure with the metal grid electrode and the electric charge capture composite layer can be obtained, and the electrical property is good.
Description
Technical field
The invention belongs to memory manufacturing technology field, be specifically related to a kind of P-BiCS structure and forming method thereof.
Background technology
Because 2D nand flash memory exists micro bottleneck, 3D NAND becomes the developing direction in memory technology field.Researcher proposes a kind of U-shaped vertical-channel 3D and NOT-AND flash (pipe-shaped bit cost scalable, P-BiCS) structure that combines silicon through hole technology.The technology that this P-BiCS adopts is: after alternately laminated gate electrode film and interlayer dielectric, by being embedded in polysilicon passage from the superiors to undermost through hole, carry out stacked multiple memory cell., P-BiCS is linkage unit on U-shaped NAND string.
Existing P-BiCS structure preparation method is: deposit SiO in silicon base
2insulating barrier; Make annular channel pattern by lithography, etch groove; Deposit sacrificial layer material is filled the groove of tubular channel pattern; Planarization, removes the sacrificial layer material at non-annular channel pattern place; Alternating deposition SiO
2insulating barrier and polysilicon control grid layer; Vertical etching laminated construction, to bottom annular channel sacrifice layer, is overlooked etched hole rounded; Etching is removed annular channel sacrifice layer; Deposit electric charge capture composite bed successively; Fill polysilicon as conducting channel; On laminated construction, etch groove, so that the adjacent through-holes being connected by bottom annular channel control grid is around separated.
The P-BiCS structure that above-mentioned prior art obtains has following shortcoming: (1) is owing to having high-temperature technology in follow-up flow process, the alternately etching process prior art of simultaneous oxidation silicon and metal cannot solve, so directly deposited metal is as controlling grid, so just cannot utilize that high-work-function metal grid can bring as more excellent memory electrology characteristics such as higher erasing speeds.(2) owing to also having many high-temperature step after deposit electric charge capture composite bed, and the high-k materials such as hafnium oxide at high temperature can crystallization cause device electrology characteristic to decline, therefore also cannot use high-k material as electric charge capture composite bed, affect the electric property of device.
Summary of the invention
The present invention is intended at least solve cannot adopting metal gate, cannot using the technical problem of high-k material as electric charge capture composite bed of existing in prior art.
For this reason, one object of the present invention is to propose that a kind of metal gate is replaced, high-k material is as the formation method of the P-BiCS structure of electric charge capture composite bed.
Another object of the present invention is to propose a kind of P-BiCS structure of the electric charge capture composite bed with metal gate and high-k material.
To achieve these goals, according to the formation method of the P-BiCS structure of the embodiment of one aspect of the invention, can comprise the following steps: substrate is provided, and forms laying on described substrate; Carve annular channel pattern and etch groove in described laying top light; In described groove, deposit the first material is to form annular channel sacrifice layer; On described laying, alternating deposition the second material and the 3rd material are to form the laminated construction of insulating barrier and control gate sacrifice layer; In described laminated construction, form vertical etched hole, the bottom of described vertical etched hole contacts with the end of described annular channel sacrifice layer; Remove described annular channel sacrifice layer, so that the described vertical etched hole at described annular channel sacrifice layer two ends is communicated with; Fill polysilicon to form U-shaped conductive channel; Etching central authorities groove in described laminated construction, to separate the described laminated construction around separately of two vertical sections of described U-shaped conductive channel; Remove described control gate sacrifice layer; Deposit forms electric charge capture composite bed, and described electric charge capture composite bed covers the surface of two vertical sections of described insulating barrier and described U-shaped conductive channel; Deposited metal gate material is with formation control grid.
According to the formation method of the P-BiCS structure of the embodiment of the present invention, can form the P-BiCS structure with metal gates and the electric charge capture lamination layer structure that contains high-k material, the higher erasing speed of bringing that can make 3D and NOT-AND flash utilize metal gates, larger memory window value, the advantage of better charge-retention property; Can utilize high-k material as electric charge capture composite bed, device is had and be better than traditional SONOS(Si/SiO simultaneously
2/ SiN/SiO
2/ Si) flash memory charge storage density, better the electric charge blocking capability on barrier layer.
In addition, can also there is following additional technical feature according to the formation method of the P-BiCS structure of the embodiment of the present invention:
In an example of the present invention, adopt the first corrosive liquid wet etching to remove described annular channel sacrifice layer, wherein, described the first corrosive liquid is greater than the corrosion rate to described the second material to the corrosion rate of described the first material, and is greater than the corrosion rate to described the 3rd material.
In an example of the present invention, adopt the second corrosive liquid wet etching to remove described control gate sacrifice layer, wherein, described the second corrosive liquid is greater than the corrosion rate to described the second material to the corrosion rate of described the 3rd material, and is greater than the corrosion rate to described polysilicon.
In an example of the present invention, described deposit forms electric charge capture composite bed and comprises: deposit electric charge tunnel layer material, charge storage layer material and electric charge barrier layer material successively.
In an example of the present invention, described the first material is aluminium oxide or cupric oxide.
In an example of the present invention, described the second material is silicon dioxide.
In an example of the present invention, described the 3rd material is silicon nitride.
In an example of the present invention, overlook described vertical etched hole rounded.
In an example of the present invention, described metal gate material is tungsten.
The P-BiCS structure of embodiment according to a further aspect of the invention, this P-BiCS structure is to make by above-mentioned method.
According to the P-BiCS structure of the embodiment of the present invention, there is the electric charge capture lamination layer structure of metal gates and high-k material, the higher erasing speed that can make 3D and NOT-AND flash utilize metal gates to bring, larger memory window value, the better advantage of charge-retention property; Can utilize high-k material as electric charge capture composite bed, device is had and be better than traditional SONOS(Si/SiO simultaneously
2/ SiN/SiO
2/ Si) flash memory charge storage density, better the electric charge blocking capability on barrier layer.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 to Figure 11 is the process schematic diagram of the formation method of the P-BiCS structure of the embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
First aspect present invention proposes a kind of formation method of P-BiCS structure, comprises the following steps:
S1., substrate is provided, and on substrate, forms laying.
As shown in Figure 1, provide single crystal silicon material substrate 101, and form SiO on substrate 101
2laying 102.
S2. carve annular channel pattern and etch groove in laying top light.
As shown in Figure 2, carve annular channel pattern and etch groove 102a in the top light of laying 102.
It should be noted that, although only show a groove in figure, in practical application, on a wafer, can etch several parallel grooves.
S3. in groove deposit the first material to form annular channel sacrifice layer.
As shown in Figure 3, deposition the first material, to fill full groove 102a, then carries out planarization, removes first material at non-tubular pattern place, has obtained the annular channel sacrifice layer 103 of the first material.Wherein, the first material can be the materials such as aluminium oxide or cupric oxide.
S4. on laying alternating deposition the second material and the 3rd material to form the laminated construction of insulating barrier and control gate sacrifice layer.
As shown in Figure 4, on laying 102 alternating deposition the second material and the 3rd material to form the laminated construction of insulating barrier 104 and control gate sacrifice layer 105.The second material can be SiO
2deng material.The 3rd material can be the materials such as SiN.
S5. in laminated construction, form vertical etched hole, the bottom of vertical etched hole contacts with the end of annular channel sacrifice layer.
As shown in Figure 5 a, in the laminated construction of insulating barrier 104 and control gate sacrifice layer 105, form vertical etched hole 106.The bottom of this vertical etched hole 106 contacts with the end of annular channel sacrifice layer 103.Vertical etched hole 106 can be circular port.Fig. 5 b is the vertical view of the structure shown in Fig. 5 a, and Fig. 5 b has demonstrated the situation on a wafer with multipair vertical etched hole.
S6. remove annular channel sacrifice layer, so that the vertical etched hole at annular channel sacrifice layer two ends is communicated with.
As shown in Figure 6, remove annular channel sacrifice layer 103, so that the vertical etched hole 106 at annular channel sacrifice layer 103 two ends is communicated with.Alternatively, adopt the first corrosive liquid wet etching to remove annular channel sacrifice layer 106.Wherein, the first corrosive liquid is greater than the corrosion rate to the second material to the corrosion rate of the first material, and is greater than the corrosion rate to the 3rd material.In one embodiment, the first corrosive liquid can be hydrochloric acid.
S7. fill polysilicon to form U-shaped conductive channel.
As shown in Figure 7a, fill polysilicon to form U-shaped conductive channel 107.This U-shaped conductive channel 107 has occupied the locus of the vertical etched hole 106 at original annular channel sacrifice layer 103 and two ends thereof.Fig. 7 b is the vertical view of the structure shown in Fig. 7 a, and Fig. 7 b has demonstrated the situation on a wafer with multiple U-shaped conductive channels.
S8. etching central authorities groove in laminated construction, to separate the laminated construction around separately of two vertical sections of U-shaped conductive channel.
As shown in Figure 8 a, etching central authorities groove 108 in the laminated construction of insulating barrier 104 and control gate sacrifice layer 105, to separate the laminated construction around separately of two vertical sections of U-shaped conductive channel 107.At this moment, expose the part side of insulating barrier 104 and control gate sacrifice layer 105, be convenient to the follow-up wet etching that carries out.Fig. 8 b is the vertical view of the structure shown in Fig. 8 a, and Fig. 8 b has demonstrated on a wafer and formed strip groove by the separated situation in multiple U-shaped conductive channels both sides.
S9. remove control gate sacrifice layer.
As shown in Figure 9, remove control gate sacrifice layer 105, now in original laminated construction, be only left insulating barrier 104.Alternatively, adopt the second corrosive liquid wet etching to remove control gate sacrifice layer 105, wherein, the second corrosive liquid is greater than the corrosion rate to the second material to the corrosion rate of the 3rd material, and is greater than the corrosion rate to polysilicon.In one embodiment, the second corrosive liquid can be phosphoric acid.
S10. deposit forms electric charge capture composite bed, and electric charge capture composite bed covers the surface of two vertical sections of insulating barrier and U-shaped conductive channel.
As shown in figure 10, deposit forms electric charge capture composite bed 109, and this electric charge capture composite bed 109 covers the surface of two vertical sections of insulating barrier 104 and U-shaped conductive channel 107.Alternatively, deposit formation electric charge capture composite bed 109 specifically comprises: deposit electric charge tunnel layer material, charge storage layer material and electric charge barrier layer material successively.
S11. deposited metal gate material is with formation control grid.
As shown in figure 11, plated metal grid material is to be full of control grid part, and then etching is removed excess metal grid material, and different control between grid 110 is not connected mutually.In addition, can also between multiple control grids 110, fill insulating layer material isolates.Alternatively, metal gate material is tungsten.
In sum, the formation method of P-BiCS structure of the present invention can form the P-BiCS structure with metal gates and the electric charge capture lamination layer structure that contains high-k material, the higher erasing speed of bringing that can make 3D and NOT-AND flash utilize metal gates, larger memory window value, the advantage of better charge-retention property; Can utilize high-k material as electric charge capture composite bed, device is had and be better than traditional SONOS(Si/SiO simultaneously
2/ SiN/SiO
2/ Si) flash memory charge storage density, better the electric charge blocking capability on barrier layer.
Second aspect present invention also proposes a kind of P-BiCS structure, this P-BiCS structure is to make by the formation method of above-disclosed any P-BiCS structure of the present invention, therefore also there is the electric charge capture lamination layer structure of metal gates and high-k material, the higher erasing speed that can make 3D and NOT-AND flash utilize metal gates to bring, larger memory window value, the better advantage of charge-retention property; Can utilize high-k material as electric charge capture composite bed, device is had and be better than traditional SONOS(Si/SiO simultaneously
2/ SiN/SiO
2/ Si) flash memory charge storage density, better the electric charge blocking capability on barrier layer.
In description of the invention, it will be appreciated that, term " " center ", " longitudinally ", " laterally ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", " counterclockwise ", " axially ", " radially ", orientation or the position relationship of indications such as " circumferentially " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, rather than device or the element of indication or hint indication must have specific orientation, with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.
In addition, term " first ", " second " be only for describing object, and can not be interpreted as indication or hint relative importance or the implicit quantity that indicates indicated technical characterictic.Thus, one or more these features can be expressed or impliedly be comprised to the feature that is limited with " first ", " second ".In description of the invention, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the terms such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and for example, can be to be fixedly connected with, and can be also to removably connect, or integral; Can be mechanical connection, can be also electrical connection; Can be to be directly connected, also can indirectly be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements.For the ordinary skill in the art, can understand as the case may be above-mentioned term concrete meaning in the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic " on " or D score can be that the first and second features directly contact, or the first and second features are by intermediary indirect contact.And, First Characteristic Second Characteristic " on ", " top " and " above " but First Characteristic directly over Second Characteristic or oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " can be First Characteristic under Second Characteristic or tiltedly, or only represent that First Characteristic level height is less than Second Characteristic.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, to the schematic statement of above-mentioned term not must for be identical embodiment or example.And, specific features, structure, material or the feature of description can one or more embodiment in office or example in suitable mode combination.In addition, those skilled in the art can carry out combination and combination by the different embodiment that describe in this specification or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, modification, replacement and modification.
Claims (10)
1. a formation method for P-BiCS structure, is characterized in that, comprises the following steps:
Substrate is provided, and forms laying on described substrate;
Carve annular channel pattern and etch groove in described laying top light;
In described groove, deposit the first material is to form annular channel sacrifice layer;
On described laying, alternating deposition the second material and the 3rd material are to form the laminated construction of insulating barrier and control gate sacrifice layer;
In described laminated construction, form vertical etched hole, the bottom of described vertical etched hole contacts with the end of described annular channel sacrifice layer;
Remove described annular channel sacrifice layer, so that the described vertical etched hole at described annular channel sacrifice layer two ends is communicated with;
Fill polysilicon to form U-shaped conductive channel;
Etching central authorities groove in described laminated construction, to separate the described laminated construction around separately of two vertical sections of described U-shaped conductive channel;
Remove described control gate sacrifice layer;
Deposit forms electric charge capture composite bed, and described electric charge capture composite bed covers the surface of two vertical sections of described insulating barrier and described U-shaped conductive channel;
Deposited metal gate material is with formation control grid.
2. the formation method of P-BiCS structure according to claim 1, it is characterized in that, adopt the first corrosive liquid wet etching to remove described annular channel sacrifice layer, wherein, described the first corrosive liquid is greater than the corrosion rate to described the second material to the corrosion rate of described the first material, and is greater than the corrosion rate to described the 3rd material.
3. the formation method of P-BiCS structure according to claim 1, it is characterized in that, adopt the second corrosive liquid wet etching to remove described control gate sacrifice layer, wherein, described the second corrosive liquid is greater than the corrosion rate to described the second material to the corrosion rate of described the 3rd material, and is greater than the corrosion rate to described polysilicon.
4. the formation method of P-BiCS structure according to claim 1, is characterized in that, described deposit forms electric charge capture composite bed and comprises: deposit electric charge tunnel layer material, charge storage layer material and electric charge barrier layer material successively.
5. the formation method of P-BiCS structure according to claim 1, is characterized in that, described the first material is aluminium oxide or cupric oxide.
6. the formation method of P-BiCS structure according to claim 1, is characterized in that, described the second material is silicon dioxide.
7. the formation method of P-BiCS structure according to claim 1, is characterized in that, described the 3rd material is silicon nitride.
8. the formation method of P-BiCS structure according to claim 1, is characterized in that, overlooks described vertical etched hole rounded.
9. the formation method of P-BiCS structure according to claim 1, is characterized in that, described metal gate material is tungsten.
10. a P-BiCS structure, is characterized in that, is to make by the method described in any one in claim 1-9.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623458A (en) * | 2008-12-24 | 2012-08-01 | 海力士半导体有限公司 | Vertical channel type nonvolatile memory device and method for fabricating the same |
| US20120217564A1 (en) * | 2011-02-25 | 2012-08-30 | Tang Sanh D | Semiconductor charge storage apparatus and methods |
| US20130221423A1 (en) * | 2012-02-29 | 2013-08-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623458A (en) * | 2008-12-24 | 2012-08-01 | 海力士半导体有限公司 | Vertical channel type nonvolatile memory device and method for fabricating the same |
| US20120217564A1 (en) * | 2011-02-25 | 2012-08-30 | Tang Sanh D | Semiconductor charge storage apparatus and methods |
| US20130221423A1 (en) * | 2012-02-29 | 2013-08-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing same |
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