CN103887234A - TFT array substrate and manufacture method thereof - Google Patents
TFT array substrate and manufacture method thereof Download PDFInfo
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- CN103887234A CN103887234A CN201210560105.3A CN201210560105A CN103887234A CN 103887234 A CN103887234 A CN 103887234A CN 201210560105 A CN201210560105 A CN 201210560105A CN 103887234 A CN103887234 A CN 103887234A
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- 239000000758 substrate Substances 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000011347 resin Substances 0.000 claims abstract description 61
- 229920005989 resin Polymers 0.000 claims abstract description 61
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 238000009413 insulation Methods 0.000 claims description 69
- 238000002161 passivation Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 33
- 239000000203 mixture Substances 0.000 claims description 7
- 229910018540 Si C Inorganic materials 0.000 claims description 6
- 229910018557 Si O Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 6
- 230000032798 delamination Effects 0.000 claims description 3
- 230000035515 penetration Effects 0.000 abstract 1
- 238000002834 transmittance Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- -1 indium tin metal oxide Chemical class 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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- Thin Film Transistor (AREA)
Abstract
The invention discloses a thin film transistor (TFT) array substrate which comprises a base substrate, a TFT, grid lines, data lines and a pixel electrode, wherein the TFT, the grid lines, the data lines and the pixel electrode are formed on the base substrate; the area of the TFT array substrate, except the TFT area, and the structure, except the grid lines, the data lines and the pixel electrode are made of organic resin. The invention also discloses a manufacture method of the thin film transistor (TFT) array substrate. According to the TFT array substrate and the manufacture method, the loss of penetration light can be reduced, and transmittance of the whole TFT array substrate is improved.
Description
Technical field
The present invention relates to array base palte technical field, relate in particular to a kind of thin-film transistor (Thin FilmTransistor, TFT) array base palte and manufacture method thereof.
Background technology
At present, in TFT production technology, gate insulation layer and passivation layer generally use silicon nitride (SiNx) material, and SiNx material itself has advantages of good stability, good insulating.But, use the tft array substrate of SiNx material as gate insulation layer and passivation layer, the transmitance of tft array substrate can only remain on 85% left and right, along with the increase of SiNx consumption, tft array substrate stress sharply becomes greatly, causes transmitance reduction and base plate deformation to become large; And rough surface is caused larger impact on rear end to the liquid crystal aligning in box technique (cellrubbing) technique, makes liquid crystal aligning disorder, easily cause and show extremely.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of tft array substrate and manufacture method thereof, can reduce the loss of transmitted light, improves the transmitance of tft array substrate.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention provides a kind of thin-film transistor tft array substrate, comprising: underlay substrate, be formed at TFT, grid line, data wire and pixel electrode on described underlay substrate, wherein,
On region on described tft array substrate except TFT region, the material of the structure except described grid line, data wire and pixel electrode is organic resin.
Here, described tft array substrate also comprises: gate insulation layer; Wherein, described gate insulation layer comprises: be formed at the gate insulation layer on described TFT region;
Described tft array substrate also comprises: the passivation layer between described TFT and described pixel electrode;
The layer that described organic resin forms has the upper surface of planarization;
The refractive index of described underlay substrate is identical with the refractive index of described organic resin;
Described organic resin comprises in the non-photosensitive type organic resin material that contains Si-C or contain Si-O structure on main chain one or both combination;
Wherein, described TFT comprises: gate electrode, be formed at the gate insulation layer on described gate electrode and be formed at active layer, source signal electrode and the leakage signal electrode on described gate insulation layer; Or,
Source signal electrode, leakage signal electrode and active layer, and be formed at the gate insulation layer on described source signal electrode, leakage signal electrode and described active layer, be formed at the gate electrode on described gate insulation layer.
The present invention also provides a kind of manufacture method of above-mentioned thin-film transistor tft array substrate, and the method comprises:
On underlay substrate, form TFT, grid line, data wire and pixel electrode, wherein,
On region on described tft array substrate except TFT region, the structure except described grid line, data wire and pixel electrode all adopts organic resin to form.
Here in the described step that forms TFT on underlay substrate, comprise the step of the gate insulation layer on the region beyond the above TFT of described underlay substrate being carried out to etching; And on the region being etched away at described gate insulation layer, form the step of organic resin layer;
Described on underlay substrate, form TFT after and forming before described pixel electrode, described method also comprises: form passivation layer; Wherein,
On the described region being etched away at described gate insulation layer, form organic resin layer, for:
Adopt organic resin to form described passivation layer, described passivation layer covers the region beyond described TFT region and described TFT region; Or,
On the underlay substrate with described TFT, form described passivation layer, passivation layer on the gate insulation layer being etched away on region beyond described TFT is carried out to etching, on the region being etched away at described passivation layer, form described organic resin layer, described passivation layer comprises described organic resin layer.
Wherein, the described TFT that forms on underlay substrate, comprising:
On underlay substrate, form gate electrode;
On the underlay substrate with described gate electrode, form described gate insulation layer;
On described gate insulation layer, form active layer and source signal electrode, leakage signal electrode; Or,
On underlay substrate, form source signal electrode, leakage signal electrode and active layer;
On the underlay substrate with described source signal electrode, leakage signal electrode and described active layer, form described gate insulation layer;
On described gate insulation layer, form described gate electrode.
Described active layer and source signal electrode, the leakage signal electrode of forming on described gate insulation layer, for: in a mask plate composition technique, form described active layer and described source signal electrode, leakage signal electrode by halftoning technique.
Described employing organic resin forms described passivation layer, described passivation layer covers the region beyond described TFT region and described TFT region, described passivation layer comprises that described passivation layer and the described pixel electrode in described organic resin layer is in a mask plate composition technique, forms by halftoning technique and delamination technique.
TFT LCD array base palte provided by the present invention and manufacture method thereof, have following advantage and disadvantage:
In the present invention, adopt organic resin as smoothing material, so, on the one hand, because organic resin is that high permeability, stress are low, the material of planarization, good uniformity, can effectively reduce the deformation quantity of TFT LCD array base palte and prevent pixel layer overlap joint time, there is fracture; On the other hand, due to the selected refractive index of non-photosensitive type organic resin material of the present invention and the refractive index of array base palte basically identical, can effectively reduce the loss of throw light, improve the transmitance of tft array substrate.
Accompanying drawing explanation
Fig. 1 is the TFT structural section schematic diagram of thin-film transistor tft array substrate of the present invention;
Fig. 2 to Fig. 7 is the schematic cross-section of TFT structure in thin-film transistor tft array substrate manufacture process of the present invention.
Description of reference numerals
1, substrate, 2, gate electrode, 3, gate insulation layer, 4, active layer, 5, source leakage signal electrode layer, 5a, source signal electrode, 5b, leakage signal electrode, 6, photoresist, 7, raceway groove, 8, passivation layer, 9, via hole, 10, pixel electrode.
Embodiment
Owing to can making TFT entirety become smooth after use organic resin, can make cell rubbing technique be more prone to control, and the refractive index of organic resin and the refractive index of substrate basically identical, therefore the organic resin that, the present invention adopts not only can be used as smoothing material, but also can improve the transmitance of tft array substrate.
A kind of thin-film transistor tft array substrate, comprise: underlay substrate, be formed at TFT, grid line, data wire and pixel electrode on described underlay substrate, wherein, on region on described tft array substrate except TFT region, the structure except described grid line, data wire and pixel electrode all adopts organic resin to form.
Here, described thin-film transistor tft array substrate also comprises: gate insulation layer; Wherein, described gate insulation layer comprises: be formed at the gate insulation layer on described TFT region;
Described thin-film transistor tft array substrate also may comprise: the passivation layer between described TFT and described pixel electrode; The material that forms described passivation layer can be organic resin, can be also the composite material of organic resin and other materials.
On thin-film transistor tft array substrate, have by grid line and data wire and intersect and define the multiple pixel cells that form, in each pixel cell, comprise TFT and pixel electrode, therefore, above-mentioned " on the region on described tft array substrate except TFT region, except described grid line, structure beyond data wire and pixel electrode all adopts organic resin to form " refer to, in each pixel cell, (be in each unit area being surrounded by grid line and data wire, do not comprise grid line and data wire), structure except TFT structure and pixel electrode structure all adopts organic resin to form.
Conventionally, TFT structure comprises gate electrode, gate insulation layer, active layer, source signal electrode and leakage signal electrode, wherein said gate electrode, active layer, source signal electrode and leakage signal electrode are generally all formed in TFT region, rather than the All Ranges of covering pixel cell, and gate insulation layer covers TFT region and region corresponding to pixel electrode conventionally in the prior art; And in the present embodiment, in pixel cell, described gate insulation layer is not cover region that pixel electrode is corresponding, this feature preferably can realize in the following way:
In the time forming described gate insulation layer, first form the gate insulation layer material that covers TFT region and pixel electrode area (described pixel electrode area is the real region in Fig. 1), in follow-up step, again gate insulation layer material corresponding described pixel electrode area is etched away; Or, in the time forming gate insulation layer, utilize mask composition technique only on TFT region, to form gate insulation layer material, do not form gate insulation layer material in pixel electrode area, thereby form the pattern of needed gate insulation layer.
Here the layer that, described organic resin forms has the upper surface of planarization;
The refractive index of described underlay substrate is identical with the refractive index of described organic resin;
Described organic resin comprises in the non-photosensitive type organic resin material that contains Si-C or contain Si-O structure on main chain one or both combination;
Described TFT comprises: gate electrode, be formed at the gate insulation layer on described gate electrode and be formed at active layer, source signal electrode and the leakage signal electrode on described gate insulation layer; Or,
Described TFT is top gate structure, comprises: source signal electrode, leakage signal electrode and active layer, and be formed at the gate insulation layer on described source signal electrode, leakage signal electrode and described active layer, be formed at the gate electrode on described gate insulation layer.
In such scheme, organic resin material is that high permeability, stress are low, the material of planarization, good uniformity, occurs fracture can effectively reduce the deformation quantity of tft array substrate and prevent pixel layer overlap joint time; On the other hand, due to the selected refractive index of non-photosensitive type organic resin material of the present invention and the refractive index of array base palte basically identical, can effectively reduce the loss of throw light, improve the transmitance of tft array substrate.
Fig. 1 is the TFT structural section schematic diagram of thin-film transistor tft array substrate of the present invention, on described thin-film transistor tft array substrate, also comprise grid line and data wire, the cross section of TFT structure and the cross section of pixel electrode area in this figure, are only provided, not shown grid line and data wire.
Described thin-film transistor tft array substrate comprises:
Wherein, described TFT comprises: gate electrode 2, be formed at gate insulation layer 3 on described gate electrode 2, be formed at active layer 4, source leakage signal electrode layer 5 on described gate insulation layer 3, be formed at the raceway groove 7 on source leakage signal electrode layer 5, described raceway groove 7 blocks source leakage signal electrode layer 5 above described active layer 4, described disconnected source leakage signal electrode layer 5 is divided into: source signal electrode 5a, leakage signal electrode 5b;
In conjunction with the above, the concrete structure of described thin-film transistor FTF array base palte, comprising:
Here, described passivation layer 6 covers the region beyond described TFT region and described TFT region, and the material that described in the present embodiment, passivation layer adopts is organic resin.
Wherein, described organic resin comprises in the non-photosensitive type organic resin material that contains Si-C or contain Si-O structure on main chain one or both combination;
Described gate insulation layer can be silicon nitride (SiNx) material;
Described pixel layer is transparent conductive material;
Described transparent conductive material is nano indium tin metal oxide, indium zinc metal oxide or tin indium oxide material.
The present invention adopts and on main chain, contains Si-C, or the non-photosensitive type organic resin material that contains Si-O structure is as passivation layer, replace traditional silicon nitride (SiNx) material, so, on the one hand, because refractive index and the substrate refractive index of organic resin material that the present invention adopts is basic identical, when light is during from substrate viewing area below incident shown in Fig. 1, through the basically identical film of two-layer transmissivity, that is: when light is through substrate and organic resin layer, can not cause refraction and the reflection of light, and pixel layer is very thin, impact on light is very little, therefore can realize the maximization of transmitance, effectively reduce the loss of throw light, improve the transmitance of tft array substrate, transmitance maximum can reach 93%, on the other hand, the organic resin material that the present invention adopts has advantages of that stress is low, planarization good, good uniformity, can effectively reduce the deformation quantity of tft array substrate, and can prevent from occurring rupturing when pixel layer from overlapping.
The present invention also provides the manufacture method of thin-film transistor tft array substrate shown in Fig. 1, and specific implementation step comprises:
Step 1: deposit gate electrode 2 on underlay substrate 1;
Step 2: deposit gate insulation layer 3 on the underlay substrate with described gate electrode 2;
Step 3: deposit successively active layer 4, source leakage signal electrode layer 5 on described gate insulation layer 3, as shown in Figure 2; On the source leakage signal electrode layer 5 shown in Fig. 2, apply photoresist 6, as shown in Figure 3; In the structure shown in Fig. 3, expose, develop, get rid of described source leakage signal electrode layer 5 two end portions photoresists 6, expose two end portions source leakage signal electrode layer 5, and get rid of the part photoresist at raceway groove 7 places, as shown in Figure 4;
Step 4: by the source leakage signal electrode layer 5 exposing and described in corresponding active layer 4, the gate insulation layer 3 at leakage signal electrode layer 5 places, source of exposing etch away, until expose the part underlay substrate 1 at two ends, as shown in Figure 5;
Step 5: the photoresist 6 on source leakage signal electrode layer 5 is peeled off, and etch raceway groove 7 on described source leakage signal electrode layer 5, make described raceway groove 7 on described active layer 4, block source leakage signal electrode layer 5, source leakage signal electrode layer 5 is divided into: source signal electrode 5a, leakage signal electrode 5b, and exposed portions serve active layer 4, as shown in Figure 6;
It should be noted that step 3 to step 5 can also be:
Apply photoresist 6 at described gate insulation layer 3, and expose, develop, get rid of described gate insulation layer 3 two end portions photoresists 6, expose two end portions gate insulation layer 3, the gate insulation layer exposing 3 is etched away; Said process is: to the etching of carrying out of the gate insulation layer 3 on the region beyond described underlay substrate 1 the above TFT;
On described source leakage signal electrode layer 5, etch raceway groove 7, make described raceway groove 7 on described active layer 4, block source leakage signal electrode layer 5, source leakage signal electrode layer 5 is divided into: source signal electrode 5a, leakage signal electrode 5b, and exposed portions serve active layer 4;
Step 6: deposit passivation layer 8 on the underlay substrate with described source signal electrode 5a, leakage signal electrode layer 5b, raceway groove 7, active layer 4, gate insulation layer 3 and gate electrode 2, as shown in Figure 7;
Step 7: expose in the position that need to manufacture via hole, development and etching, etch via hole 9 on passivation layer 8;
Step 8: pixel deposition electrode 10 on described passivation layer 8, described pixel electrode 10 is connected with leakage signal electrode 5b by described via hole 9, as shown in Figure 1.
Wherein, the step that forms active layer 4 and source signal electrode 5a, leakage signal electrode 5b is in a mask plate composition technique, forms described active layer 4 and described source signal electrode 5a, leakage signal electrode 5b by halftoning (Half tone) technique;
The step that forms described passivation layer 8 and described pixel electrode 10 is in a mask plate composition technique, forms by halftoning technique and delamination (Lift off) technique;
Here, described TFT is the TFT of non-top gate structure, basically identical owing to thering is manufacture method and the said process of tft array substrate of TFT of top gate structure, therefore, do not repeating herein, above-mentioned manufacture method is only for explaining the manufacture process of tft array substrate of the present invention, not for limiting the manufacture method of tft array substrate of the present invention.
Here, it should be noted that, described passivation layer can be directly organic resin, also can adopt the composite material of organic resin and other materials, but, organic resin in described passivation layer needs the viewing area shown in whole coverage diagrams 1, thereby reaches the object of the transmitance that improves tft array substrate, and the passivation layer of non-display area can adopt organic resin, also can adopt the material of thinking except organic resin.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention.
Claims (16)
1. a manufacture method for thin-film transistor tft array substrate, is characterized in that, the method comprises:
On underlay substrate, form TFT, grid line, data wire and pixel electrode, wherein,
On region on described tft array substrate except TFT region, the structure except described grid line, data wire and pixel electrode all adopts organic resin to form.
2. manufacture method according to claim 1, is characterized in that, in the described step that forms TFT on underlay substrate, comprises the step of the gate insulation layer on the region beyond the above TFT of described underlay substrate being carried out to etching; And on the region being etched away at described gate insulation layer, form the step of organic resin layer.
3. manufacture method according to claim 2, is characterized in that, described on underlay substrate, form TFT after and forming before described pixel electrode, described method also comprises: form passivation layer; Wherein,
On the described region being etched away at described gate insulation layer, form organic resin layer, for:
Adopt organic resin to form described passivation layer, described passivation layer covers the region beyond described TFT region and described TFT region; Or,
On the underlay substrate with described TFT, form described passivation layer, passivation layer on the gate insulation layer being etched away on region beyond described TFT is carried out to etching, on the region being etched away at described passivation layer, form described organic resin layer, described passivation layer comprises described organic resin layer.
4. manufacture method according to claim 1, is characterized in that, the layer that described organic resin forms has the upper surface of planarization.
5. manufacture method according to claim 1, is characterized in that, the described TFT that forms on underlay substrate, comprising:
On underlay substrate, form gate electrode;
On the underlay substrate with described gate electrode, form described gate insulation layer;
On described gate insulation layer, form active layer and source signal electrode, leakage signal electrode; Or,
On underlay substrate, form source signal electrode, leakage signal electrode and active layer;
On the underlay substrate with described source signal electrode, leakage signal electrode and described active layer, form described gate insulation layer;
On described gate insulation layer, form described gate electrode.
6. manufacture method according to claim 5, it is characterized in that, described active layer and source signal electrode, the leakage signal electrode of forming on described gate insulation layer, for: in a mask plate composition technique, form described active layer and described source signal electrode, leakage signal electrode by halftoning technique.
7. manufacture method according to claim 3, it is characterized in that, described employing organic resin forms described passivation layer, described passivation layer covers the region beyond described TFT region and described TFT region, described passivation layer comprises that described passivation layer and the described pixel electrode in described organic resin layer is in a mask plate composition technique, forms by halftoning technique and delamination technique.
8. manufacture method according to claim 1, is characterized in that, the refractive index of described underlay substrate is identical with the refractive index of described organic resin.
9. manufacture method according to claim 1, is characterized in that, described organic resin comprises in the non-photosensitive type organic resin material that contains Si-C or contain Si-O structure on main chain one or both combination.
10. a thin-film transistor tft array substrate, comprising: underlay substrate, be formed at TFT, grid line, data wire and pixel electrode on described underlay substrate, wherein,
On region on described tft array substrate except TFT region, the material of the structure except described grid line, data wire and pixel electrode is organic resin.
11. thin-film transistor tft array substrates according to claim 10, is characterized in that, described tft array substrate also comprises: gate insulation layer; Wherein, described gate insulation layer comprises: be formed at the gate insulation layer on described TFT region.
12. thin-film transistor tft array substrates according to claim 10, is characterized in that, described tft array substrate also comprises: the passivation layer between described TFT and described pixel electrode.
13. thin-film transistor tft array substrates according to claim 10, is characterized in that, the layer that described organic resin forms has the upper surface of planarization.
14. thin-film transistor tft array substrates according to claim 10, is characterized in that, the refractive index of described underlay substrate is identical with the refractive index of described organic resin.
15. thin-film transistor tft array substrates according to claim 10, is characterized in that, described organic resin comprises in the non-photosensitive type organic resin material that contains Si-C or contain Si-O structure on main chain one or both combination.
16. thin-film transistor tft array substrates according to claim 10, it is characterized in that, described TFT comprises: gate electrode, be formed at the gate insulation layer on described gate electrode and be formed at active layer, source signal electrode and the leakage signal electrode on described gate insulation layer; Or,
Source signal electrode, leakage signal electrode and active layer, and be formed at the gate insulation layer on described source signal electrode, leakage signal electrode and described active layer, be formed at the gate electrode on described gate insulation layer.
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| CN114023767A (en) * | 2021-10-26 | 2022-02-08 | Tcl华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
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| CN102629077A (en) * | 2011-06-29 | 2012-08-08 | 北京京东方光电科技有限公司 | Preparation methods of resin dielectric layer and its material, liquid crystal panel and display member |
| CN102645803A (en) * | 2011-10-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, liquid crystal panel, display device and manufacturing methods thereof |
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| CN114023767A (en) * | 2021-10-26 | 2022-02-08 | Tcl华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
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Application publication date: 20140625 |