CN103886900A - Content addressable memory and similarity matching method - Google Patents
Content addressable memory and similarity matching method Download PDFInfo
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Abstract
The invention provides a content addressable memory which comprises a CAM (Central Address Memory) array, a matching rate maximizing unit, a matching line read circuit and an address encoder, wherein tail lines of all CAM units in one same row of the CAM array are connected with the matching rate maximizing unit; the matching rate maximizing unit is used for outputting a row of the CAM units, with the minimum tail circuit current, of the CAM array as a first level signal, and used for outputting other rows as a second level signal; the matching line read circuit is used for respectively adjusting the first level signal and the second level signal and subsequently outputting the adjusted first level signal and second level signal; the address encoder is used for outputting a storage address corresponding to the adjusted first level signal as a storage address of a data word with the highest similarity. The invention further provides a corresponding similarity matching method. By adopting the content addressable memory, not only is the maximum matching rate operation of the data word achieved, but also compared with a voltage type maximizing circuit, the content addressable memory is high in comparison speed and small in influence on overall CAM speed.
Description
Technical field
The present invention relates to memory area, more particularly, relate to a kind of Content Addressable Memory and Similarity Match Method.
Background technology
Content Addressable Memory (Content Addressable Memory, CAM) is to visit and the memory device of Update Table according to the position of the content of stored data instead of storage data.Because CAM has at a high speed, walks abreast, easily expands and realize the features such as flexible, can be widely used for network application, high-speed data processing etc. at present.In the time carrying out data search, CAM compares all entities in the search data word of reception and CAM, exists single coupling, multiple coupling still not to mate to determine between the entity in search data word and CAM.Each memory location in the row of CAM is connected with matched line, the instruction of this matched line between stored data word and search word relatively coupling or matching result not, and can be processed by priority encoder all matched lines of instruction matching status, so that the match address of the limit priority providing as the output of CAM to be provided.
Foregoing addressable memory can determine between the entity in search data word and CAM and exist single coupling, multiple coupling still not to mate, and its Output rusults is coupling or do not mate, and this matching mechanisms can be applicable to network service.But in many applications that other need to mate, for example pattern-recognition, artificial intelligence, often need to judge the matching degree or the similarity that in search data word and CAM, between entity, exist, the i.e. degree of match bit array in two comparands, match bit array is more, illustrate that these two comparands are more similar, the accuracy rate of identification is just higher.
At present, in pattern-recognition, artificial intelligence, carrying out matching degree computing all leans on high-speed CPU or DSP to carry out, its mode is by the serial comparison one by one of the template word in the character library of data word to be searched and pattern-recognition, like this whole matching time long, be difficult to carry out real-time matching for large form storehouse.
In addition, on January 8th, 2014, disclosed application number was that Chinese patent application that " 201310349930.3 ", name are called " a kind of Content Addressable Memory system, addressing method and device " has disclosed and a kind ofly asks large circuit to realize the scheme of similarity coupling by voltage-type, but in this scheme, need switching capacity, will greatly increase area; And the speed of switching capacity is slow, limit the comparison speed of overall CAM; In addition, voltage-type asks large circuit first to carry out latch to input voltage, then asks large, and complex time, time delay are long.
Summary of the invention
The technical problem to be solved in the present invention is, cannot realize similarity coupling and the slow problem of matching speed for foregoing addressable memory, and a kind of Content Addressable Memory and Similarity Match Method are provided.
The technical scheme that the present invention solves the problems of the technologies described above is, a kind of Content Addressable Memory is provided, comprise by cam array, the matching degree of the capable CAM cell formation of M and ask big unit, matchline sense circuit and address scrambler, wherein M is more than or equal to 2 integer, and the buttock line that is positioned at all CAM unit of same row in described cam array is connected to matching degree and asks big unit; Described matching degree ask big unit for a line of capable M of cam array CAM unit median caudal filament electric current minimum is output as to the first level signal, other each line outputs are second electrical level signal; Described matchline sense circuit is adjusted respectively rear output for the first level signal and the second electrical level signal of described matching degree being asked to big unit output; Described address scrambler is the memory address output as the highest data word of similarity for the corresponding memory address of signal after described the first level signal is adjusted.
In Content Addressable Memory of the present invention, described matching degree asks big unit to comprise M input subelement, and each input subelement is connected to cam array Yi road buttock line and will after the current subtraction of the buttock line of the constant current source of formed objects and access, exports.
In Content Addressable Memory of the present invention, described input subelement comprises the first equal proportion current mirror, the second equal proportion current mirror, C grade proportional current mirror, constant current source, the first switching tube and second switch pipe, wherein: described the first equal proportion current mirror, the second equal proportion current mirror, C grade proportional current mirror connect successively, and the output terminal of C grade proportional current mirror is the output terminal of this input subelement; The output terminal of described constant current source is connected to the input end of the second equal proportion current mirror via the first switching tube, second switch pipe string is connected between the second equal proportion current mirror, C grade proportional current mirror.
In Content Addressable Memory of the present invention, described matching degree asks big unit to comprise that M is asked large subelement, this M asks large subelement to be connected respectively to the output terminal of an input subelement, and of access electric current maximum asks large subelement output high level, other ask large subelement output low level.
In Content Addressable Memory of the present invention, ask large subelement to comprise M N-channel MOS pipe described in each, and M the metal-oxide-semiconductor array of asking all N-channel MOS pipes in large subelement to form M × M; Same M N-channel MOS pipe asking large subelement is arranged in the output terminal that the same row of described metal-oxide-semiconductor array and the grid of this M N-channel MOS pipe connect respectively corresponding input subelement; Drain electrode with all N-channel MOS pipes of a line in described metal-oxide-semiconductor array is connected; In described metal-oxide-semiconductor array, every a line has respectively and only has the grid of a N-channel MOS pipe to be connected with drain electrode with each row.
In Content Addressable Memory of the present invention, described matching degree asks big unit to comprise M non-linear conversion subelement, and each non-linear conversion subelement for by one corresponding ask the high level of large subelement output to be converted to the first level signal, low transition is second electrical level signal.
In Content Addressable Memory of the present invention, described in each, non-linear conversion subelement comprises the first N-channel MOS pipe, the second N-channel MOS pipe, a P channel MOS tube and the 2nd P channel MOS tube, wherein: the grid of a P channel MOS tube connects the drain electrode of bias voltage, drain electrode connection the first N-channel MOS pipe; The grid of described the first N-channel MOS pipe is connected to correspondence and asks the output terminal of large subelement, drain electrode to be connected respectively to the grid of the second N-channel MOS pipe and the 2nd P channel MOS tube; A described P channel MOS tube is connected and is connected to high level with the source electrode of the 2nd P channel MOS tube; The drain electrode of described the 2nd P channel MOS tube connects the drain electrode of the second N-channel MOS pipe the output terminal as non-linear conversion subelement.
The present invention also comprises a kind of Similarity Match Method, comprises the following steps:
(a) a line of the buttock line electric current minimum of each row CAM unit of the cam array by the capable CAM cell formation of M is output as to the first level signal, other each line outputs are second electrical level signal, described M is more than or equal to 2 integer;
(b) described the first level signal and second electrical level signal are adjusted respectively to rear output;
(c) the corresponding memory address of signal after described the first level signal is adjusted is as the memory address output of the highest data word of similarity.
In Similarity Match Method of the present invention, described step (a) comprising:
(a1) constant current source of formed objects is subtracted each other and obtains M relatively electric current with the M end of line line current of described cam array respectively;
(a2) make described M relatively in electric current maximum Yi road be converted to high level and by other roads relatively current conversion be low level;
(a3) described high level is converted to the first level signal output, is the output of second electrical level signal by described low transition.
Content Addressable Memory of the present invention and Similarity Match Method, not only can realize the maximum matching degree operation of data word, and ask large circuit with respect to voltage-type, and relatively speed is fast, little on the impact of overall CAM speed for it.
Brief description of the drawings
Fig. 1 is the schematic diagram of Content Addressable Memory embodiment of the present invention.
Fig. 2 is the schematic diagram of CAM unit in Fig. 1.
Fig. 3 is the schematic diagram that in Fig. 1, matching degree is asked the specific implementation of big unit.
Fig. 4 is each voltage signal sequential chart of Content Addressable Memory of the present invention.
Fig. 5 is the schematic flow sheet of Similarity Match Method embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As shown in Figure 1, 2, be the schematic diagram of Content Addressable Memory embodiment of the present invention.Content Addressable Memory in the present embodiment comprises by cam array 11, the matching degree of the capable CAM cell formation of M asks big unit 12, matchline sense circuit 13 and address scrambler 14, and wherein M is more than or equal to 2 integer.
In above-mentioned cam array, every a line CAM unit comprises that N CAM unit and each CAM unit comprise a storing sub-units 111 and a comparison subelement 112, and N is more than or equal to 2 integer.CAM unit is stored data word and is searched for the comparison (every a line CAM realizes unit the comparison of a search word) between word and the data word of storage by comparing subelement 112 by storing sub-units 111.Especially, this buttock line of the buttock line IL(IL that is positioned at all CAM unit of same row in above-mentioned cam array 11 picks out from subelement 112 relatively) be connected to matching degree and ask big unit 12.
Matching degree ask big unit 12 for a line of capable M of cam array CAM unit median caudal filament electric current minimum is output as to the first level signal, other each line outputs are second electrical level signal.In the time of specific implementation, above-mentioned the first level signal is that high level signal and second electrical level signal are low level signal, or the first level signal is that low level signal and second electrical level signal are high level signal.
In the time that CAM unit compares, its matched line ML that compares subelement 112 is precharged to high level, when from scounting line SL and/bit that the bit of the search word of SL is stored with storing sub-units 111 is while mating, relatively subelement 112 ends, and is zero thereby make matched line ML keep the electric current in high level and corresponding buttock line IL; When from scounting line SL and/bit of search word of SL is not when the bit of storing sub-units 111 mates, comparison subelement 112 forms discharge channel, thus matched line ML is dragged down and buttock line IL in there is discharge current.Mate lesser with the bit of the data word of storage with searching for word in a line CAM unit, the quantity of the comparison subelement 112 in discharge condition is more, and the electric current in the buttock line IL of this row CAM is larger; On the contrary, mate manyly with searching for word in a line CAM unit with the bit of the data word of storage, the quantity of the comparison subelement 112 in discharge condition is fewer, and the buttock line electric current of this row CAM is less.Like this, matching degree asks large subelement 102 just can select a line CAM unit of buttock line electric current minimum to export the first level signal, the data word of this row CAM unit storage and the similarity maximum of searching for word.
Foregoing addressable memory is by sampling to the buttock line electric current of each row CAM unit, and using buttock line electric current as judging the foundation of data word with search word similarity, not only can realize similarity judgement, and compared to the mode that adopts matched line voltage as basis for estimation, without latch input, have the advantages that sequential is simple, time delay is little.
As shown in Figure 3, matching degree in Fig. 1 is asked big unit 12 specifically can comprise in M input subelement 121(figure and is only illustrated three), and the electric current that each input subelement 121 is connected to the electric current Bing Jiangge road buttock line of cam array Yi road buttock line carries out size reversion, namely comparison electric current minimum being converted to of the electric current maximum of buttock line is exported, comparison electric current maximum being converted to of buttock line electric current minimum is exported.
Particularly, can, by by the constant current source of formed objects Yu Ge road buttock line current subtraction respectively, realize the reversion of size of current.For example, above-mentioned each input subelement 121 can comprise the first equal proportion current mirror (being made up of mirror image pipe Q11, Q12), the second equal proportion current mirror (mirror image pipe Q13, Q14 form), C grade proportional current mirror (mirror image pipe Q17, Q18 form), constant current source, the first switching tube Q16 and second switch pipe Q15, wherein the first equal proportion current mirror, the second equal proportion current mirror, C grade proportional current mirror connect successively, and the output terminal of C grade proportional current mirror is the output terminal of this input subelement 121; The output terminal of constant current source is connected to the input end of the second equal proportion current mirror via the first switching tube Q16, second switch pipe Q15 is serially connected with between the second equal proportion current mirror, C grade proportional current mirror.By controlling the first switching tube Q16 and second switch pipe Q15 can realize the sampling of comparison electric current (inputting the output end current of subelement 121): in the time of the first switching tube Q16 and second switch pipe Q15 conducting, relatively electric currents of input subelement 121 outputs; In the time of the first switching tube Q16 and second switch pipe Q15 disconnection, input subelement 121 output low levels.
Above-mentioned matching degree asks big unit 12 also to comprise that M is asked large subelement 122, this M asks large subelement 122 to be connected respectively to the output terminal of an input subelement 121, and of access electric current maximum asks large subelement 122 to export high level, other ask large subelement 122 output low levels.
Especially, above-mentioned each ask large subelement 122 to comprise M N-channel MOS pipe, and this M asks all N-channel MOS pipes in large subelement 122 to form the metal-oxide-semiconductor array of M × M, and (in this metal-oxide-semiconductor array, the size of all N-channel MOS pipes is all identical, the same same row of asking M N-channel MOS pipe of large subelement 122 to be arranged in this metal-oxide-semiconductor array, and the grid of this M N-channel MOS pipe connects respectively same relatively electric current); In above-mentioned metal-oxide-semiconductor array, be connected with the drain electrode of all N-channel MOS pipes of a line and this metal-oxide-semiconductor array in every a line and each row grid that has respectively and only have a N-channel MOS pipe be connected with draining, for example, in the N-channel MOS pipe of the first row, the grid of first N-channel MOS is connected with drain electrode, in the N-channel MOS pipe of the second row, the grid of second N-channel MOS is connected with drain electrode, the grid of tri-N-channel MOSs of N-channel MOS Guan Zhong of the third line is connected (certainly with drain electrode, in actual applications, said sequence can be adjusted).
Above-mentioned M asks large subelement 122 to form a kind ofly to have high precision, high-speed side direction suppresses interconnection network, in the time of this network work, each input current end (comparing electric current) all can have inhibiting effect each other, this will cause a kind of competition mechanism, it is the input end (because the conducting resistance of each mirror image pipe in input subelement 121 is relatively little) of corresponding maximum current, the electric current of other input end will be attracted to come, thereby respective nodes is suppressed to low level.Certainly, in actual applications, matching degree asks big unit also can adopt the large subelement of asking of other types, to replace the above-mentioned large subelement realization of asking of giving an example similarly to ask large output.
Above-mentioned matching degree asks big unit 12 also to comprise M non-linear conversion subelement 123, and each non-linear conversion subelement 123 is second electrical level signal for the low transition that a corresponding high level of asking large subelement 122 to export is converted to the first level signal or large asking of correspondence subelement 122 is exported.Each non-linear conversion subelement comprises the first N-channel MOS pipe Q41, the second N-channel MOS pipe Q42, a P channel MOS tube Q31 and the 2nd P channel MOS tube Q32, wherein: the grid of a P channel MOS tube Q31 connects the drain electrode of bias voltage, drain electrode connection the first N-channel MOS pipe Q41; The grid of the first N-channel MOS pipe Q41 is connected to correspondence and asks the output terminal of large subelement 122, drain electrode to be connected respectively to the grid of the second N-channel MOS pipe Q42 and the 2nd P channel MOS tube Q32; A described P channel MOS tube is connected and is connected to high level with the source electrode of the 2nd P channel MOS tube; The drain electrode of the 2nd P channel MOS tube Q32 connects the drain electrode of the second N-channel MOS pipe Q42 the output terminal as non-linear conversion subelement 123.
As shown in Figure 4, be that above-mentioned matching degree is asked big unit 12 to carry out similarity to ask large sequential chart.In figure, SL is the level signal of carrying out search operation, SL ,/SL are the level signal of search data input, Vp is the level signal that non-linear conversion subelement 123 arranges bias voltage, and Vct carries out the control signal of asking large operation, and VML is the large result level signal of asking of output.
In the t1 moment, carry out search operation inputted search data, to comparison subelement 112 bit of inputted search words respectively of the each row CAM unit in cam array 11.Scounting line by cam array 11 to SL and/SL inputted search key word, cam array 11 starts M word of self storage and search key to compare, each matched line starts electric discharge, also difference of the different discharge current sizes of matching degree.
In the t2 moment, non-linear conversion subelement 123 arranges bias voltage, and VML exports corresponding level signal.
In the t3 moment after Preset Time, the first switching tube Q16 of control inputs subelement 121 and second switch pipe Q15 closure, carry out and ask large operation.Now, control inputs subelement 121 is to compare electric current by the buttock line current reversal of each input, and asks large operation by asking large subelement 122 to carry out, and makes VML export a road first level signal HeM-1 road second electrical level signal.
Foregoing addressable memory is without switching capacity, thereby can greatly reduce the area of whole device, simultaneously little on the impact of overall CAM speed, and do not need latch input, and sequential is simple, time delay is little.
As shown in Figure 5, the present invention also provides a kind of Similarity Match Method, and it comprises the following steps:
Step S51: after similarity relatively starts, one line output of the buttock line electric current minimum of each row CAM unit of the cam array by the capable CAM cell formation of M is converted to level signal output corresponding to the first level signal, other each row and is converted to second electrical level signal, above-mentioned M is more than or equal to 2 integer.
In this step, can be first the constant current source of formed objects be subtracted each other and obtains M relatively electric current with the M end of line line current of cam array respectively, then making in this M comparison electric current maximum Yi road be converted to high level and current conversion are compared in other roads is low level; Finally above-mentioned high level is converted to the first level signal output, low transition is the output of second electrical level signal.
Step S52: the first level signal and second electrical level signal are adjusted respectively to rear output.
Step S53: the corresponding memory address of signal after the first level signal is adjusted is as the memory address output of the highest data word of similarity.
The above; only for preferably embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (9)
1. a Content Addressable Memory, comprise by cam array, the matching degree of the capable CAM cell formation of M and ask big unit, matchline sense circuit and address scrambler, wherein M is more than or equal to 2 integer, it is characterized in that: the buttock line that is positioned at all CAM unit of same row in described cam array is connected to matching degree and asks big unit; Described matching degree ask big unit for a line of capable M of cam array CAM unit median caudal filament electric current minimum is output as to the first level signal, other each line outputs are second electrical level signal; Described matchline sense circuit is adjusted respectively rear output for the first level signal and the second electrical level signal of described matching degree being asked to big unit output; Described address scrambler is the memory address output as the highest data word of similarity for the corresponding memory address of signal after described the first level signal is adjusted.
2. Content Addressable Memory according to claim 1, it is characterized in that: described matching degree asks big unit to comprise M input subelement, and each input subelement is connected to cam array Yi road buttock line and will after the current subtraction of the buttock line of the constant current source of formed objects and access, exports.
3. Content Addressable Memory according to claim 2, it is characterized in that: described input subelement comprises the first equal proportion current mirror, the second equal proportion current mirror, C grade proportional current mirror, constant current source, the first switching tube and second switch pipe, wherein: described the first equal proportion current mirror, the second equal proportion current mirror, C grade proportional current mirror connect successively, and the output terminal of C grade proportional current mirror is the output terminal of this input subelement; The output terminal of described constant current source is connected to the input end of the second equal proportion current mirror via the first switching tube, second switch pipe string is connected between the second equal proportion current mirror, C grade proportional current mirror.
4. according to the Content Addressable Memory described in claim 2 or 3, it is characterized in that: described matching degree asks big unit to comprise that M is asked large subelement, this M asks large subelement to be connected respectively to the output terminal of an input subelement, and of access electric current maximum asks large subelement output high level, other ask large subelement output low level.
5. Content Addressable Memory according to claim 4, is characterized in that: described in each, ask large subelement to comprise M N-channel MOS pipe, and the individual metal-oxide-semiconductor array of asking all N-channel MOS pipes formation M × M in large subelement of M; Same M N-channel MOS pipe asking large subelement is arranged in the output terminal that the same row of described metal-oxide-semiconductor array and the grid of this M N-channel MOS pipe connect respectively corresponding input subelement; Drain electrode with all N-channel MOS pipes of a line in described metal-oxide-semiconductor array is connected; In described metal-oxide-semiconductor array, every a line has respectively and only has the grid of a N-channel MOS pipe to be connected with drain electrode with each row.
6. Content Addressable Memory according to claim 5, it is characterized in that: described matching degree asks big unit to comprise M non-linear conversion subelement, and each non-linear conversion subelement for by one corresponding ask the high level of large subelement output to be converted to the first level signal, low transition is second electrical level signal.
7. Content Addressable Memory according to claim 6, it is characterized in that: described in each, non-linear conversion subelement comprises the first N-channel MOS pipe, the second N-channel MOS pipe, a P channel MOS tube and the 2nd P channel MOS tube, wherein: the grid of a P channel MOS tube connects the drain electrode of bias voltage, drain electrode connection the first N-channel MOS pipe; The grid of described the first N-channel MOS pipe is connected to correspondence and asks the output terminal of large subelement, drain electrode to be connected respectively to the grid of the second N-channel MOS pipe and the 2nd P channel MOS tube; A described P channel MOS tube is connected and is connected to high level with the source electrode of the 2nd P channel MOS tube; The drain electrode of described the 2nd P channel MOS tube connects the drain electrode of the second N-channel MOS pipe the output terminal as non-linear conversion subelement.
8. a Similarity Match Method, is characterized in that: comprise the following steps:
(a) a line of the buttock line electric current minimum of each row CAM unit of the cam array by the capable CAM cell formation of M is output as to the first level signal, other each line outputs are second electrical level signal, described M is more than or equal to 2 integer;
(b) described the first level signal and second electrical level signal are adjusted respectively to rear output;
(c) the corresponding memory address of signal after described the first level signal is adjusted is as the memory address output of the highest data word of similarity.
9. Similarity Match Method according to claim 8, is characterized in that: described step (a) comprising:
(a1) constant current source of formed objects is subtracted each other and obtains M relatively electric current with the M end of line line current of described cam array respectively;
(a2) make described M relatively in electric current maximum Yi road be converted to high level and by other roads relatively current conversion be low level;
(a3) described high level is converted to the first level signal output, is the output of second electrical level signal by described low transition.
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| CN104200838A (en) * | 2014-08-28 | 2014-12-10 | 平湖凌云信息科技有限公司 | Content addressable memory (CAM) and intelligent similarity matching method |
| CN104598919A (en) * | 2014-12-22 | 2015-05-06 | 宁波力芯科信息科技有限公司 | Fuzzy recognizer and method for similarity intelligent matching |
| CN112259147A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Content addressable memory, array and processor system |
| CN113098487A (en) * | 2021-06-10 | 2021-07-09 | 上海亿存芯半导体有限公司 | IO interface circuit with single input port and multiple slave addresses and communication equipment |
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| US5406508A (en) * | 1992-09-30 | 1995-04-11 | Kawasaki Steel Corporation | Content addressable memory and method of use thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104200838A (en) * | 2014-08-28 | 2014-12-10 | 平湖凌云信息科技有限公司 | Content addressable memory (CAM) and intelligent similarity matching method |
| CN104200838B (en) * | 2014-08-28 | 2016-08-24 | 平湖凌云信息科技有限公司 | content addressable memory and similarity intelligent matching method |
| CN104598919A (en) * | 2014-12-22 | 2015-05-06 | 宁波力芯科信息科技有限公司 | Fuzzy recognizer and method for similarity intelligent matching |
| CN104598919B (en) * | 2014-12-22 | 2017-09-19 | 宁波力芯科信息科技有限公司 | Fuzzy recognizer and method for similarity intelligent Matching |
| CN112259147A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Content addressable memory, array and processor system |
| CN112259147B (en) * | 2020-10-21 | 2021-09-10 | 海光信息技术股份有限公司 | Content addressable memory, array and processor system |
| CN113098487A (en) * | 2021-06-10 | 2021-07-09 | 上海亿存芯半导体有限公司 | IO interface circuit with single input port and multiple slave addresses and communication equipment |
| CN113098487B (en) * | 2021-06-10 | 2021-09-24 | 上海亿存芯半导体有限公司 | IO interface circuit with single input port and multiple slave addresses and communication equipment |
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| CN103886900B (en) | 2016-10-26 |
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