CN103872415B

CN103872415B - Individual layer diaphragm loaded type four laminar substrate micro-band-microstrip interconnection structure

Info

Publication number: CN103872415B
Application number: CN201410119103.XA
Authority: CN
Inventors: 喻梦霞; 吴阳; 徐军
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2014-03-27
Filing date: 2014-03-27
Publication date: 2015-12-09
Anticipated expiration: 2034-03-27
Also published as: CN103872415A

Abstract

A kind of individual layer diaphragm loaded type four laminar substrate micro-band-microstrip interconnection structure, its object is to realize microwave signal in four layers of medium substrate in the low reflection of interlayer and low-loss transmission.It comprises 4 layers of dielectric layer, metal level is provided with between two between dielectric layer, the dielectric layer one of top layer and the dielectric layer four of bottom are provided with microstrip line, microstrip line is connected with the signal via of metal level by vertically running through dielectric layer, described microstrip line both sides are evenly equipped with metal throuth hole row, around signal via, metal throuth hole is set by circular array distribution, it is characterized in that, it is metal aperture anti-pad that signal via runs through metal level place, the metal aperture anti-pad center of circle, all on signal via center line, intermediate metal layer place signal via is provided with matching diaphragm.

Description

Single-layer diaphragm loading type four-layer substrate microstrip-microstrip interconnection structure

Technical Field

The invention relates to a microstrip-microstrip interconnection structure loaded by adopting a single-layer diaphragm, which is suitable for a four-layer substrate microwave circuit.

Background

In multi-layer board circuits, vertical metallized via structures are commonly used to implement the interlayer interconnection of microwave signals in multi-layer board circuits, as well as the interconnection between integrated circuit devices. But the vertical metallized via structure will exhibit discontinuity effects in the microwave and even higher frequency bands, causing strong electromagnetic radiation and coupling. Placing metal vias around the microwave signal hole is a common method to provide a return current to eliminate the resonance between the metal layers of the substrate.

For the prior art, when a multilayer circuit process is realized, the LTCC (low temperature co-fired ceramic) technology is mostly adopted, the interconnection structure based on the LTCC technology is generally complex, the requirement on the process level is high, and the warpage deformation of the multilayer board in the firing process often causes the interconnection structure to change, which affects the performance of the whole circuit. The interconnection structure based on the multilayer composite dielectric substrate is rarely reported at home and abroad, the single-layer diaphragm loading type microstrip-microstrip interconnection structure adopted by the invention is simple and easy to process and has low technological requirement, and the single-layer diaphragm loading type microstrip-microstrip interconnection structure can be finished by etching a circle of circular ring with a specific size at the position of a central metal through hole during circuit etching. The impedance matching is completed by adjusting the radiuses of the metal diaphragm and the anti-welding disc, and the low-insertion-loss and low-reflection transmission of microwave signals is realized.

Disclosure of Invention

The purpose of this patent is to provide a four-layer substrate microstrip-microstrip interconnection structure of single-layer diaphragm loading formula, realizes the low reflection and the low-loss transmission of microwave signal between the layer in four-layer medium base plate.

In order to achieve the purpose, the invention adopts the following technical scheme:

a single-layer diaphragm loading type four-layer substrate microstrip-microstrip interconnection structure comprises 4 dielectric layers, wherein the dielectric layers comprise a dielectric layer I4-1, a dielectric layer II 4-2, a dielectric layer III 4-3, a dielectric layer IV 4-4 and metal layers, and the metal layers comprise an upper metal layer 5-1, a middle metal layer 5-2 and a lower metal layer 5-3;

the dielectric layer I4-1, the upper metal layer 5-1, the dielectric layer II 4-2, the middle metal layer 5-2, the dielectric layer III 4-3, the lower metal layer 5-3 and the dielectric layer IV 4-4 are sequentially arranged from top to bottom;

the microstrip line 6 is arranged on the first dielectric layer 4-1 and the fourth dielectric layer 4-4, the microstrip line 6 is connected through signal through holes 1 which vertically penetrate through the dielectric layers and the metal layers, 3 rows of metal through holes are arranged on two sides of the microstrip line 6, the metal through holes 3 are distributed around the signal through holes 1 according to a circular array, and the microstrip line is characterized in that the metal hole anti-bonding pad 7 is arranged at the position where the signal through hole 1 penetrates through the metal layers, the circle centers of the metal hole anti-bonding pads 7 are all located on the central line of the signal through hole 1, and the matching diaphragm 2 is arranged on the signal through hole.

In the technical scheme, the upper metal layer 5-1 and the lower metal layer 5-3 are symmetrically arranged at the upper end and the lower end of the middle metal layer 5-2, and the dielectric layer I4-1, the dielectric layer II 4-2, the dielectric layer III 4-3 and the dielectric layer IV 4-4 are symmetrically arranged at the upper end and the lower end of the middle metal layer 5-2.

In the above technical solution, the diameter of the metal hole anti-pad 7 of the upper metal layer 5-1 is D _ a1

The capacitance calculation formula yields: c_t1＝A·(B+D)

Wherein,

C_t1d _ a1 is the diameter of the via antipad 7 of the upper metal layer 5-1, Dv represents the diameter of the signal via 1, h1 represents the thickness of dielectric layer one 4-1, h2 represents the thickness of dielectric layer two 4-2, t represents the thickness of the metal layer,_ris a measure of the relative dielectric constant of the material,₀the dielectric constant is vacuum, m is the m-time differential of the length h1 of the signal through hole in the dielectric layer I4-1, and n is the n-time differential of the length h2 of the signal through hole in the dielectric layer II 4-2;

the diameter of the metal hole reverse pad 7 of the middle metal layer 5-2 is D _ a2

The capacitance calculation formula yields:

wherein,

ct2 is the total capacitance of the middle metal layer 5-2, D _ a2 is the diameter of the metal hole reverse pad 7 of the middle metal layer 5-2, D _ m is the diameter of the matching diaphragm 2, Dv is the diameter of the signal via 1, J₀(x) Is a first class 0 order Bessel function, N₀(x) Is a second class 0 order Bessel function;

the diameter of the metal hole reverse pad 7 of the lower metal layer 5-3 is D _ a3, D _ a3 ═ D _ al.

In the above technical scheme, the diameter D _ m of the matching diaphragm

The inductance calculation formula yields:

wherein Lm is the inductance of the metal diaphragm, and t represents the thickness of the metal layer.

Because the invention adopts the technical scheme, the invention has the following beneficial effects:

according to the single-layer diaphragm loading type four-layer substrate microstrip-microstrip interconnection structure, the metal matching diaphragm is added at the position of the signal through hole of the middle metal layer, impedance matching is achieved by adjusting the radius of the matching diaphragm and the radius of the anti-welding pad, and reflection during microwave signal transmission is reduced.

The invention improves the metal through hole structure around the microwave signal hole to provide a return current loop, thereby ensuring the stable transmission of the microwave signal (less signal leakage and electromagnetic shielding); the grounding-like coplanar waveguide structure is adopted as a transmission path of microwave signals, and the microwave signal transmission line has better dispersion characteristic, anti-electromagnetic interference characteristic and higher mechanical strength, so that the microwave signal transmission line can be widely applied to actual engineering.

The design process of the invention is divided into three parts, namely a similar grounding coplanar waveguide transmission area, a similar coaxial transmission area and a single-layer diaphragm loading type microstrip-microstrip interconnection area. The three parts are separately designed, and input and output impedances of the three areas are ensured to be 50 ohms during design so as to complete matching connection of the three areas. In the quasi-grounding coplanar waveguide transmission area, the line width of the microstrip line and the distance between the metal hole columns are designed to ensure that the input and output impedance is 50 ohms; in the quasi-coaxial transmission area, the distance between a metal hole pad and metal holes distributed around the metal hole pad according to a circular array is designed to ensure that the input and output impedance is 50 ohms; in the single-layer diaphragm loading type microstrip-microstrip interconnection area, the diameters of the anti-welding discs of the first metal layer and the third metal layer are designed to ensure that the input impedance and the output impedance are 50 ohms.

Drawings

FIG. 1a is a top view of a ground-like coplanar waveguide;

FIG. 1b is a top view of a coplanar waveguide;

FIG. 2a is a cross-section of a type-ground coplanar waveguide;

FIG. 2b is a cross-section of a grounded coplanar waveguide;

FIGS. 3a and 3b are top views of the quasi-coaxial transmission area, where 3a is the top quasi-coaxial area and 3b is the bottom quasi-coaxial area;

FIGS. 4a, 4b, 4c are schematic views of equivalent coaxial lines in the coaxial-like transmission region, FIG. 4a is a coaxial-like transmission region, FIG. 4b is a cross section of a coaxial line, and FIG. 4c is a coaxial line structure;

FIG. 5 is a schematic cross-sectional view of a four-layer substrate interconnect structure;

FIG. 6 is a top view of a first metal layer and a third metal layer;

FIG. 7 is a top view of a second metal layer (the metal layer where the matching diaphragm is located);

FIG. 8 is a schematic perspective view of a four-layer substrate interconnect structure;

FIG. 9 illustrates an equivalent circuit of a diaphragm-loaded microstrip-microstrip interconnection structure;

FIG. 10 is a schematic diagram of the capacitance differential of the cross section of the metal layer 1;

in the figure, 1-signal through hole, 2-matching membrane, 3-metal through hole, 4-1-dielectric layer I, 4-2-dielectric layer II, 4-3-dielectric layer III, 4-4-dielectric layer IV, 5-1-top metal layer, 5-2-middle metal layer, 5-3-bottom metal layer, 6-microstrip line and 7-metal hole reverse bonding pad.

Detailed Description

The invention is further explained below with reference to the drawings in which:

firstly, a quasi-grounding coplanar waveguide is designed according to a general design method of the grounding coplanar waveguide, as shown in fig. 1a, the quasi-grounding coplanar waveguide is a top view, as shown in fig. 1a, a microstrip line 6 is arranged in the center, the line width is W, two sides of the microstrip line are metal through hole rows, the distance between two rows of metal through holes 3 is Hv2, the structure of the quasi-grounding coplanar waveguide can be equivalently the grounding coplanar waveguide as shown in fig. 1b, W is the line width, and S is the gap between the quasi-grounding coplanar waveguide and the ground plane. FIG. 2 is a cross-sectional view of a quasi-grounded coplanar waveguide and a coplanar waveguide structure, when the grounded coplanar waveguide is utilized as the equivalent grounded coplanar waveguide structure: hv2 ═ W +2S

Using the design formula of the grounded coplanar waveguideWhile neglecting the wall-to-characteristic impedance Z₀The influence of (a) is:

wherein,

when in use

When the temperature of the water is higher than the set temperature,

when in use

<math> <mrow> <mfrac> <mi>W</mi> <mi>h</mi> </mfrac> <mo>&GreaterEqual;</mo> <mn>1</mn> </mrow> </math>

When the temperature of the water is higher than the set temperature,

η＝120π

wherein,

in the formula, W is the line width of the 50 ohm microstrip line, h is the thickness of the dielectric layer,_ris the relative dielectric constant of the dielectric layer,_effmis the equivalent dielectric constant of the dielectric layer, Z_mIs the microstrip line impedance, Z_cK (k) is the coefficient of the closed ellipse integral for coplanar waveguide impedance. At the time of design, let Z₀The microstrip line size W is determined to be 50 Ω, and the distance Hv2 between the ground-like coplanar waveguide metal hole arrays 3 can be obtained.

Then, the top layer and the bottom layer are designed to have the same-axis-like regions, as shown by the dotted line region in fig. 3a, the top layer is designed to have the same-axis-like region, as shown by the dotted line region in fig. 3b, the bottom layer is designed to have the same-axis-like region, and the top layer and the bottom layer are designed to have mirror symmetry structures. In design, the coaxial-like transmission region is equivalent to a coaxial transmission structure, as shown in fig. 4a-4 c. Hvl is the metal via hole distance distributed around the signal via hole according to circular array, which is equivalent to the diameter of the outer conductor of the coaxial line structure; d is the diameter of the central metal hole reverse welding disc, which is equivalent to the diameter of the inner conductor of the coaxial structure; dv is the signal via diameter. For quasi-coaxial structures, the impedance Z_CoaxNamely, the formula:

so that Z is_Cozx＝Z₀I.e. coplanar waveguide impedance with the type of groundSimilarly, determining the diameter D of the reverse bonding pad can obtain the similar coaxial region symmetrical metal hole spacing Hv 1.

And finally, designing a microstrip-microstrip interconnection area loaded on the single-layer diaphragm. Fig. 5 is a schematic cross-sectional view of the 4-layer substrate, and fig. 8 is a schematic perspective view. The 4 layers of substrates are composed of 4 layers of dielectric layers, which include three metal layers, fig. 6 is a top view of a first metal layer and a third metal layer, and fig. 7 is a top view of a second metal layer (a metal layer where the matching film is located). The upper and lower parts are input and output by microstrip lines, the metal matching membrane is designed at the central signal through hole position of the middle metal layer 5-2 and cooperates with the anti-bonding pads on the three metal layers to match impedance.

It can be extracted from fig. 5 that the equivalent circuit is shown in fig. 9, the whole equivalent circuit is a two-port network, and the internal interconnection structure of the four-layer substrate is divided into three T-type network cascades, respectively representing the discontinuity structure of each metal layer at the central signal via 1. Wherein L is_length1、L_length2、L_length3And L_length4Represents the self-inductance of the signal via 1 divided into four parts by the metal layer, C_total1、C_total2And C_total3Representing the total capacitance, Z, of the central signal via 1 to the three metal layers, respectively_in1、Z_in2And Z_in3Representing the impedance, Z ', of the T-network of each stage, seen from Port1 to Port 2'_in3、Z′_in2And Z'_in1Representing the impedance, L, of the T-network per stage, seen from port2 to port1_mRepresenting the inductance introduced by the metal matching diaphragm.

The impedance of each stage of the T-network as seen from port1 to port2 is found by the equivalent circuit as:

the impedance of each stage of the T-network seen from port2 to port1 is:

because this structure is reciprocal symmetrical structure, can obtain:

Z_in1＝Z′_in3①Z_in2＝Z′_in2②Z_in3＝Z′_in1③

the method can be obtained by the formula:

L_{Z i n 1}^{2} = L_{Z i n 3}^{1}

C_t1＝C_t3

the formula is obtained by the following formula:

the formula can be obtained as follows:

the equation of the input impedance is simplified to obtain:

impedance matching is carried out when three T-type networks are cascaded, and then the requirement of + is satisfied

Z_in2＝Z′_in1 ^*

Z_in3＝Z′_in2 ^*

And make Z_in0＝Z_in4＝Z_coax2I.e. impedance matching with the quasi-coaxial transmission area:

in the actual design process, L is determined in consideration of the machining accuracy and the error_Zin1、C_t1And L_mThe value of (c): namely the thicknesses h1 and h2 of the first dielectric layer and the second dielectric layer (the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are arranged from top to bottom); the anti-pad diameter D _ a1 of the upper metal layer and the bottom metal layer; the metal matches the diaphragm diameter D _ m. From Z'_in1Obtaining Z 'by the calculation formula'_in1In the Z course of_in2C can be obtained from the conjugate matching condition_t2The value of (D), i.e., the intermediate metal layer antipad diameter D _ a2, is designed. The specific structure dimensions are calculated from the capacitance and inductance values.

Calculating formula from the capacitance of the metal matching diaphragm:

wherein,

d _ a2 is the diameter of the middle metal layer anti-pad, D _ m is the diameter of the matching diaphragm, Dv is the diameter of the signal via 1, J₀(x) Is a first class 0 order Bessel function, N₀(x) Is a second class of 0 th order Bessel function.

As shown in fig. 10, which is a schematic cross-sectional view of the metal layer 1, when calculating the capacitance of the top metal layer to the signal via, m times of differentiation is performed on a thickness h1 of the dielectric layer to calculate the capacitance of the metal via 3 in the dielectric layer one to the metal layer 1; and (3) carrying out n-time differentiation on the thickness h2 of the dielectric layer II to calculate the capacitance of the metal through hole length between the parallel metal plates to the metal layer I, wherein the calculation formula is as follows:

C_top-plane＝C_bottom-plane＝A·B

wherein,

C_plane-pair＝A·D

wherein,

comprises the following steps: c_t1＝C_t3＝C_top-plane+C_plane-pair

In the above formula, t is the thickness of each metal layer, and h1 and h2 represent the thicknesses of the first dielectric layer and the second dielectric layer, respectively. The capacitor C can be obtained by the above-mentioned formulas_t1、C_t2And C_t3。

In calculating the metal via inductance L_0nFrom the following formula:

wherein n represents the metal via self-inductance divided into 4 parts by each metal layer, L_0nNamely L_lengthn。h_nAnd Dv represents the thickness of each dielectric layer, and is the diameter of the signal through hole 1. Inductance L in calculating metal matching diaphragm_padThe above formula is continuously used, and the following steps are included:

where t represents the metal layer thickness and D _ m represents the metal matching diaphragm diameter. The design of the single-layer diaphragm loading type four-layer substrate microstrip-microstrip interconnection structure can be completed by the formula.

Claims

1. A single-layer diaphragm loading type four-layer substrate microstrip-microstrip interconnection structure comprises 4 dielectric layers, a metal layer and a microstrip substrate, wherein the dielectric layers comprise a first dielectric layer (4-1), a second dielectric layer (4-2), a third dielectric layer (4-3) and a fourth dielectric layer (4-4), and the metal layer comprises an upper metal layer (5-1), a middle metal layer (5-2) and a lower metal layer (5-3);

the dielectric layer I (4-1), the upper metal layer (5-1), the dielectric layer II (4-2), the middle metal layer (5-2), the dielectric layer III (4-3), the lower metal layer (5-3) and the dielectric layer IV (4-4) are sequentially arranged from top to bottom;

microstrip lines (6) are arranged on the first dielectric layer (4-1) and the fourth dielectric layer (4-4), the microstrip lines (6) are connected through signal through holes (1) which vertically penetrate through the dielectric layers and the metal layers, metal through hole (3) rows are arranged on two sides of the microstrip lines (6), and the metal through holes (3) are distributed around the signal through holes (1) according to a circular array, and the microstrip line anti-bonding device is characterized in that metal hole anti-bonding pads (7) are arranged at positions, penetrating through the metal layers, of the signal through holes (1), the circle centers of the metal hole anti-bonding pads (7) are all arranged on the central line of the signal through holes (1), and matching diaphragms (2) are arranged on the signal;

the upper metal layer (5-1) and the lower metal layer (5-3) are symmetrically arranged at the upper end and the lower end of the middle metal layer (5-2), and the dielectric layer I (4-1), the dielectric layer II (4-2), the dielectric layer III (4-3) and the dielectric layer IV (4-4) are symmetrically arranged at the upper end and the lower end of the middle metal layer (5-2);

the diameter of the metal hole anti-pad (7) of the upper metal layer (5-1) is D _ a1

The capacitance calculation formula yields: c_t1＝A·(B+D)

Wherein,

C_t1d _ a1 is the diameter of the metal hole anti-pad (7) of the upper metal layer (5-1), Dv represents the diameter of the signal via (1), h1 represents the thickness of the dielectric layer one (4-1), and h2 represents the total capacitance of the upper metal layer (5-1)The thickness of the dielectric layer two (4-2), t represents the thickness of the metal layer,_ris a measure of the relative dielectric constant of the material,₀the dielectric constant is vacuum, m is the m-time differential of the length h1 of the signal through hole in the dielectric layer I (4-1), and n is the n-time differential of the length h2 of the signal through hole in the dielectric layer II (4-2);

the diameter of the metal hole anti-pad (7) of the middle layer metal layer (5-2) is D _ a2

The capacitance calculation formula yields:

wherein,

ct2 is the total capacitance of the middle metal layer (5-2), D _ a2 is the diameter of the metal via anti-pad (7) of the middle metal layer (5-2), D _ m is the diameter of the matching diaphragm (2), Dv is the diameter of the signal via (1), J₀(x) Is a first class 0 order Bessel function, N₀(x) Is a second class 0 order Bessel function;

the diameter of the metal hole anti-pad (7) of the lower metal layer (5-3) is D _ a3, and D _ a3 is D _ a 1.

2. The single-layer diaphragm-loaded four-layer substrate microstrip-microstrip interconnection structure according to claim 1, wherein matching diaphragm diameter D _ m

The inductance calculation formula yields: