CN103872094A - Semiconductor device and formation method thereof - Google Patents
Semiconductor device and formation method thereof Download PDFInfo
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- CN103872094A CN103872094A CN201210533924.9A CN201210533924A CN103872094A CN 103872094 A CN103872094 A CN 103872094A CN 201210533924 A CN201210533924 A CN 201210533924A CN 103872094 A CN103872094 A CN 103872094A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 54
- 229920005591 polysilicon Polymers 0.000 claims description 53
- 230000003647 oxidation Effects 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 239000013598 vector Substances 0.000 claims description 8
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical group [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910019001 CoSi Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- SEOYNUHKXVGWFU-UHFFFAOYSA-N mu-oxidobis(oxidonitrogen) Chemical compound O=NON=O SEOYNUHKXVGWFU-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor device and a formation method thereof. The semiconductor device comprises a substrate, a semiconductor layer and a material layer. The semiconductor layer is formed on the substrate. The material layer is formed on the semiconductor layer. The semiconductor layer and the material layer are provided with a conical contour along a vertical direction which extends from the substrate. Therefore, formation of an electrical bridge or a short circuit between structures can be effectively inhibited.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of for example, for improving semiconductor device of filling up between structure (oxide is filled up) and forming method thereof.
Background technology
A kind of significant capability of manufacturing reliable integrated circuit is for positively filling up the space between structure.For example, it may must avoid two contacts between structure, not form short circuit.Space between structure may be filled up with a kind of oxide.But if in the oxide of a hole formation between structure, the subsequent processing steps of for example clean and deposition one electric conducting material, may cause not being supposed to be deposited on the electric conducting material between structure, between structure, form short circuit and allow.
As can be seen here, above-mentioned existing semiconductor device and forming method thereof, in product structure, manufacture method and use, obviously still has inconvenience and defect, and is urgently further improved.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is completed by development always, and common product and method do not have appropriate structure and method to address the above problem, this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of new semiconductor device and forming method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to, overcome the defect that existing semiconductor device and forming method thereof exists, be to make it can effectively be suppressed at electric bridge between structure or the formation of short circuit and a kind of new semiconductor device and forming method thereof, technical problem to be solved are provided, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor device proposing according to the present invention comprises a substrate, semi-conductor layer and a material layer.Semiconductor layer is formed on substrate.Material layer is formed on semiconductor layer.Semiconductor layer and material layer have a taper profile along a vertical direction of extending from substrate.One surface and a surface of material layer of semiconductor layer are copline.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor device, wherein this semiconductor layer is a polysilicon layer.
Aforesaid semiconductor device, wherein this material layer is semi-conductor layer.
Aforesaid semiconductor device, wherein this material layer is a metal silicide layer.
Aforesaid semiconductor device, wherein coplanar those surfaces of this semiconductor layer and this material layer form a non-zero angle with a normal line vector of this substrate.
Aforesaid semiconductor device, wherein a tip size of this material layer is less than a bottom size of this semiconductor layer.
Aforesaid semiconductor device, also comprises that a dielectric layer is between this substrate and this semiconductor layer.
Aforesaid semiconductor device, wherein this dielectric layer is one silica layer.
Aforesaid semiconductor device, wherein this dielectric layer is a stack layer.
Aforesaid semiconductor device, wherein this stack layer is monoxide/nitride/oxide (ONO) layer.
Aforesaid semiconductor device, wherein this stack layer is monoxide/nitride/oxide/nitride/oxide (ONONO) layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The formation method of a kind of semiconductor device proposing according to the present invention comprises: a substrate is provided; On substrate, form a polysilicon layer; A part for oxidation polysilicon layer; And remove the oxidized portion of polysilicon layer, for providing a taper profile to polysilicon layer along a vertical direction of extending from substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The formation method of aforesaid semiconductor device, wherein forms this polysilicon layer this step on this substrate and comprises: on this substrate, form one first polysilicon layer; And on this first polysilicon layer, form one second polysilicon layer.
The formation method of aforesaid semiconductor device, wherein a sidewall of this polysilicon layer and a normal line vector of this substrate form a non-zero angle.
The formation method of aforesaid semiconductor device, also comprises and converts an apex zone of this polysilicon layer to a metal silicide layer.
The formation method of aforesaid semiconductor device, wherein one of this remaining polysilicon layer surface is copline with a surface of this metal silicide.
The formation method of aforesaid semiconductor device, wherein coplanar those surfaces of this polysilicon layer and this metal silicide form a non-zero angle with a normal line vector of this substrate.
The formation method of aforesaid semiconductor device, wherein a tip size of this metal silicide is less than a bottom size of this first polysilicon layer.
The formation method of aforesaid semiconductor device, also comprises: on this substrate, form a dielectric layer, wherein this polysilicon layer is formed on this dielectric layer.
The formation method of aforesaid semiconductor device, wherein this dielectric layer is an oxide layer or periodically stack layer of monoxide/nitride.
The formation method of aforesaid semiconductor device, wherein the step of this part of this this polysilicon layer of oxidation is a plasma oxidation.
The formation method of aforesaid semiconductor device, wherein this plasma oxidation is to carry out under a low pressure condition.
The formation method of aforesaid semiconductor device, this oxidized portion that is also included in this polysilicon layer is removed and forms an oxide layer afterwards.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, semiconductor device of the present invention and forming method thereof at least has following advantages and beneficial effect: the present invention can effectively be suppressed at electric bridge between structure or the formation of short circuit.
In sum, the invention relates to a kind of semiconductor device and forming method thereof.This semiconductor device comprises a substrate, semi-conductor layer and a material layer.Semiconductor layer is formed on substrate.Material layer is formed on semiconductor layer.Semiconductor layer and material layer have a taper profile along a vertical direction of extending from substrate.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is a kind of sectional side view of semiconductor device.
Fig. 2 is a kind of sectional side view of semiconductor device.
Fig. 3 is a kind of sectional side view of semiconductor device.
Fig. 4 is a kind of sectional side view of semiconductor device.
Fig. 5 is a kind of sectional side view of semiconductor device.
Fig. 6 is a kind of sectional side view of semiconductor device.
Fig. 7 is a kind of sectional side view of semiconductor device.
Fig. 8 is a kind of sectional side view of semiconductor device.
Fig. 9 is a kind of sectional side view of semiconductor device.
Figure 10 is a kind of sectional side view of semiconductor device.
Figure 11 is a kind of sectional side view of semiconductor device.
Figure 12 A to Figure 12 E is the sectional side view of oxidation profile.
10: semiconductor device 12: dielectric layer
12a, 12b: dielectric layer part 14: silicon substrate
16: the first polysilicon layer 16a, 16b: the first polysilicon layer part
18: the second polysilicon layer 18a, 18b: the second polysilicon layer part
20: rigid mask layer 20a: Part I/rigid mask layer part
20b: Part II/rigid mask layer part 22a: the first structure
22b: the second structure 24: oxide layer
26: hole 28a, 28b, 28c:CoSi (cobalt silicide)
100: semiconductor device 122a, 122b: structure
124a, 124b: oxide 126: oxide layer
128a, 128b:CoSi (cobalt silicide) 130: non-zero angle
132: normal line vector
Embodiment
Technological means and effect of taking for reaching predetermined goal of the invention for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to the semiconductor device proposing according to the present invention and forming method thereof its embodiment, structure, method, step, feature and effect thereof, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known and present in the following detailed description coordinating with reference to graphic preferred embodiment.By the explanation of embodiment, should obtain one more deeply and concrete understanding for technological means and effect of reaching predetermined object and taking to the present invention, but appended graphic be only to provide with reference to the use of explanation, be not used for the present invention to be limited.
Referring to shown in Fig. 1, is a kind of sectional side view of semiconductor device.Semiconductor device 10 comprises a dielectric layer 12, and it is formed on a silicon substrate 14.In the present embodiment, dielectric layer 12 is monoxide-nitride-oxide (ONO) layer.One first polysilicon layer 16 is formed on dielectric layer 12, and one second polysilicon layer 18 is formed on the first polysilicon layer 16.One has the rigid mask layer 20 of patterning of a Part I 20a and a Part II 20b, is formed on the second polysilicon layer 18.
Referring to and read shown in Fig. 2, is a kind of sectional side view of semiconductor device.By carrying out an etch process with rigid mask layer 20 as shade, for setting up the first structure 22a and the second structure 22b.Etch process may be an anisotropic dry ecthing.Structure 22a and 22b comprise respectively dielectric layer part 12a and 12b, the first polysilicon layer part 16a and 16b, the second polysilicon layer part 18a and 18b and rigid mask layer part 20a and 20b.
Shown structure 22a and 22b are in fact illustrative, and following discussion is the semiconductor structure that is suitable for any pattern.For example, first and second polysilicon layer 16 and 18 may be made up of single polycrystalline silicon layer, and dielectric layer 12 may be provided as periodically stack layer or an oxide layer of an ONONO.Structure 22a and 22b may arrange in order to comprise the storage of memory device and some objects of character line structure.
Referring to shown in Fig. 3, is a kind of sectional side view of semiconductor device.Remove rigid mask layer 20 from the shown semiconductor device 10 of Fig. 2.
Referring to shown in Fig. 4, is a kind of sectional side view of semiconductor device.For example form an oxide layer 24 by deposition.A hole 26 in oxide layer 24 is to be formed between structure 22a and 22b.The depth-to-width ratio of minification and increase semiconductor device contributes to the formation of hole 26.
Referring to shown in Fig. 5, is a kind of sectional side view of semiconductor device.Carry out a CoSi pre-oxidation clean.Cleaning reduces oxide layer 24.Cleaning also makes hole 26 expose.During cleaning, the exposure of hole 26 also can cause the size of hole 26 to increase.The exposure of hole 26 and/or expansion are exposed silicon substrate 14.
Referring to shown in Fig. 6, is a kind of sectional side view of semiconductor device.Carrying out a Co deposits to form respectively CoSi (cobalt silicide) 28a and 28b on structure 22a and 22b.Hole 26 exposes silicon substrate 14.Therefore,, in the time carrying out Co deposition, CoSi 28c is formed between structure 22a and 22b.CoSi 28c can be used as the electric bridge between structure 22a and 22b, uses and between structure 22a and 22b, causes the short circuit that is not supposed to.For example, be arranged under the situation in a memory device at structure 22a and 22b, may form a character line short circuit.Although the description of a Co deposition, but it will be appreciated by those skilled in the art that in fact this is only illustration, and this discussion is suitable for metal silicide or the conductive deposits of any pattern.
Referring to now shown in Fig. 7, is a kind of sectional side view of semiconductor device.On the semiconductor device 10 of Fig. 3, carry out a plasma oxidation so that semiconductor device 100 to be provided.Semiconductor device 100 comprises silicon substrate 14. Structure 122a and 122b are formed on silicon substrate 14. Structure 122a and 122b comprise respectively dielectric layer part 12a and 12b, the first polysilicon layer part 16a and 16b and the second polysilicon layer part 18a and 18b.Plasma oxidation forms respectively oxide 124a and 124b in structure 122a and 122b.Oxide 124a and 124b have a taper profile.
It will be appreciated by those skilled in the art that and can utilize certain methods to carry out plasma oxidation step.For example, utilize a microwave source, plasma oxidation may be at the temperature of 400-550 ℃, under the pressure of <1 holder (Torr), and with the microwave power of 1kW-5kW, and with (the O of 0.5-30%
2+ H
2)/(total flow) gas flow be performed.About another example, utilize a RF source, plasma oxidation may be at the temperature of 400-550 ℃, under the pressure of <1 holder, with radio frequency (RF) power of 2kW-5kW, and with (the O of 0.5-30%
2+ H
2)/(total flow) gas flow be performed.
Referring to shown in Fig. 8, is a kind of sectional side view of semiconductor device.Remove oxide 124a and 124b, use and leave structure 122a and the 122b with a taper profile.That is a top critical dimension (CD) of structure 122a and 122b is less than a bottom size of structure 122a and 122b.
Referring to shown in Fig. 9, is a kind of sectional side view of semiconductor device.For example form an oxide layer 126 by deposition.With the shown device of Fig. 4 comparatively speaking, reduce significantly or eliminated the risk that forms hole between structure 122a and 122b.The taper profile of structure 122a and 122b provides improvement oxide to fill up performance.
Referring to shown in Figure 10, is a kind of sectional side view of semiconductor device.Carry out a CoSi pre-oxidation clean.Cleaning reduces oxide layer 126.
Referring to shown in Figure 11, is a kind of sectional side view of semiconductor device.Carry out a Co deposition to form CoSi (cobalt silicide) 128a and 128b at structure 122a and 122b respectively.With the device of Fig. 6 comparatively speaking, be suppressed at electric bridge between structure 122a and 122b or the formation of short circuit.For example, structure 122a and 122b are arranged under the situation in a memory device, reduced or eliminated the problem of character line short circuit.
A sidewall of structure 122a comprises first surface of polysilicon layer part 16a and a surface of CoSi 128a, and these two surfaces are copline.About the taper profile of structure 122a, the normal line vector 132 for copline part and silicon substrate 14 of the first polysilicon layer part 16a and CoSi 128a forms a non-zero angle 130.
Referring to shown in Figure 12 A to Figure 12 E, is the sectional side view of oxidation profile.For example, with reference to the illustrated plasma oxidation profile of figure 7, can be controlled based on applied pressure and bias voltage during plasma oxidation step.Figure 12 A has low pressure and does not have a taper of bias voltage to be oxidized profile during being presented at plasma oxidation.Figure 12 B shows an oxidation profile with thicker base section (have low pressure and apply bias voltage during plasma oxidation).Figure 12 C shows the oxidation profile with sharp corners (have high pressure and there is no bias voltage during plasma oxidation).Figure 12 D shows the oxidation profile with level and smooth corner (have high pressure and apply bias voltage during plasma oxidation).Figure 12 E shows a reference thermal oxidation profile.In other words, low pressure and do not have bias voltage plasma oxidation can anisotropically be oxidized polysilicon layer.The head portion of polysilicon layer converts oxide material significantly to, and the base section of polysilicon layer slightly converts oxide material to.Therefore, polysilicon layer can be trimmed to into a taper profile after carrying out low pressure and there is no bias voltage plasma oxidation.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the method for above-mentioned announcement and technology contents to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (23)
1. a semiconductor device, is characterized in that it comprises:
One substrate;
Semi-conductor layer, is formed on this substrate; And
One material layer, is formed on this semiconductor layer, wherein
This semiconductor layer and this material layer have a taper profile along a vertical direction of extending from this substrate, and a surface and a surface of this material layer of this semiconductor layer are copline.
2. semiconductor device according to claim 1, is characterized in that wherein this semiconductor layer is a polysilicon layer.
3. semiconductor device according to claim 1, is characterized in that wherein this material layer is semi-conductor layer.
4. semiconductor device according to claim 1, is characterized in that wherein this material layer is a metal silicide layer.
5. semiconductor device according to claim 1, is characterized in that wherein coplanar those surfaces of this semiconductor layer and this material layer form a non-zero angle with normal line vectors for this substrate.
6. semiconductor device according to claim 1, is characterized in that a tip size of this material layer is wherein less than a bottom size of this semiconductor layer.
7. semiconductor device according to claim 1, characterized by further comprising a dielectric layer between this substrate and this semiconductor layer.
8. semiconductor device according to claim 7, is characterized in that wherein this dielectric layer is one silica layer.
9. semiconductor device according to claim 7, is characterized in that wherein this dielectric layer is a stack layer.
10. semiconductor device according to claim 9, is characterized in that wherein this stack layer is monoxide/nitride/oxide layer.
11. semiconductor devices according to claim 9, is characterized in that wherein this stack layer is monoxide/nitride/oxide/nitride/oxide layer.
The formation method of 12. 1 kinds of semiconductor devices, is characterized in that it comprises the following steps:
One substrate is provided;
On this substrate, form a polysilicon layer;
Be oxidized a part for this polysilicon layer; And
Remove this oxidized portion of this polysilicon layer, to provide a taper profile to this polysilicon layer along a vertical direction of extending from this substrate.
The formation method of 13. semiconductor devices according to claim 12, is characterized in that wherein forming this polysilicon layer this step on this substrate and comprises:
On this substrate, form one first polysilicon layer; And
On this first polysilicon layer, form one second polysilicon layer.
The formation method of 14. semiconductor devices according to claim 12, is characterized in that wherein a sidewall of this polysilicon layer and a normal line vector of this substrate form a non-zero angle.
The formation method of 15. semiconductor devices according to claim 12, characterized by further comprising and convert an apex zone of this polysilicon layer to a metal silicide layer.
The formation method of 16. semiconductor devices according to claim 15, is characterized in that wherein a surface surperficial and this metal silicide of this remaining polysilicon layer is copline.
The formation method of 17. semiconductor devices according to claim 15, is characterized in that wherein coplanar those surfaces of this polysilicon layer and this metal silicide form a non-zero angle with normal line vectors for this substrate.
The formation method of 18. semiconductor devices according to claim 15, is characterized in that a tip size of this metal silicide is wherein less than a bottom size of this first polysilicon layer.
The formation method of 19. semiconductor devices according to claim 12, characterized by further comprising: on this substrate, form a dielectric layer, wherein this polysilicon layer is formed on this dielectric layer.
The formation method of 20. semiconductor devices according to claim 19, is characterized in that wherein this dielectric layer is an oxide layer or periodically stack layer of monoxide/nitride.
The formation method of 21. semiconductor devices according to claim 12, is characterized in that wherein the step of this part of this this polysilicon layer of oxidation is a plasma oxidation.
The formation method of 22. semiconductor devices according to claim 21, is characterized in that wherein this plasma oxidation is to carry out under a low pressure condition.
The formation method of 23. semiconductor devices according to claim 12, characterized by further comprising after this oxidized portion of this polysilicon layer is removed and forms an oxide layer.
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| KR20090070912A (en) * | 2007-12-27 | 2009-07-01 | 주식회사 하이닉스반도체 | Method for fabricating isolation layer in semiconductor device |
| US20110111532A1 (en) * | 2009-11-11 | 2011-05-12 | Samsung Electronics Co., Ltd. | Methods of forming pattern structures and methods of manufacturing semiconductor devices using the same |
| US20110298033A1 (en) * | 2010-06-03 | 2011-12-08 | Junya Matsunami | Semiconductor storage device |
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|---|---|---|---|---|
| EP1714292B1 (en) * | 2004-01-21 | 2008-03-05 | SanDisk Corporation | Non-volatile memory cell using high-k material and inter-gate programming |
| US20060189073A1 (en) * | 2005-02-22 | 2006-08-24 | Intel Corporation | Control gate profile for flash technology |
| CN1897280A (en) * | 2005-07-13 | 2007-01-17 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| KR20090070912A (en) * | 2007-12-27 | 2009-07-01 | 주식회사 하이닉스반도체 | Method for fabricating isolation layer in semiconductor device |
| US20110111532A1 (en) * | 2009-11-11 | 2011-05-12 | Samsung Electronics Co., Ltd. | Methods of forming pattern structures and methods of manufacturing semiconductor devices using the same |
| US20110298033A1 (en) * | 2010-06-03 | 2011-12-08 | Junya Matsunami | Semiconductor storage device |
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Application publication date: 20140618 |