CN103855099B - Substrate structure with component arrangement area and manufacturing technology thereof - Google Patents
Substrate structure with component arrangement area and manufacturing technology thereof Download PDFInfo
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- CN103855099B CN103855099B CN201210508903.1A CN201210508903A CN103855099B CN 103855099 B CN103855099 B CN 103855099B CN 201210508903 A CN201210508903 A CN 201210508903A CN 103855099 B CN103855099 B CN 103855099B
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- dielectric layer
- setting area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a substrate structure with a component arrangement area and a manufacturing technology of the substrate structure. The substrate structure with the component arrangement area comprises a core layer, a first dielectric layer, an analog circuit pattern and a second dielectric layer. The core layer comprises a first surface, a patterned metal layer and the component arrangement area, wherein the patterned metal layer is arranged on the first surface and comprises a plurality of connecting pads, and the connecting pads are arranged in the component arrangement area; the first dielectric layer is arranged on the core layer and comprises a plurality of openings, and the openings are exposed out of the connecting pads; the analog circuit pattern is arranged on the first dielectric layer, and the analog circuit pattern carries out orthographic projection to the periphery of a projection area on the first dielectric layer by surrounding the component arrangement area; the second dielectric layer is arranged on the first dielectric layer, the analog circuit pattern is covered with the second dielectric layer, the second dielectric layer comprises a component arrangement groove, and the component arrangement groove corresponds to the projection area, penetrates through the second dielectric layer, and is communicated with the openings so that the connecting pads can be exposed.
Description
Technical field
The present invention relates to a kind of board structure and its manufacture craft, and more particularly to a kind of base with element setting area
Hardened structure and its manufacture craft.
Background technology
In recent years, making rapid progress with electronic technology, high-tech electronic industry is come out one after another so that more humane,
Electronic product with better function is constantly weeded out the old and bring forth the new, and is designed towards light, thin, short, small trend.In these electronic products
A circuit substrate would generally be configured, this circuit substrate is used to carry single or multiple electronic components, but electronic component is configured at
Loaded area can be caused on circuit substrate to be increased, thus how electronic component is built in circuit substrate, it has also become current
Key technology.
In the prior art, the substrate manufacture technique of embedded element need to be first using laser drill or machine drilling in core
A perforate is formed in layer, then embedded element is configured in perforate.However, embedded element need to be by connection pad and the line of circuit substrate
Road floor electrical connection, thus a patterned anti-soldering layer must be pre-formed at perforate setting in manufacture craft（solder mask
layer）, made to carry out follow-up connection pad.This manufacture craft must be fabricated separately with other manufacture crafts of circuit substrate, carry
The complexity of manufacturing process steps high, and when carrying out perforate making with laser, the control needs of its laser depth are very accurate, with
Avoid drilling welding resisting layer or have the residual of welding resisting layer, the making that above mentioned problem all improves the circuit substrate of embedded element is difficult
Degree.Further, since the thickness of core layer is typically smaller than 100 microns（μm）, it is also a test for anti-welding technology now.
The content of the invention
It is an object of the invention to provide a kind of board structure with element setting area, its manufacture craft it is relatively simple and
Manufacture craft yield is higher.
It is still another object of the present invention to provide a kind of substrate manufacture technique with element setting area, its step is more simple
The list and product yield produced is higher.
Be that up to above-mentioned purpose, the present invention proposes a kind of board structure with element setting area, it include a core layer,
One first dielectric layer, one intend line pattern and one second dielectric layer.Core layer includes a first surface, a patterned metal layer
And an element setting area.Patterned metal layer is arranged on first surface and including multiple connection pads, in element setting area.The
One dielectric layer is arranged in core layer and is open including multiple, and connection pad is exposed respectively.Intend line pattern and be arranged at the first dielectric
On layer, and plan line pattern is around the view field in element setting area orthographic projection to the first dielectric layer.Second is situated between
Electric layer is arranged on the first dielectric layer and covers plan line pattern.Second dielectric layer includes that an element sets groove, correspondence projected area
Domain runs through the second dielectric layer, and open communication to expose connection pad.
The present invention proposes a kind of substrate manufacture technique with element setting area, and it comprises the following steps：First, there is provided one
Core layer.Core layer includes a first surface, a metal level and an element setting area.Metal level is arranged on first surface.Connect
, patterned metal layer is forming a patterned metal layer.Patterned metal layer includes multiple connection pads, positioned at element setting area
It is interior.Then, one first dielectric layer is formed on first surface, the first dielectric layer overlay pattern metal level.Then, one is formed to intend
Line pattern is on the first dielectric layer.Intend a projected area of the line pattern in element setting area orthographic projection to the first dielectric layer
Set around domain.Afterwards, a mould release membrance is set in the view field of the first dielectric layer, line pattern position is intended in mould release membrance covering
In the part in view field.Then, one second dielectric layer is formed on the first dielectric layer.Second dielectric layer cover mould release membrance with
And intend line pattern.Then, one first perforate and multiple second perforates are formed.First perforate is surround around view field simultaneously
Plan line pattern is extended to through the second dielectric layer.Second perforate extends through the second dielectric layer and extends to connection pad.Afterwards,
Make mould release membrance and the first dielectric layer depart from, groove is set to form an element.
In one embodiment of this invention, above-mentioned element sets groove exposure plan line pattern and is located at around view field
Part.
In one embodiment of this invention, the above-mentioned board structure with element setting area also includes an electronic component,
Element is arranged to set in groove, and electronic component is formed with connection pad and electrically connected.
In one embodiment of this invention, the above-mentioned board structure with element setting area also includes multiple bonding wires, point
Electricity Lian Jie not connection pad and electronic component.
In one embodiment of this invention, the above-mentioned board structure with element setting area also includes multiple soldered balls, point
Electricity Lian Jie not connection pad and electronic component.
In one embodiment of this invention, the material of above-mentioned plan line pattern includes copper, palladium, nickel, silver.
In one embodiment of this invention, the above-mentioned perforate of formation first and the method for the second perforate are opened including laser
Hole.
In one embodiment of this invention, the above-mentioned substrate manufacture technique with element setting area also includes setting extremely
A few electronic component is set in groove in element, and electronic component is formed with connection pad and electrically connected.
In one embodiment of this invention, above-mentioned electronic component routing engage or flip-chip bonded by way of and connection pad
Form electrical connection.
It is of the invention to replace existing middle core layer upper in the welding resisting layer in element setting area using dielectric layer based on above-mentioned,
Make the dielectric layer of element setting area inside and outside integrally formed and while formed, thus existing complicated substrate can be simplified
Manufacture craft.Additionally, the present invention will also be used to stop that the plan line pattern that laser runs through is arranged on dielectric layer, rather than it is such as existing
In be set along in core layer with connection pad, thus the problem that laser beam drilling severity control is difficult can be avoided.Therefore, the present invention
Really the manufacture craft of the substrate with element setting area can be simplified, the yield of its product can be more improved.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate appended accompanying drawing
It is described in detail below.
Brief description of the drawings
Figure 1A to Fig. 1 H is a kind of section of substrate manufacture technique with element setting area of one embodiment of the invention
Schematic diagram；
Fig. 2 is a kind of generalized section of board structure with element setting area of another embodiment of the present invention.
Main element symbol description
100、200：Board structure with element setting area
110：Core layer
112：First surface
113：Second surface
114：Metal level
116：Element setting area
118：Patterned metal layer
118a、218a：Connection pad
120：First dielectric layer
122、222：View field
124：Opening
130：Intend line pattern
140：Mould release membrance
150：Second dielectric layer
160：Element sets groove
162：First perforate
164：Second perforate
180、280：Electronic component
190：Bonding wire
290：Soldered ball
Specific embodiment
Figure 1A to Fig. 1 H is according to a kind of substrate manufacture technique with element setting area of one embodiment of the invention
Generalized section.Please also refer to Figure 1A, the substrate manufacture technique with element setting area of the present embodiment comprises the following steps：It is first
First, there is provided core layer 110 as shown in Figure 1A.Core layer 110 sets including a first surface 112, a metal level 114 and an element
Put area 116.Metal level 114 is arranged on first surface 112.Element setting area 116 is a region on the surface of core layer 110, is used
It is used with setting electronic component.It is worth noting that, in the present embodiment, core layer 110 is a two-sided Copper Foil core layer, meaning
That is, relative two surfaces of core layer 110（One second surface 113 of first surface 112 and relative first surface 112）Can respectively have
There is a Copper Foil（Such as the metal level 114 of Figure 1A）, and the making of line layer is carried out simultaneously in relative two surfaces of core layer 110, with
Increase production efficiency.Following Making programme explains the manufacture craft on the first surface 112 for core layer 110, this
Invention is not limited to the structure and its manufacture craft on the second surface 113 of core layer 110.
Then, referring to Figure 1A and Figure 1B, a patterning manufacture craft is carried out to the metal level 114 in Figure 1A, with
Form the patterned metal layer 118 shown in Figure 1B.Patterned metal layer 118 includes multiple connection pad 118a, wherein connection pad 118a
In in element setting area 116.Then, as shown in Figure 1 C, one first dielectric layer 120 is formed on first surface 112, wherein first
The overlay pattern metal level 118 of dielectric layer 120, re-forms a plan line pattern 130 on the first dielectric layer 120 afterwards.Intend line
Road pattern 130 is set around a view field 122 as shown in Figure 1 C, and line pattern 130 and view field are intended in part
Overlapped around 122.Here, view field 122 is on the orthographic projection of element setting area 116 to the first dielectric layer 120 in Figure 1B
Region.
Hold above-mentioned, the reference picture that please continue 1D sets a mould release membrance 140 in the view field 122 of the first dielectric layer 120,
The part that line pattern 130 is located in view field 122 is intended in the covering of mould release membrance 140, that is to say, that line is intended in the covering of mould release membrance 140
The part Chong Die with around view field 122 of road pattern 130.Refer to Fig. 1 E, then, formed one second dielectric layer 150 in
On first dielectric layer 120, wherein the covering mould release membrance 140 of the second dielectric layer 150 and plan line pattern 130.Then repeat afterwards
The line layer manufacture craft of general multilayer wiring board, with the line layer overlie one another in formation multilayer on the second dielectric layer 150
The number of plies of the line layer to required for reaching.
Please continue again with reference to Fig. 1 F, then, form one first perforate 162 and multiple second perforates 164.Specifically,
First perforate 162 extends to plan line pattern 130 around view field 122 and through the second dielectric layer 150.Also
It is to say, the first perforate 162 is profile to intend the part Chong Die with view field 122 of line pattern 130, by the multilayer of board structure
The tunnel of outer surface 170 1 of line layer is through to the second dielectric layer 150, and extends to plan line pattern 130 below.In this reality
Apply in example, the method for forming the first perforate 162 and the second perforate 164 includes laser beam drilling, and intends the material of line pattern 130
Including copper, palladium, nickel, silver.Because laser cannot pass through the materials such as copper, palladium, nickel, silver, therefore, intend line pattern 130 and be used to control
The depth that laser runs through, makes the frame of the first perforate 162 cross view field 122 and down be through to plan line pattern 130 and stops.
Second perforate 164 then extends through the second dielectric layer 150 and extends to connection pad 118a.The material of connection pad 118a is similarly alternatively
The materials such as copper, palladium, nickel, silver, with the depth for controlling laser to run through.
Afterwards, referring to Fig. 1 F and Fig. 1 G, the mould release membrance 140 in Fig. 1 F is made to depart from the first dielectric layer 120, with shape
Element into Fig. 1 G sets groove 160, is set with electronic component.In general, the material of mould release membrance 140 includes epoxy resin
（Epoxy）, polyethylene（Polyethylene, PE）, polypropylene（Polypropylene, PP）Deng the sticking colloid of tool, but simultaneously
It is not limited.Mould release membrance 140 is usually surface has the film of separation property, and it connects under given conditions with specific material
There is slight viscosity without stickiness or only after touch.The present embodiment is to be easy to be taken off with the first dielectric layer 120 using mould release membrance 140
From characteristic, the frame of the first perforate 162 cross view field 122 and down be through to plan line pattern 130 after, by mould release membrance
140 peel off from the first dielectric layer 120, are formed above-mentioned element and are set groove with the line layer removed positioned at mould release membrance more than 140
160.In this way, completing the substrate manufacture technique with element setting area of the present embodiment.
Then, an electronic component 180 can be also arranged at element and set in groove 160 by the present embodiment as shown in fig. 1H, and electricity
Subcomponent 180 is formed with connection pad 118a and electrically connected.In the present embodiment, for example, chip of electronic component 180, and electronic component
180 electrically connect by way of routing is engaged with connection pad 118a formation, will be embedded in substrate in electronic component 180.But this hair
It is bright to be not limited thereto.In other embodiments of the invention, electronic component 180 also can be by way of flip-chip bonded and connection pad
118a forms electrical connection.
According to above-mentioned manufacture craft, you can produce the board structure 100 with element setting area as shown in fig. 1H,
It includes that a core layer 110, one first dielectric layer 120, intend the dielectric layer 150 of line pattern 130 and 1 second.Core layer
110 include a first surface 112, a patterned metal layer 118 and an element setting area 116.Patterned metal layer 118 is arranged at
On first surface 112 and including multiple connection pad 118a, connection pad 118a is located in element setting area 116.First dielectric layer 120 is set
In in core layer 110 and including multiple opening 124, connection pad 118a is exposed respectively.Intend line pattern 130 and be arranged at the first dielectric
On layer 120, intend line pattern 130 and set around a view field 122 as shown in Figure 1 C, and line pattern is intended in part
130 is Chong Die with around view field 122.It is worth noting that, intending line pattern 130 with connection pad 118a not at substrate knot
In the same layer of structure, connection pad 118a is located in core layer 110, and intends first Jie of the line pattern 130 positioned at the top of core layer 110
In electric layer 120.
Hold above-mentioned, the second dielectric layer 150 is arranged on the first dielectric layer 120 and covers plan line pattern 130.Second dielectric
Layer 150 includes that an element sets groove 160, and correspondence view field 122 runs through the second dielectric layer 150, and open communication 124 to expose
Go out connection pad 118a.In the present embodiment, the board structure 100 with element setting area may also include multilayer line layer and be stacked in the
On two dielectric layers 150, the quantity of line layer is depending on the actual demand of product.Element sets groove 160 then by the multilayer wire of substrate
The tunnel of outer surface 170 1 of road floor is through to the second dielectric layer 150 and extends to plan line pattern 130 below, to expose plan
Line pattern 130 is located at the part around view field 122.
In the present embodiment, the board structure 100 with element setting area may also include an electronic component 180 and a plurality of weldering
Line 190, electronic component 180 is arranged at element and sets in groove 160, and is electrically connected with connection pad 118a formation.Bonding wire 190 is connected respectively
Between connection pad 118a and electronic component 180, electronic component 180 is formed with connection pad 118a by bonding wire 190 and electrically connect, with
To be embedded in substrate in electronic component 180.But the present invention is not limited thereto.
Fig. 2 is illustrated according to a kind of section of board structure with element setting area of another embodiment of the present invention
Figure.Fig. 2 is refer to, in the present embodiment, the board structure 200 with element setting area can also the multiple substitution of soldered ball 290 welderings
The incoming call connecting electronic component 280 of line 190 and connection pad 218a.That is, the electronic component 280 being arranged in view field 222
It is, using the mode of flip-chip bonded, to be formed with connection pad 218a by multiple soldered balls 290 and electrically connected.
In sum, the present invention replaces existing middle core layer upper in the welding resisting layer in element setting area using dielectric layer,
Make the dielectric layer of element setting area inside and outside integrally formed and while formed, thus existing complicated base can be simplified
Plate manufacture craft.Additionally, the present invention will also be used to stop that the plan line pattern that laser runs through is arranged on dielectric layer, rather than as now
What is had is set along in core layer with connection pad, thus can avoid the existing line design from causing laser beam drilling severity control to be difficult
Problem.Therefore, the present invention can simplify the manufacture craft of the substrate with element setting area really, can more improve the good of its product
Rate.
Although disclosing the present invention with reference to above example, but it is not limited to the present invention, any affiliated skill
Skilled person in art field, without departing from the spirit and scope of the present invention, can make a little change with retouching, therefore this hair
Bright protection domain should be by being defined that the claim enclosed is defined.
Claims (10)
1. a kind of board structure with element setting area, including：
Core layer, including first surface, patterned metal layer and element setting area, the patterned metal layer are arranged at first table
On face and including multiple connection pads, those connection pads are located in the element setting area；
First dielectric layer, is arranged in the core layer and is open including multiple, and those connection pads are exposed respectively；
Intend line pattern, be arranged on first dielectric layer, and the plan line pattern extremely should around the element setting area orthographic projection
Around a view field on first dielectric layer；And
Second dielectric layer, is arranged on first dielectric layer and covers the plan line pattern, and second dielectric layer sets including element
Put groove, to should view field run through second dielectric layer, and connect those opening to expose those connection pads, the element set
A part of the groove exposure around the plan line pattern of the projected area.
2. there is the board structure of element setting area as claimed in claim 1, wherein element setting groove exposes the plan circuit
Pattern is located at the part around the view field.
3. the board structure with element setting area as claimed in claim 1, also includes：
Electronic component, is arranged at the element and sets in groove, and the electronic component is formed with those connection pads and electrically connected.
4. the board structure with element setting area as claimed in claim 3, also includes：
Multiple bonding wires, are electrically connected those connection pads and the electronic component.
5. the board structure with element setting area as claimed in claim 3, also includes：
Multiple soldered balls, are electrically connected those connection pads and the electronic component.
6. the board structure with element setting area as claimed in claim 1, the wherein material of the plan line pattern include copper,
Palladium, nickel, silver.
7. a kind of substrate manufacture technique with element setting area, including：
One core layer is provided, the core layer include first surface, metal level and element setting area, the metal level be arranged at this first
On surface；
The metal level is patterned to form a patterned metal layer, the patterned metal layer includes multiple connection pads, positioned at the element
In setting area；
One first dielectric layer is formed on the first surface, first dielectric layer covers the patterned metal layer；
Form one and intend line pattern on first dielectric layer, the plan line pattern around the element setting area orthographic projection to this
Set around a view field on one dielectric layer；
One mould release membrance is set in the view field of first dielectric layer, the mould release membrance covers the plan line pattern positioned at the throwing
Part in the domain of shadow zone；
One second dielectric layer is formed on first dielectric layer, second dielectric layer covers the mould release membrance and the plan line map
Case；
Form one first perforate and multiple second perforates, first perforate around the view field and run through this second
Dielectric layer and extend to the plan line pattern, those second perforates extend through second dielectric layer and extend to those connection pads；
And
Make the mould release membrance depart from first dielectric layer, groove is set to form an element.
8. it is as claimed in claim 7 that there is the substrate manufacture technique of element setting area, wherein forming first perforate and being somebody's turn to do
The method of a little second perforates includes laser beam drilling.
9. there is the substrate manufacture technique of element setting area as claimed in claim 7 or 8, also include：
An at least electronic component is set to be set in groove in the element, and the electronic component is formed with those connection pads and electrically connected.
10. there is the substrate manufacture technique of element setting area as claimed in claim 9, the wherein electronic component is connect by routing
Close or the mode of flip-chip bonded is electrically connected with the formation of those connection pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210508903.1A CN103855099B (en) | 2012-12-03 | 2012-12-03 | Substrate structure with component arrangement area and manufacturing technology thereof |
Applications Claiming Priority (1)
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| US20160037645A1 (en) * | 2014-08-01 | 2016-02-04 | Samsung Electro-Mechanics Co., Ltd. | Embedded board and method of manufacturing the same |
| CN111326640B (en) * | 2018-12-13 | 2022-08-09 | 同泰电子科技股份有限公司 | Method for forming window on light-emitting diode carrier plate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6084297A (en) * | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
| CN102548253A (en) * | 2010-12-28 | 2012-07-04 | 富葵精密组件(深圳)有限公司 | Manufacturing method of multilayer circuit board |
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| US7893527B2 (en) * | 2007-07-24 | 2011-02-22 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor plastic package and fabricating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084297A (en) * | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
| CN102548253A (en) * | 2010-12-28 | 2012-07-04 | 富葵精密组件(深圳)有限公司 | Manufacturing method of multilayer circuit board |
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