CN103855050A - Wafer yield monitoring method - Google Patents
Wafer yield monitoring method Download PDFInfo
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- CN103855050A CN103855050A CN201410118221.9A CN201410118221A CN103855050A CN 103855050 A CN103855050 A CN 103855050A CN 201410118221 A CN201410118221 A CN 201410118221A CN 103855050 A CN103855050 A CN 103855050A
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- graphic structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The invention discloses a wafer yield monitoring method which comprises the following steps of checking and searching graphical structures violating a design rule in a wafer layout according to the design rule; classifying the graphical structures violating the design rule into a plurality of types, and selecting at least one type according to the number of the graphical structures violating the design rule in all the types; estimating programming defects possibility caused by the graphical structures of the selected type; designing a corresponding monitoring structure according to the estimated programming defects; testing the yield of a wafer through the monitoring structure. According to the wafer yield monitoring method, the test time can be shortened, and the verification accuracy for checking the design rule can be improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of wafer yield monitoring method.
Background technology
The yield of semiconductor crystal wafer is the key that can product enter volume production, is also the key index that can volume production order increase, and therefore, in manufacture of semiconductor, for guaranteeing quality and the stability of wafer, need to carry out yield test to wafer.And for logicality product, as processor, interface etc., due to the restriction of himself characteristic, in the time going wrong, be difficult to locate fast and confirm invalid position, and also just cannot find fast failure cause, so can cause a large amount of losses.
Logicality product development often can run into and design the inefficacy causing with processing procedure surplus deficiency; and by Design Rule Checking (Design Rule Check; the examination in the not enough region of surplus (not meeting the violation result of design rule) DRC) obtaining is to judge by artificial method; detection time is long and subjectivity is larger, ignores possibly the violation result that does not meet design rule that need to modify.In addition, if for the detection of this inefficacy adopt conventional means as wafer can acceptance test (wafer acceptance test, WAT) be difficult to pinpoint the problems, this is because the measuring object of WAT test is single transistor (as single NMOS or PMOS), rather than the logic gates having combined), so cannot learn whether logicality product designs correctly.
Owing to having become the bottleneck of logicality product Yield lmproved from develop volume production process because designing the inefficacy causing with not enough this problem of processing procedure surplus.For such problem, be necessary to propose a kind of new for monitoring the yield monitoring method of such problem.
Summary of the invention
Main purpose of the present invention aims to provide a kind of yield monitoring method, can judge whether fast to have the situation of violating Design Rule Checking, to reach lifting yield, shortens the construction cycle, enters fast the object of volume production.
For reaching above-mentioned purpose, the invention provides a kind of yield monitoring method, comprise the following steps:
Step S1: search the graphic structure of violating design rule in chip layout by Design Rule Checking;
Step S2: the graphic structure of described violation design rule is divided into multiple classifications and chooses wherein at least one classification according to the quantity of violating the graphic structure of design rule in each described classification;
Step S3: the graphic structure of the described classification of choosing is assessed to the processing procedure defect that it can cause;
Step S4: for the corresponding monitoring of structures of described processing procedure faultiness design of assessment; And
Step S5: chip yield is tested by described monitoring of structures.
Preferably, in step S2, according to the type of described design rule and/or the type of described graphic structure violated, the graphic structure of described violation design rule is divided into multiple classifications.
Preferably, the type of described design rule comprises the Aligning degree of the graphic structure of live width, the different layers of spacing, the graphic structure of graphic structure.
Preferably, the type of described graphic structure include graphic structure, the polysilicon layer in source region graphic structure, contact hole graphic structure detection architecture and be positioned at active area and polysilicon layer between the graphic structure in intermediate layer.
Preferably, described monitoring of structures is arranged on the Cutting Road of wafer.
Preferably, described monitoring of structures comprises test pin and test structure, and described test structure has the graphic structure identical with the graphic structure of the corresponding violation design rule of this monitoring of structures and the graphic structure of periphery thereof.
Preferably, if in step S3 for the graphic structure of the described classification of choosing, it is multiple assessing its processing procedure defect causing, in step S4 for the corresponding monitoring of structures of processing procedure faultiness design described in each.
Preferably, the layout design of described monitoring of structures is square, and its length of side is 20～30um.
Yield monitoring method proposed by the invention, by violating the graphic structure classification of design rule and carry out the design of estimating of processing procedure defect and corresponding monitoring of structures to thering is at least one class graphic structure of the quantity that breaks the rules at most, can increase monitoring means to the graphic structure the most easily having problems targetedly, save the testing time, improve the examination accuracy to Design Rule Checking, can reach fast lifting yield, shorten the construction cycle, enter fast the effect of volume production.
Accompanying drawing explanation
Figure 1 shows that the flow chart of the yield monitoring method of one embodiment of the invention;
Fig. 2～4 are depicted as the schematic diagram that designs monitoring of structures in the yield monitoring method of one embodiment of the invention;
Figure 5 shows that the domain schematic diagram of monitoring of structures in the yield monitoring method of one embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Fig. 1 is the schematic flow sheet of yield monitoring method provided by the invention.As shown in the figure, yield monitoring method comprises the following steps:
Step S1: search the graphic structure of violating design rule in chip layout by Design Rule Checking.
In this step, first provide a chip layout, it includes multiple graphic structures as metal wire, contact hole, active area, polysilicon etc.For these graphic structures, there is the corresponding design rule relevant with position relationship to the size of graphic structure.Design rule relates to many aspects, for example, distance between width, the adjacent pattern structure of graphic structure, the minimum feature of graphic structure, the Aligning degree between the graphic structure of different layers etc.In the present invention, adopt Design Rule Checking (Design rule checking, DRC) to judge whether the domain of graphic structure meets the requirement of design rule, and find out the graphic structure of violating design rule.
Step S2: the graphic structure of violating design rule is divided into multiple classifications and chooses wherein at least one classification according to the quantity of the graphic structure of middle violation design rule of all categories.
Along with the complexity of IC Layout constantly increases, chip layout is after DRC detects, same design rule may check out various the graphic structures of violating this design rule in domain, and the violation result that all design rules checked out more may be doubled and redoubled.Therefore, in this step, the graphic structure of violating design rule is classified, choose at least one classification wherein by the quantity of the graphic structure of different classes of middle violation design rule.Specifically, can classify according to the type of the design rule of violating, the graphic structure of for example violating the first design rule is made as the first kind, and the graphic structure of violating the second design rule is made as Equations of The Second Kind, the like.In all classifications, according to the quantity sequence of the comprised graphic structure breaking the rules, choose several classifications that quantity is maximum (as the graphic structure quantity of the violation design rule comprising is 10 classifications of front 10), the follow-up graphic structure to these 10 classifications is analyzed.In the present invention,, also can classify according to the type of graphic structure itself or in conjunction with design rule type and graphic structure type according to the type of the design rule of violating except above-mentioned.Here the type of said design rule comprises design rule of the Aligning degree of the graphic structure of design rule, the different layers of the live width of design rule, the graphic structure of the spacing of graphic structure etc., and the type of graphic structure can include source region graphic structure, polysilicon graphics structure, contact hole (contact hole plug) graphic structure etc.
Step S3: the graphic structure of the classification of choosing is assessed to the processing procedure defect that it can cause.
In this step, the graphic structure of choosing for each class, its consequence of violating design rule may cause one or more processing procedure defects, and therefore, each processing procedure defect that may cause such other graphic structure is inferred and assesses.
Step S4: for the corresponding monitoring of structures of processing procedure faultiness design of assessment.
In this step, for the corresponding monitoring of structures of each assessed processing procedure faultiness design.Concrete, this monitoring of structures (test key) is for after completing in chip manufacturing, prepares before wafer cutting and encapsulation, chip to be tested.Preferably monitoring of structures is designed on wafer Cutting Road, tested rear cutly, do not take chip internal space.As previously mentioned, each monitoring of structures is that the processing procedure defect that may cause for the graphic structure of the violation design rule of a certain classification is designed, and therefore it should have and violates structure that the graphic structure of design rule is identical with such other and for this structure being drawn to the test pin (Pad) of testing.In addition, in order to allow monitoring of structures can reflect strictly according to the facts the impact of chip internal same structure region on the correlation effect such as load effect, optical approach effect, it also can comprise the graphic structure of the graphic structure periphery of violating design rule, as shown in Figure 5, except the graphic structure breaking the rules, the layout design of monitoring of structures has comprised other graphic structures of periphery equally, thereby this monitoring of structures can keep the characteristic of chip internal same structure completely.For the layout design that makes monitoring of structures meets above-mentioned requirements, it is designed to the square that the length of side is 20～30um, and the monitoring of structures of the present embodiment is the square of length of side 20um.Completing after the layout design of monitoring of structures, carry out the making of mask plate, and carry out the manufacture of monitoring of structures and chip.
Step S5: chip yield is tested by monitoring of structures.
In this step, complete chip manufacturing, before carrying out wafer cutting and encapsulation, utilizing this monitoring of structures to carry out yield test to chip.
The schematic diagram of the yield monitoring method that Fig. 2～4 are the present invention's one specific embodiment, is illustrated below with reference to Fig. 2～4 pair specific embodiments of the invention.
In the present embodiment, first carry out step S1 and step S2, find out and violate the graphic structure of design rule, to its classification and therefrom choose the graphic structure classification with maximum violation design rule quantity, in the present embodiment, carry out the classification of graphic structure in conjunction with the type of design rule and the type of graphic structure, and the classification of the graphic structure of choosing is the graphic structure of " violating polysilicon POLY minimum spacing " this design rule.
Then, carry out step S3, assess the processing procedure defect that this violation result can cause, comprise following several defect: contact hole (contact hole plug) short circuit between polysilicon or open circuit, polysilicon short circuit, polysilicon and contact hole short circuit.
Afterwards, carry out step S4, on the basis of domain that retains original design, design respectively the monitoring of structures for each defect.As shown in Figure 2, for the first defect, the contact hole CT1 and the CT2 that are connected with source region between the polysilicon of the test pin 201 and 202 connection A of the place of breaking the rules of the first monitoring of structures, test pin 203 is connected with the contact hole 103 of other positions, source region.If measure no current between test pin 201/202 and test pin 203, illustrate that inter polysilicon fails good filling, contact hole (contact hole plug) CT1/CT2 that test pin 201/202 is drawn fails be connected with active area and cause and open circuit.There is electric current if measure between test pin 201 and 202, short circuit between two contact hole (contact hole plug) CT1 that illustrate that test pin 201 and 202 draws and CT2.For the second defect, as shown in Figure 3, the test pin 301 of the second monitoring of structures is connected polysilicon POLY1 and the POLY2 of the B of place that breaks the rules with 302.There is electric current if measure between test pin 301 and 302, between the polysilicon POLY1 of the explanation B of the place of breaking the rules and POLY2, be short-circuited.For the third defect, please refer to Fig. 4, the test pin 401 and 402 of the 3rd detection architecture connects contact hole CT1 and the CT2 of the active area between polysilicon POLY1 and the POLY2 of the C of place that breaks the rules, and test pin 403 and 404 is connected respectively to break the rules locates polysilicon POLY1 and the POLY2 of C.Whether whether polysilicon POLY1 and the contact hole CT1/CT2 that can measure the C of the place of breaking the rules by test pin 401/402 and test pin 403 are short-circuited, and can be measured between the polysilicon POLY2 of the C of the place of breaking the rules and contact hole CT1/CT2 and be short-circuited by test pin 401/402 and test pin 404.Therefore,, by above-mentioned 3 monitoring of structures are arranged on the Cutting Road of wafer, can test the graphic structure of " violating polysilicon minimum spacing " this design rule.In addition, if the layer of the graphic structure breaking the rules between active area and polysilicon, so except designing the monitoring of structures that causes short circuit, opens circuit, also will consider to increase the monitoring of structures design of device Vt/Idsat.As shown in Fig. 2～4, except the layout design at the place that breaks the rules, the domain of monitoring of structures relates to the graphic structure that also can comprise the graphic structure periphery of violating design rule, in the time utilizing this monitoring of structures to test, can reflect strictly according to the facts thus the impact of chip internal same structure region on the correlation effect such as load effect, optical approach effect, keep the characteristic of chip internal same structure.
In sum, yield monitoring method provided by the present invention, by violating the graphic structure classification of design rule and carry out the design of estimating of processing procedure defect and corresponding monitoring of structures to thering is at least one class graphic structure of the quantity that breaks the rules at most, can increase monitoring means to the graphic structure the most easily having problems targetedly, save thus the testing time, improve the examination accuracy to Design Rule Checking, can reach fast lifting yield, shorten the construction cycle, enter fast the effect of volume production.
Although the present invention discloses as above with preferred embodiment; so described many embodiment only give an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (8)
1. a chip yield method of testing, comprises the following steps:
Step S1: search the graphic structure of violating design rule in chip layout by Design Rule Checking;
Step S2: the graphic structure of described violation design rule is divided into multiple classifications and chooses wherein at least one classification according to the quantity of violating the graphic structure of design rule in each described classification;
Step S3: the graphic structure of the described classification of choosing is assessed to the processing procedure defect that it can cause;
Step S4: for the corresponding monitoring of structures of described processing procedure faultiness design of assessment; And
Step S5: chip yield is tested by described monitoring of structures.
2. yield monitoring method according to claim 1, is characterized in that, in step S2, according to the type of described design rule and/or the type of described graphic structure violated, the graphic structure of described violation design rule is divided into multiple classifications.
3. yield monitoring method according to claim 2, is characterized in that, the type of described design rule comprises the lithography alignment degree of the graphic structure of live width, the different layers of the spacing of graphic structure, graphic structure.
4. yield monitoring method according to claim 1, it is characterized in that, the type of described graphic structure include the graphic structure in source region, polysilicon layer graphic structure, contact hole graphic structure detection architecture and be positioned at active area and polysilicon layer between the graphic structure in intermediate layer.
5. yield monitoring method according to claim 4, is characterized in that, described monitoring of structures is arranged on the Cutting Road of wafer.
6. yield monitoring method according to claim 1, it is characterized in that, described monitoring of structures comprises test pin and test structure, and described test structure has the graphic structure identical with the graphic structure of the corresponding violation design rule of this monitoring of structures and the graphic structure of periphery thereof.
7. yield monitoring method according to claim 1, it is characterized in that, if, for the graphic structure of the described classification of choosing, it is multiple assessing its processing procedure defect causing in step S3, in step S4 for the corresponding monitoring of structures of processing procedure faultiness design described in each.
8. yield monitoring method according to claim 1, is characterized in that, the layout design of described monitoring of structures is square, and its length of side is 20～30um.
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| CN106531724A (en) * | 2016-11-30 | 2017-03-22 | 上海华力微电子有限公司 | Test structure and test method |
| CN107122552A (en) * | 2017-05-02 | 2017-09-01 | 上海华力微电子有限公司 | A kind of method of the regular inspection result of automatic review of design |
| CN109284513A (en) * | 2017-07-20 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | Detection method and device, computer readable storage medium, the terminal of chip layout |
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| CN109284513A (en) * | 2017-07-20 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | Detection method and device, computer readable storage medium, the terminal of chip layout |
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| CN103855050B (en) | 2016-08-17 |
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