CN103853629A - Data stream memorizing method and field programmable gate array - Google Patents
Data stream memorizing method and field programmable gate array Download PDFInfo
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- CN103853629A CN103853629A CN201210500605.8A CN201210500605A CN103853629A CN 103853629 A CN103853629 A CN 103853629A CN 201210500605 A CN201210500605 A CN 201210500605A CN 103853629 A CN103853629 A CN 103853629A
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Abstract
An embodiment of the invention provides a data stream memorizing method and a field programmable gate array for a nonvolatile programmable logic device. The method includes: receiving a programming command used for indicating programming of a volatile memory from a data interface; conducting programming operation on the volatile memory according to the programming command and configuring a data stream file; receiving a copying command from the data interface, wherein the copying command is used for indicating copying of the data stream file in the volatile memory to a nonvolatile memory; copying the data stream file to the nonvolatile memory according to the copying command. By means of the method, the technical problem in the prior art that a nonvolatile field programmable gate array (FPGA) device with a volatile memory like a static random access memory (SRAM) can only copy the data stream file from an electrically erasable programmable read-only memory (EEPROM) to the SRAM and cannot achieve double-way transmission of the data stream file between the EEPROM and the SRAM is solved.
Description
Technical field
The present invention, about data stream memory technology, particularly about the data stream memory technology of programmable gate array FPGA, is a kind of data stream storage means and field programmable gate array of Nonvolatile programmable logical device concretely.
Background technology
FPGA is that one can be after powering on, then the chip that the control program of needs is inputted.Therefore, FPGA is not fixing circuit, but a kind of chip that can optionally change function, the function of FPGA can change along with the data of input.
FPGA, from the characteristic of store both program data, is generally divided into two kinds of volatibility FPGA and non-volatile FPGA.Volatibility FPGA adopts SRAM storer to deposit programming data stream file conventionally.In the time that device powers on, generally need to be programmed by outer CPU, or automatically by loading programming data stream file in outside nonvolatile memory.And non-volatile FPGA has retained programming data stream file due in self storer, after powering on, can enter as duty.
The realization of non-volatile FPGA mainly contains two kinds of sights: one is with the direct control logic circuit of nonvolatile memory.At present all simple PLD of SPLD(), the complicated PLD of CPLD() and the non-volatile FPGA of part be all this mode of employing.Another kind of non-volatile FPGA is with the direct control logic circuit of SRAM, but on chip, has nonvolatile memory simultaneously.In the time that device powers on, programming data stream file can be loaded into SRAM automatically from nonvolatile memory.
The patent No. is that 6828823 U.S. Patent application relates to the non-volatile FPGA device with SRAM, and the jtag interface of the disclosed FPGA device of this application by FPGA outside or cpu i/f are to SRAM Direct Programming, and programming finishes rear FPGA and can enter as duty.Another kind of mode is by the jtag interface of FPGA outside, EEPROM to be programmed.Finish after FPGA can accept instruction automatically from an EEPROM copying whole data streaming file to SRAM.After copying end, FPGA can enter as duty.The subject matter that this type of FPGA device exists is that the course of work is comparatively complicated, only can realize data streaming file is copied to SRAM from EEPROM, cannot realize the transmitted in both directions of data streaming file between EEPROM and SRAM, therefore need user to need to be grasped the programming operation of the storer to two or more, reduced user's experience.
Summary of the invention
The embodiment of the present invention provides a kind of data stream storage means and field programmable gate array of Nonvolatile programmable logical device, simplify the programmed method of user to the non-volatile FPGA device with volatile memory such as SRAM, by the control circuit module in FPGA, under outside instruction, data streaming file in volatile memory can be copied in nonvolatile memory automatically, thereby complete the programming to non-volatile FPGA.
One of object of the present invention is, the data stream storage means of a kind of Nonvolatile programmable logical device PLD is provided, described Nonvolatile programmable logical device comprises nonvolatile memory and volatile memory, described method comprises: receive programming instruction from data-interface, described programming instruction is used to indicate programmes to volatile memory; According to described programming instruction, volatile memory is carried out to programming operation, configuration data stream file; Receive duplicate instructions from data-interface, described duplicate instructions is used to indicate the data streaming file in volatile memory is copied to described nonvolatile memory; According to described duplicate instructions, data streaming file is copied to described nonvolatile memory.
One of object of the present invention is, the data stream storage means of a kind of Nonvolatile programmable logical device PLD is provided, described Nonvolatile programmable logical device comprises nonvolatile memory and volatile memory, described method comprises: receive programming instruction from data-interface, described programming instruction is used to indicate programmes to volatile memory and nonvolatile memory; According to described programming instruction, described volatile memory is carried out to programming operation, configuration data stream file; According to described programming instruction, described nonvolatile memory is carried out to programming operation, configuration the second data streaming file; Receive duplicate instructions from data-interface, described duplicate instructions is used to indicate data streaming file is copied to described nonvolatile memory from volatile memory, and the second data streaming file is copied to described volatile memory from nonvolatile memory; According to described duplicate instructions, data streaming file is copied to described nonvolatile memory from volatile memory, the second data streaming file is copied to described volatile memory from nonvolatile memory.
One of object of the present invention is, a kind of field programmable gate array is provided, comprise nonvolatile memory, volatile memory, data-interface, data stream transmitting device and TAP controller, described data-interface, be used for receiving programming instruction, described programming instruction is used to indicate TAP controller volatile memory and nonvolatile memory is carried out to programming operation; Described TAP controller, for according to described programming instruction, described volatile memory being carried out to programming operation, configuration data stream file, carries out programming operation according to described programming instruction to described nonvolatile memory, configuration the second data streaming file; Described data-interface, also for receiving duplicate instructions, described duplicate instructions is used to indicate data streaming file is copied to described nonvolatile memory from volatile memory, and the second data streaming file is copied to described volatile memory from nonvolatile memory; Described data stream transmitting device, for data streaming file being copied to described nonvolatile memory from volatile memory according to described duplicate instructions, copies to described volatile memory by the second data streaming file from nonvolatile memory.
Beneficial effect of the present invention is, having solved the non-volatile FPGA device with volatile memory such as SRAM in prior art only can realize data streaming file is copied to SRAM from EEPROM, cannot realize the technical barrier of the transmitted in both directions of data streaming file between EEPROM and SRAM, simplify the programmed method of user to the non-volatile FPGA device with volatile memory such as SRAM, by the control circuit module in FPGA, under outside instruction, data streaming file in volatile memory can be copied in nonvolatile memory automatically, thereby complete the programming to non-volatile FPGA, realize the transmitted in both directions of data streaming file between EEPROM and SRAM, improve user's experience.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The process flow diagram of the embodiment one of the data stream storage means of a kind of Nonvolatile programmable logical device that Fig. 1 provides for the embodiment of the present invention;
The process flow diagram of the embodiment two of the data stream storage means of a kind of Nonvolatile programmable logical device that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is the particular flow sheet of the step S104 in Fig. 1;
The process flow diagram of the data stream storage means of the another kind of Nonvolatile programmable logical device that Fig. 4 provides for the embodiment of the present invention;
Fig. 5 is the particular flow sheet of the embodiment one of the step S105 in Fig. 4;
Fig. 6 is the particular flow sheet of the embodiment two of the step S405 in Fig. 4;
The structural representation of a kind of field programmable gate array that Fig. 7 provides for the embodiment of the present invention;
The programming schematic diagram of a kind of field programmable gate array that Fig. 8 provides for the embodiment of the present invention;
Control circuit and the interface schematic diagram of a kind of field programmable gate array that Fig. 9 provides for the embodiment of the present invention;
Figure 10 is the schematic diagram of the control circuit module of field programmable gate array and a kind of embodiment of interface;
The schematic block circuit diagram of data double-way transmission in a kind of field programmable gate array that Figure 11 provides for the embodiment of the present invention;
The physical circuit figure of data double-way transmission in a kind of field programmable gate array that Figure 12 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The structural representation of a kind of field programmable gate array that Fig. 7 provides for the embodiment of the present invention, as shown in Figure 7, field programmable gate array provided by the invention specifically comprises: nonvolatile memory 100, volatile memory 200, data-interface, data stream transmitting device 400 and TAP controller 500
Wherein, described data-interface, for receiving programming instruction, described programming instruction is used to indicate TAP controller 500 volatile memory 200 and nonvolatile memory 100 is carried out to programming operation.Data-interface, in concrete embodiment, can be cpu i/f 301 and/or jtag interface 302, and volatile memory can be SRAM, and nonvolatile memory can be EEPROM or flash memory.
Described TAP controller 500, for described volatile memory 200 being carried out to programming operation according to described programming instruction, configuration data stream file, carries out programming operation according to described programming instruction to described nonvolatile memory 100, configuration the second data streaming file;
Described data-interface, also for receiving duplicate instructions, described duplicate instructions is used to indicate data streaming file is copied to described nonvolatile memory 100 from volatile memory 200, and the second data streaming file is copied to described volatile memory 200 from nonvolatile memory 100;
Described data stream transmitting device 400, for data streaming file being copied to described nonvolatile memory 100 from volatile memory 200 according to described duplicate instructions, the second data streaming file is copied to described volatile memory 200 from nonvolatile memory 100.
Fig. 7 has shown a kind of structural representation of volatile memory and nonvolatile memory in FPGA, in the figure, nonvolatile memory has two, how soon volatile memory has, in other embodiments of the present invention, the different demands that use according to reality, nonvolatile memory can be arranged to one or more, and its function is mainly stored data.Outside volatile memory decapacitation stored data, directly steering logic, makes FPGA work.In concrete embodiment, volatile memory is such as can be SRAM, and nonvolatile memory is such as can be EEPROM or flash memory.
The programming schematic diagram of a kind of field programmable gate array that Fig. 8 provides for the embodiment of the present invention, Fig. 8 has shown in FPGA how to programme.Programming can be by the programming instruction of jtag interface or cpu i/f transmission, by TAP controller to SRAM or EEPROM or flash memory Direct Programming.Programming finishes rear FPGA and can accept duplicate instructions, and data streaming file copies to SRAM from EEPROM automatically, and data streaming file carries out transmitted in both directions between EEPROM and SRAM, and FPGA can enter duty afterwards.
Control circuit and the interface schematic diagram of a kind of field programmable gate array that Fig. 9 provides for the embodiment of the present invention, once data streaming file has existed in SRAM, according to passing a duplicate instructions of coming from jtag interface or cpu i/f, TAP controller just can write the data streaming file in SRAM in EEPROM/ flash memory automatically.
Figure 10 is the schematic diagram of the control circuit module of field programmable gate array and a kind of embodiment of interface, and in this embodiment, jtag interface is realized by 1149.1, and TAP controller is realized by replication mode, P1532 and cpu model.Once data streaming file has existed in SRAM, according to passing an instruction of coming from 1149.1JTAG interface or cpu i/f, replication mode just can write the data streaming file in SRAM in EEPROM/ flash memory soon automatically.
The schematic block circuit diagram of data double-way transmission in a kind of field programmable gate array that Figure 11 provides for the embodiment of the present invention, as shown in Figure 11, data link 400 in the present invention comprises the first address pointer shift register ASR, the second address pointer shift register and data shift register DSR
When the bidirectional data transfers of EEPROM of the present invention and SRAM, address pointer shift register (Address Shift Register) is selected the address of data in SRAM and EEPROM, guarantee it is same address.Realize data and exchange to the opposing party from a side by the data address pointer shift register (Address Shift Register) that is shifted.
Wherein, when data streaming file copies to nonvolatile memory from volatile memory, the first described address pointer shift register, for receiving described duplicate instructions, selects address corresponding to each data streaming file in volatile memory successively according to described duplicate instructions;
The second described address pointer shift register, for selecting the identical address, address that nonvolatile memory is corresponding with described each data streaming file;
Described data shift register, for copying to described nonvolatile memory by each data streaming file from described volatile memory successively.
In the time that the second data streaming file copies to volatile memory from nonvolatile memory, the second described address pointer shift register, for receiving described duplicate instructions, select successively address corresponding to each the second data streaming file in nonvolatile memory according to described duplicate instructions;
The first described address pointer shift register, for selecting identical address, the volatile memory address corresponding with described each the second data streaming file;
Described data shift register, for copying to described volatile memory by each the second data streaming file from described nonvolatile memory successively.
In Figure 11, SRAM and nonvolatile memory are further defined as the bidimensional matrix of N*M size.Address pointer shift register (Address Shift Register) length is N+1; Be M+1 by data shift register (Data Shift Register) length.What in Figure 11, show is that a row of n bit address according to being copied in the middle of nonvolatile memory from SRAM.Wherein, shown in Figure 12, be the physical circuit schematic diagram as an example of m bit location example.The circuit unit of Figure 12 repeats just to have formed DSR M+1 time, and control signal has determined the function of DSR.
The process flow diagram of the embodiment one of the data stream storage means of a kind of Nonvolatile programmable logical device that Fig. 1 provides for the embodiment of the present invention, described Nonvolatile programmable logical device comprises nonvolatile memory and volatile memory, as shown in Figure 1, the data stream storage means in described field programmable gate array comprises:
S101: receive programming instruction from data-interface, described programming instruction is used to indicate programmes to volatile memory, data-interface is in concrete embodiment, can be cpu i/f 301 and/or jtag interface 302, volatile memory can be SRAM, and nonvolatile memory can be EEPROM or flash memory.
S102: according to described programming instruction, volatile memory is carried out to programming operation, configuration data stream file.The programming schematic diagram of a kind of field programmable gate array that Fig. 8 provides for the embodiment of the present invention, Fig. 8 has shown in FPGA how to programme.Programming can be by the programming instruction of jtag interface or cpu i/f transmission, by TAP controller to SRAM Direct Programming.Programming finishes rear FPGA and can accept duplicate instructions, and data streaming file copies to EEPROM from SRAM automatically, and FPGA can enter duty afterwards.
S103: receive duplicate instructions from data-interface, described duplicate instructions is used to indicate the data streaming file in volatile memory is copied to described nonvolatile memory;
S104: data streaming file is copied to described nonvolatile memory according to described duplicate instructions.
The method has realized data streaming file and has copied to nonvolatile memory from volatile memory.In the specific embodiment of the present invention, the different demands that use according to reality, nonvolatile memory can be arranged to one or more, and its function is mainly stored data.Outside volatile memory decapacitation stored data, directly steering logic, makes FPGA work.In concrete embodiment, volatile memory is such as can be SRAM, and nonvolatile memory is such as can be EEPROM or flash memory.
The process flow diagram of the embodiment two of the data stream storage means of a kind of Nonvolatile programmable logical device that Fig. 2 provides for the embodiment of the present invention, as shown in Figure 2, the method, except above-mentioned steps, also comprises S205: the described described data streaming file of nonvolatile memory storage.
Fig. 3 is the particular flow sheet of the step S104 in Fig. 1, and as shown in Figure 3, step S104 specifically comprises:
S301: address pointer shift register receives described duplicate instructions;
S302: described address pointer shift register is selected address corresponding to each data streaming file in volatile memory successively;
S303: address pointer shift register is selected the address identical address corresponding with described each data streaming file in nonvolatile memory;
S304: data shift register copies to described nonvolatile memory by each data streaming file from described volatile memory successively.
The schematic block circuit diagram of data streaming file transmission in a kind of field programmable gate array that Figure 11 provides for the embodiment of the present invention, as shown in Figure 11, data link 400 in the present invention comprises the first address pointer shift register ASR, the second address pointer shift register and data shift register DSR
When the data transmission of EEPROM of the present invention and SRAM, address pointer shift register (Address Shift Register) is selected the address of data in SRAM and EEPROM, guarantee it is same address.Realize data and exchange to the opposing party from a side by the data address pointer shift register (Address Shift Register) that is shifted.
In Figure 11, SRAM and nonvolatile memory are further defined as the bidimensional matrix of N*M size.Address pointer shift register (Address Shift Register) length is N+1; Be M+1 by data shift register (Data Shift Register) length.What in Figure 11, show is that a row of n bit address according to being copied in the middle of nonvolatile memory from SRAM.Wherein, shown in Figure 12, be the physical circuit schematic diagram as an example of m bit location example.The circuit unit of Figure 12 repeats just to have formed DSR M+1 time, and control signal has determined the function of DSR.
The process flow diagram of the data stream storage means of the another kind of Nonvolatile programmable logical device that Fig. 4 provides for the embodiment of the present invention, as shown in Figure 4, the method specifically comprises:
S401: receive programming instruction from data-interface, described programming instruction is used to indicate programmes to volatile memory and nonvolatile memory; Data-interface, in concrete embodiment, can be cpu i/f 301 and/or jtag interface 302, and volatile memory can be SRAM, and nonvolatile memory can be EEPROM or flash memory.
S402: according to described programming instruction, described volatile memory is carried out to programming operation, configuration data stream file;
S403: according to described programming instruction, described nonvolatile memory is carried out to programming operation, configuration the second data streaming file; The programming schematic diagram of a kind of field programmable gate array that Fig. 8 provides for the embodiment of the present invention, Fig. 8 has shown in FPGA how to programme.Programming can be by the programming instruction of jtag interface or cpu i/f transmission, by TAP controller to SRAM Direct Programming.Programming finishes rear FPGA and can accept duplicate instructions, and data streaming file copies to EEPROM from SRAM automatically, and FPGA can enter duty afterwards.
S404: receive duplicate instructions from data-interface, described duplicate instructions is used to indicate data streaming file is copied to described nonvolatile memory from volatile memory, and the second data streaming file is copied to described volatile memory from nonvolatile memory;
S405: according to described duplicate instructions, data streaming file is copied to described nonvolatile memory from volatile memory, the second data streaming file is copied to described volatile memory from nonvolatile memory.
The method has realized data streaming file and has copied to described nonvolatile memory from volatile memory, the second data streaming file copies to described volatile memory from nonvolatile memory, has realized the transmitted in both directions of data streaming file between volatile memory and nonvolatile memory.In the specific embodiment of the present invention, the different demands that use according to reality, nonvolatile memory can be arranged to one or more, and its function is mainly stored data.Outside volatile memory decapacitation stored data, directly steering logic, makes FPGA work.In concrete embodiment, volatile memory is such as can be SRAM, and nonvolatile memory is such as can be EEPROM or flash memory.
The schematic block circuit diagram of data double-way transmission in a kind of field programmable gate array that Figure 11 provides for the embodiment of the present invention, as shown in Figure 11, data link 400 in the present invention comprises the first address pointer shift register ASR, the second address pointer shift register and data shift register DSR
When the bidirectional data transfers of EEPROM of the present invention and SRAM, address pointer shift register (Address Shift Register) is selected the address of data in SRAM and EEPROM, guarantee it is same address.Realize data and exchange to the opposing party from a side by the data address pointer shift register (Address Shift Register) that is shifted.
Fig. 5 is the particular flow sheet of the embodiment one of the step S405 in Fig. 4, and the data streaming file that this embodiment shows copies to nonvolatile memory from volatile memory, and as shown in Figure 5, step S105 specifically comprises:
S501: address pointer shift register receives described duplicate instructions;
S502: described address pointer shift register is selected address corresponding to each data streaming file in volatile memory successively;
S503: address pointer shift register is selected the address identical address corresponding with described each data streaming file in nonvolatile memory;
S504: data shift register copies to described nonvolatile memory by each data streaming file from described volatile memory successively.
Fig. 6 is the particular flow sheet of the embodiment two of the step S405 in Fig. 4, and this embodiment is that the second data streaming file copies to volatile memory from nonvolatile memory, and as shown in Figure 6, step S405 specifically comprises:
S601: address pointer shift register receives described duplicate instructions;
S602: address pointer shift register is selected address corresponding to each the second data streaming file in nonvolatile memory successively;
S603: address pointer shift register is selected the address identical address corresponding with described each the second data streaming file in volatile memory;
S604: data shift register copies to described volatile memory by each the second data streaming file from described nonvolatile memory successively.
In Figure 11, SRAM and nonvolatile memory are further defined as the bidimensional matrix of N*M size.Address pointer shift register (Address Shift Register) length is N+1; Be M+1 by data shift register (Data Shift Register) length.What in Figure 11, show is that a row of n bit address according to being copied in the middle of nonvolatile memory from SRAM.Wherein, shown in Figure 12, be the physical circuit schematic diagram as an example of m bit location example.The circuit unit of Figure 12 repeats just to have formed DSR M+1 time, and control signal has determined the function of DSR.
Below in conjunction with specific embodiment, describe data stream storage means and the field programmable gate array of a kind of Nonvolatile programmable logical device of the present invention in detail.Make example with 1149.1: first by 1149.1 (JTAG) interface, SRAM is programmed.After programming finishes, send out " a copying " instruction to copying control circuit module.This control circuit also will be programmed starting to EEPROM from SRAM reading out data.Programming connects after number, and control circuit module processed is informed user with a signal, and programming finishes.
In sum, the invention solves the non-volatile FPGA device with volatile memory such as SRAM in prior art only can realize data streaming file is copied to SRAM from EEPROM, cannot realize the technical barrier of the transmitted in both directions of data streaming file between EEPROM and SRAM, simplify the programmed method of user to the non-volatile FPGA device with volatile memory such as SRAM, by the control circuit module in FPGA, under outside instruction, data streaming file in volatile memory can be copied in nonvolatile memory automatically, thereby complete the programming to non-volatile FPGA, realize the transmitted in both directions of data streaming file between EEPROM and SRAM, improve user's experience.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method, can carry out the hardware that instruction is relevant by computer program completes, described program can be stored in general computer read/write memory medium, this program, in the time carrying out, can comprise as the flow process of the embodiment of above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-OnlyMemory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
In the present invention, applied specific embodiment principle of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (12)
1. a data stream storage means of Nonvolatile programmable logical device PLD, is characterized in that, described Nonvolatile programmable logical device comprises nonvolatile memory and volatile memory, and described method comprises:
Receive programming instruction from data-interface, described programming instruction is used to indicate programmes to volatile memory;
According to described programming instruction, volatile memory is carried out to programming operation, configuration data stream file;
Receive duplicate instructions from data-interface, described duplicate instructions is used to indicate the data streaming file in volatile memory is copied to described nonvolatile memory;
According to described duplicate instructions, data streaming file is copied to described nonvolatile memory.
2. data stream storage means according to claim 1, is characterized in that, described data-interface comprises cpu i/f and/or jtag interface.
3. data stream storage means according to claim 1, is characterized in that, described method also comprises:
The described described data streaming file of nonvolatile memory storage.
4. data stream storage means according to claim 3, is characterized in that, according to described duplicate instructions, data streaming file is copied to described nonvolatile memory and specifically comprises:
Address pointer shift register receives described duplicate instructions;
Described address pointer shift register is selected address corresponding to each data streaming file in volatile memory successively;
Address pointer shift register is selected the address identical address corresponding with described each data streaming file in nonvolatile memory;
Data shift register copies to described nonvolatile memory by each data streaming file from described volatile memory successively.
5. a data stream storage means of Nonvolatile programmable logical device PLD, is characterized in that, described Nonvolatile programmable logical device comprises nonvolatile memory and volatile memory, and described method comprises:
Receive programming instruction from data-interface, described programming instruction is used to indicate programmes to volatile memory and nonvolatile memory;
According to described programming instruction, described volatile memory is carried out to programming operation, configuration data stream file;
According to described programming instruction, described nonvolatile memory is carried out to programming operation, configuration the second data streaming file;
Receive duplicate instructions from data-interface, described duplicate instructions is used to indicate data streaming file is copied to described nonvolatile memory from volatile memory, and the second data streaming file is copied to described volatile memory from nonvolatile memory;
According to described duplicate instructions, data streaming file is copied to described nonvolatile memory from volatile memory, the second data streaming file is copied to described volatile memory from nonvolatile memory.
6. data stream storage means according to claim 5, is characterized in that, described data-interface comprises cpu i/f and/or jtag interface.
7. data stream storage means according to claim 5, is characterized in that, according to described duplicate instructions, data streaming file is copied to described nonvolatile memory from volatile memory and comprises:
Address pointer shift register receives described duplicate instructions;
Described address pointer shift register is selected address corresponding to each data streaming file in volatile memory successively;
Address pointer shift register is selected the address identical address corresponding with described each data streaming file in nonvolatile memory;
Data shift register copies to described nonvolatile memory by each data streaming file from described volatile memory successively.
8. data stream storage means according to claim 5, is characterized in that, the second data streaming file is copied to described volatile storage implement body from nonvolatile memory and comprise:
Address pointer shift register is selected address corresponding to each the second data streaming file in nonvolatile memory successively;
Address pointer shift register is selected the address identical address corresponding with described each the second data streaming file in volatile memory;
Data shift register copies to described volatile memory by each the second data streaming file from described nonvolatile memory successively.
9. an on-site programmable gate array FPGA, is characterized in that, described FPGA comprises nonvolatile memory, volatile memory, data-interface, data stream transmitting device and TAP controller,
Described data-interface, for receiving programming instruction, described programming instruction is used to indicate TAP controller volatile memory and nonvolatile memory is carried out to programming operation;
Described TAP controller, for according to described programming instruction, described volatile memory being carried out to programming operation, configuration data stream file, carries out programming operation according to described programming instruction to described nonvolatile memory, configuration the second data streaming file;
Described data-interface, also for receiving duplicate instructions, described duplicate instructions is used to indicate data streaming file is copied to described nonvolatile memory from volatile memory, and the second data streaming file is copied to described volatile memory from nonvolatile memory;
Described data stream transmitting device, for data streaming file being copied to described nonvolatile memory from volatile memory according to described duplicate instructions, copies to described volatile memory by the second data streaming file from nonvolatile memory.
10. on-site programmable gate array FPGA according to claim 9, is characterized in that, described data-interface comprises cpu i/f and/or jtag interface.
11. on-site programmable gate array FPGAs according to claim 9, is characterized in that, described data stream transmitting device comprises the first address pointer shift register, the second address pointer shift register and data shift register,
Wherein, the first described address pointer shift register, for receiving described duplicate instructions, selects address corresponding to each data streaming file in volatile memory successively according to described duplicate instructions;
The second described address pointer shift register, for selecting the identical address, address that nonvolatile memory is corresponding with described each data streaming file;
Described data shift register, for copying to described nonvolatile memory by each data streaming file from described volatile memory successively.
12. on-site programmable gate array FPGAs according to claim 9, is characterized in that, described data stream transmitting device comprises the first address pointer shift register, the second address pointer shift register and data shift register,
The second described address pointer shift register, for receiving described duplicate instructions, selects address corresponding to each the second data streaming file in nonvolatile memory successively according to described duplicate instructions;
The first described address pointer shift register, for selecting identical address, the volatile memory address corresponding with described each the second data streaming file;
Described data shift register, for copying to described volatile memory by each the second data streaming file from described nonvolatile memory successively.
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| CN101256525A (en) * | 2007-01-23 | 2008-09-03 | 三星电子株式会社 | Method and apparatus for storing page data |
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