CN103841210B - It is method of data synchronization that adjustable main is standby - Google Patents
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Abstract
The invention discloses a kind of adjustable main run using timing cycle standby be method of data synchronization, including：Define active and standby system's state parameter set S, t cycle time, asynchronous patient time c and all issue n；It is that this assembly closes S arrays CRC in each cycle to obtain every, and CRC is sent other side system；This be send out data for LCRC receiving datas be RCRC；It is often to preserve that this is and other side is nearest c cycle CRC data；It is that data are compared in LCRC and RCRC to which that each cycle is often, and this is that LCRC any one data are identical with any one data in RCRC, it is believed that active and standby system is synchronous；This is that LCRC any one data are different with any one data in RCRC, it is believed that active and standby is asynchronous；Active and standby system is synchronous each to carry out original computing and process；Active and standby be asynchronous, standby system stops computing and process, waits principal series synchrodata, and this is that synchrodata is transmitted to standby system while completing original computing and process by principal series.The present invention is relatively low to hardware performance and communication bandwidth requirement.
Description
Technical field
The present invention relates to field of industrial automation control, more particularly to a kind of adjustable main of employing timing cycle operation
Standby is method of data synchronization.
Background technology
The existing active and standby system's method of data synchronization of field of industrial automation control mainly has two kinds：
The first：Absolute clock synchronization, the algorithm can realize the synchronization of clock level, but to hardware performance and communication band
Wide requirement is very high；
Second：Each cycle synchronization, the algorithm require that each controlling cycle, principal series will transmit synchronization data to standby system,
To realize the synchronization of active and standby system, this is very high to communicating bandwidth and reliability requirement.
In existing field of industrial automation control such as railway signal control system, high furnace control system etc. to active and standby system
Synchronous require to be in 100ms levels, therefore using absolute clock synchronization or each cycle synchronous by the way of, total cost of implementation can be compared with
Height, and its data syn-chronization effect does not have the change of matter.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of relatively existing active and standby system's method of data synchronization to hardware performance
It is method of data synchronization that the adjustable main run using timing cycle relatively low with communication bandwidth requirement is standby.
For solving above-mentioned technical problem, it is method of data synchronization that the adjustable main that the present invention is run using timing cycle is standby,
Including：
Active and standby system's data syn-chronization referred in active and standby control system, a series of internal states and all on all four shape of parameter
Condition, this Series Internal state and parameter can be confirmed by specific control system.
1）Active and standby system's internal state and parameter are defined as set S, t milliseconds are defined as cycle time, active and standby is asynchronous
Patient time be c cycle, all issues are n, principal series and complete identical computing and process for each cycle is tied up to；
2）Be often to be calculated array CRC that this assembly closes S in each cycle, array CRC be defined as CRC (S,
N), and by the data is activation of array CRC to other side it is；This be send out array CRC data be LCRC, this be receive other side
The data of coefficient sets CRC are RCRC；Wherein, the length of array CRC and algorithm are situated between also dependent on specific hardware and network communication
Matter is flexibly determining；
3）Each system preserve this be and other side be nearest c cycle array CRC data, if certain cycle do not receive
To the data of other side's coefficient sets RCRC, then it is assumed that the data invalid of cycle array RCRC, the number of cycle array RCRC is skipped
According to；
4）Each cycle is often that the data in its array LCRC and array RCRC in being are compared, if this is
Any one data of array LCRC are identical with any one data in array RCRC, it is believed that active and standby system is synchronous；This coefficient sets
In LCRC, in any one data and array RCRC, any one data is different, it is believed that active and standby is asynchronous；
5）If active and standby system is synchronous each to carry out original computing and process to active and standby system；
If active and standby be asynchronous, standby system stops original computing and process, waits the synchrodata of principal series, principal series by this to be
Internal state and parameter sets S transmit to standby system, while principal series completes original computing and process as synchrodata.
6）Judge that active and standby system's synchronization levels, synchronization levels SyncLevel of the double systems of definition are：
SyncLevel=Min（|n1-n2|）where LCRC(S,n1)=RCRC(S,N2)
SyncLevel is an internal state variable defined in this algorithm, represent two be between synchronous time difference, its
Actual numerical value is that minimum period when CRC is identical between two described inside periodicity, that is, the formula are is poor.
SyncLevel numerical value is less closer to 0, illustrates that the synchronization levels of active and standby system are higher, and SyncLevel numerical value is bigger,
Illustrate that the synchronization levels of active and standby system are lower；
SyncLevel is considered as that active and standby system's synchronization levels are high interval less than or equal to 2 more than 0, and SyncLevel is recognized more than 2
For the low interval of active and standby system's synchronization levels.
Wherein, t cycle time is to be less than or equal to 100 milliseconds more than 0.
Wherein, nonsynchronous patient time is 5 cycles that are less than or equal to more than or equal to 1 for c.
Active and standby system's method of data synchronization of the present invention takes parameterized method, by set S, timing cycle t milliseconds,
And the c cycles isoparametric adjustment of synchronous tolerance, its versatility is realized, different applied environments are adapted to,
Can effectively reduce to active and standby system communication bandwidth and reliability requirement, make use of system to active and standby be asynchronous
Patient time, can effectively filter out short time of active and standby system that peripheral environment interference brings asynchronous problem, can ensure that with
The synchronization of active and standby system is realized in step tolerance.
Description of the drawings
The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is the schematic flow sheet of the present invention.
Fig. 2 is array LCRC data of the present invention and array RCRC data comparison schematic diagram.
Specific embodiment
As shown in figure 1, the adjustable main that run using timing cycle of the present invention standby be method of data synchronization, including：
1）Active and standby system's internal state and parameter are defined as set S, t milliseconds are defined as cycle time（0 ＜ t≤100）, main
Standby is that nonsynchronous patient time is c cycle（1≤c≤5）, all issues are n（1≤n≤5）, principal series and standby tie up to each week
Phase all completes identical computing and process；
2）Be often to be calculated array CRC that this assembly closes S in each cycle, array CRC be defined as CRC (S,
N), and by the data is activation of array CRC to other side it is；This be send out array CRC data markers be LCRC, this be receive
The data of other side's coefficient sets CRC are RCRC；Wherein, the length of array CRC and algorithm are logical also dependent on specific hardware and network
Interrogate medium flexibly to determine；
3）Each system preserve this be and other side be nearest c cycle array CRC data；In such as n-th cycle, need
The CRC data in this nearest c cycle for being is preserved, is data LCRC：LCRC (S, n-c+1)～LCRC (S, n), and other side system
The CRC data in c cycle, is array RCRC recently：RCRC (S, n-c+1)～RCRC (S, n).If certain cycle does not receive
The data of other side's coefficient sets RCRC, then it is assumed that the data invalid of cycle array RCRC, skip the data of cycle array RCRC；
4）As shown in Fig. 2 each cycle is often that the data in its array LCRC and array RCRC in being are compared
Compared with if any one data is identical with any one data in array RCRC in this coefficient sets LCRC, then it is assumed that active and standby system is same
Step；In this coefficient sets LCRC, in any one data and array RCRC, any one data is different（Instant array LCRC data
Entirely different with array RCRC data）, it is believed that active and standby is asynchronous；
5）If active and standby system is synchronous each to carry out original computing and process to active and standby system；
If active and standby be asynchronous, standby system stops original computing and process, waits the synchrodata of principal series, principal series by this to be
Internal state and parameter sets S transmit to standby system, while principal series completes original computing and process as synchrodata.
6）Judge that active and standby system's synchronization levels, synchronization levels SyncLevel of the double systems of definition are：
SyncLevel=Min（|n1-n2|）where LCRC(S,n1)=RCRC(S,N2)
SyncLevel numerical value is less closer to 0, illustrates that the synchronization levels of active and standby system are higher, and SyncLevel numerical value is bigger,
Illustrate that the synchronization levels of active and standby system are lower；
SyncLevel is considered as that active and standby system's synchronization levels are high interval less than or equal to 2 more than 0, and SyncLevel is recognized more than 2
For the low interval of active and standby system's synchronization levels.
The present invention has been described in detail above by specific embodiment and embodiment, but these not constitute right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (4)
1. it is method of data synchronization that a kind of adjustable main run using timing cycle is standby, it is characterized in that, including：
1) active and standby system's internal state and parameter are defined as set S, are defined as t milliseconds cycle time, active and standby is nonsynchronous appearance
The time is born for c cycle, all issues are n；
2) be often to be calculated array CRC that this assembly closes S in each cycle, CRC be defined as CRC (S, n), and should
The data is activation of array CRC to other side be, this be send out array CRC data be LCRC, this be receive other side's coefficient sets CRC
Data be RCRC；CRC：Cyclic redundancy check (CRC)；
3) each system preserve this be and other side be nearest c cycle array CRC data, if certain cycle do not receive right
The data of square coefficient sets RCRC, then it is assumed that the data invalid of cycle array RCRC, skip the data of cycle array RCRC；
Then, the CRC data in this nearest c cycle for being is LCRC：(S, n), other side is nearest c week to LCRC (S, n-c+1)～LCRC
The CRC data of phase is RCRC：RCRC (S, n-c+1)～RCRC (S, n)；
4) each cycle is often that the data in its array LCRC and array RCRC in being are compared, if this coefficient sets
In LCRC, any one data is identical with any one data in array RCRC, it is believed that active and standby system is synchronous；This coefficient sets LCRC's
Any one data in any one data and array RCRC are different, it is believed that active and standby is asynchronous；
If 5) active and standby system is synchronous each carries out original computing and process to active and standby system；
If active and standby be asynchronous, standby system stops original computing and process, waits the synchrodata of principal series, in this is by principal series
Portion's state and parameter sets S are transmitted to standby system, while principal series completes original computing and process as synchrodata.
2. it is method of data synchronization that adjustable main as claimed in claim 1 is standby, it is characterized in that：Also include step 6)
6) judge that active and standby system's synchronization levels, synchronization levels SyncLevel of the double systems of definition are：
SyncLevel=Min (| n1-n2 |) where LCRC (S, n1)=RCRC (S, n2)
I.e. closer to 0, SyncLevel numerical value is more little to illustrate that the synchronization levels of active and standby system are higher, SyncLevel numerical value is bigger, says
The synchronization levels of bright active and standby system are lower；
LCRC (S, n1) be this be this of the n-th 1 cycles be CRC numerical value；
RCRC (S, n2) represents the other side system CRC numerical value in the n-th 2 cycles.
3. it is method of data synchronization that adjustable main as claimed in claim 1 or 2 is standby, it is characterized in that：Cycle time, t was more than 0
It is less than or equal to 100 milliseconds.
4. it is method of data synchronization that adjustable main as claimed in claim 1 or 2 is standby, it is characterized in that：Nonsynchronous patient time c
It is 5 cycles that are less than or equal to more than or equal to 1.
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| CN104360916B (en) * | 2014-11-20 | 2018-01-09 | 上海富欣智能交通控制有限公司 | Main standby synchronous method based on data syn-chronization |
| CN112445127B (en) * | 2019-08-27 | 2022-03-18 | 北京东土科技股份有限公司 | Redundancy control method of master controller |
| CN110544948A (en) * | 2019-09-11 | 2019-12-06 | 国网湖南省电力有限公司 | Dual-configuration STATCOM control protection system and scheduling monitoring method thereof |
| CN113050498A (en) * | 2021-03-23 | 2021-06-29 | 北京和利时系统工程有限公司 | Data synchronization method for zone controller in CBTC (communication based train control) system |
| CN113132496B (en) * | 2021-06-17 | 2021-09-07 | 北京全路通信信号研究设计院集团有限公司 | Double-system data synchronization method, device and system of RSSP-I protocol |
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| CN101192971A (en) * | 2006-11-23 | 2008-06-04 | 中兴通讯股份有限公司 | Detection method for master/slave data consistency |
| CN101945002A (en) * | 2009-07-03 | 2011-01-12 | 中兴通讯股份有限公司 | Method and equipment for quickly comparing data of main board with data of standby board |
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| JP4542027B2 (en) * | 2005-11-30 | 2010-09-08 | 日本電信電話株式会社 | Time synchronization method, time client, time server, application device, and time synchronization system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192971A (en) * | 2006-11-23 | 2008-06-04 | 中兴通讯股份有限公司 | Detection method for master/slave data consistency |
| CN101945002A (en) * | 2009-07-03 | 2011-01-12 | 中兴通讯股份有限公司 | Method and equipment for quickly comparing data of main board with data of standby board |
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