CN103809958B - Method for improving numerical value comparison efficiency of processor and numerical value comparison processor - Google Patents
Method for improving numerical value comparison efficiency of processor and numerical value comparison processor Download PDFInfo
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- CN103809958B CN103809958B CN201210548321.6A CN201210548321A CN103809958B CN 103809958 B CN103809958 B CN 103809958B CN 201210548321 A CN201210548321 A CN 201210548321A CN 103809958 B CN103809958 B CN 103809958B
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Abstract
The invention relates to a method for improving the numerical value comparison efficiency of a processor and a numerical value comparison processor, wherein the processor mainly comprises a data memory, a comparison unit and an instruction unit; the data memory temporarily stores a plurality of groups of rewritable critical values, the processor reads the critical values of the data memory after receiving the digital values to be detected output by the electronic device, the critical values of the data memory are directly compared with the digital values to be detected, comparison codes are output, and then the instruction unit executes corresponding program functions according to the comparison codes; therefore, the processor does not need to gradually and slowly judge the magnitude relation between the digital value to be detected and the preset critical value in sequence by using a firmware program, and the processing efficiency can be improved.
Description
Technical field
The present invention relates to the technology that a kind of processor detects digital numerical value scope, more particularly to a kind of number for lifting processor
It is worth relative efficiency method and the numerical value comparator processor applied to electronic installation.
Background technology
General processor 10, as shown in figure 4, consisting predominantly of a datarams 11, an arithmetic logical unit 12, one
The command unit 30 of accumulator 121 and one, the wherein command unit include a program internal memory 31, instruction registor 32, an instruction
The program counter 34 of decoder 33 and one, the wherein arithmetic logical unit 12 coordinate the command unit 30 to enter line number with firmware
Value compares.
As shown in figure 5, for processor 10 with firmware carry out numeric ratio compared with flow, the processor 10 is in datarams first
Scale value and a subscript value on one are stored in 11, after the digital numerical value to be detected of outside input is received, is stored in the lump to the number
According to internal memory 11 (S50), when the processor 10, which performs the number range, compares flow, the ALU 30 of 8 bit is certainly
The most-significant byte member AH that datarams 11 first read digital numerical value FD0 to be detected most-significant byte member FD0H and scale value on this is compared
(S51), if more than when (FD0H>AH), then the digital numerical value FD0 to be detected is represented higher than upper scale value, and performs corresponding function journey
Sequence A (S511)；If being not more than, further determine whether to be equal to (FD0H=AH) (S52), if unequal, represent this to be checked
Survey the possibility that digital numerical value FD0 is not greater than scale value；If equal, the least-significant byte member of digital numerical value to be detected is further read
(S53) is compared in FD0L and upper scale value least-significant byte member AL, if more than (FD0L>AL), then it is similarly represented as the digital number to be detected
Value FD0 is higher than upper scale value, and performs corresponding function program A (S511)；If being not more than, the digital numerical value FD0 to be detected is represented
It is not greater than the possibility of scale value.
When the digital numerical value FD0 to be detected is not greater than the possibility of upper scale value, digital numerical value to be detected is then read
Most-significant byte member FD0H compares the most-significant byte member BH (S54) of the subscript value, if (FD0H when being less than<BH), then the numeral to be detected is represented
Numerical value FD0 is less than subscript value, and performs corresponding function program B (S541)；If being not less than, further determine whether equal
(S55)；If unequal, digital numerical value FD0 to be detected is represented between upper and lower scale value, therefore perform corresponding function program C
(S551)；If equal (FD0H=BH), the least-significant byte member FD0L of digital numerical value to be detected and the least-significant byte member BL of subscript value are read
(S56) is compared, if less than (FD0L<BL), then the digital numerical value FD0 to be detected is similarly represented as less than subscript value, and is performed
Corresponding function program B (S541).If the most-significant byte member FD0H of digital numerical value to be detected is not less than the most-significant byte member BL of the subscript value,
Digital numerical value FD0 to be detected is represented between upper and lower scale value, therefore performs corresponding function program C (S551).
The procedure code for corresponding to this flow is further provided below：
Current computing device numeric ratio is to flow, for that need to judge that digital numerical value to be detected falls into upper scale value and subscript
Result between value, if being judged with firmware program merely, at least needs said procedure code to realize, if being applied to
The judgement of more digital numerical value scopes, then required judgement time relative growth, and often processor must occur in judged result
After could perform alignment processing or control program according to result, if therefore elongate the judgement time, processor corresponding position certainly will be also resulted in
Manage or control it is insensitive, and be necessary for processor be used for number range detection efficiency improved.
The content of the invention
For above-mentioned technical disadvantages, present invention is primarily aimed at provide a kind of numerical value relative efficiency side for lifting processor
Method and apply electronic installation carry out numerical value comparator processor.
Above-mentioned purpose to be reached, used technical way is the numeric ratio for making the lifting processor compared with efficiency method bag
Contain：
An outside input is received to the digital numerical value to be detected of processor via a comparing unit；
Numerical values recited comparison is carried out to the numerical value to be detected and multigroup preset critical using the comparing unit, and exports ratio
To code a to command unit；And
Match somebody with somebody the corresponding program function of unification arithmetic logical unit execution according to code is compared by the command unit.
Preferably, above-mentioned multigroup critical value and comparison code are temporarily stored in the datarams of processor, wherein multigroup face
Dividing value is rewritable.
Preferably, wherein the bit number of the comparison code is less than the bit number of digital numerical value to be detected.
Preferably, it is respectively subscript numerical value and subscript numerical value, each critical value position that the comparing unit, which presets two groups of critical values,
First number is identical with the bit number of digital numerical value to be detected, and the comparing unit includes three groups of inputs, to receive side by side respectively
Digital numerical value to be detected and upper and lower mark numerical value, and include two output ends, represent to compare code with two bits.
Preferably, above-mentioned carry out numerical value using the comparing unit to the digital numerical value to be detected and multigroup preset critical
Size compares, and export comparison code to the command unit the step of include：
The high bit for reading the high bit and scale value on this of digital numerical value to be detected from datarams is compared；If being more than
When, then the digital numerical value to be detected is represented higher than upper scale value, and output first compares code, and stores into datarams；
If the high bit of digital numerical value to be detected is not more than the high bit of scale value on this, determine whether the two whether phase
Deng；
If unequal, the possibility that the digital numerical value to be detected is not greater than scale value is represented；
If equal, the first low level member with upper scale value of low level for further reading digital numerical value to be detected is compared；
If the low level member of digital numerical value to be detected is higher than subscript more than the low level member of upper scale value, the digital numerical value to be detected
Value, output first compares code, and stores into datarams；If being not more than, the digital numerical value to be detected is not greater than
The possibility of scale value；
The high bit of the high bit and the subscript value that read digital numerical value to be detected is compared；If be less than, representing should
Digital numerical value to be detected is less than subscript value, produces second and compares code, and stores to datarams；Conversely, then further comparing
Whether the two is equal；
If unequal, represent the digital numerical value to be detected and fall between upper scale value and subscript value, produce the 3rd and compare code；
If equal, the low level member and the low level member of subscript value for further reading digital numerical value to be detected are compared；
If the low level member of digital numerical value to be detected represents the digital numerical value to be detected and is less than less than the low level member of subscript value
Subscript value, produces second and compares code；If being not less than, represent the digital numerical value to be detected fall upper scale value and subscript value it
Between, produce the 3rd and compare code.
Preferably, above-mentioned corresponding according to arithmetic logical unit execution with code is compared from the command unit
The step of function program, includes：
The multibank capability program that correspondence compares code is stored in the program internal memory of processor；
The program counter of code addition processor will be compared, a new address is obtained, to point to and perform in the program
The function program of new address in depositing.
Furthermore, the present invention is applied to be included in electronic installation progress numerical value comparator processor：
One datarams, store multigroup critical value, and receive and temporary outside input to processor a number to be detected
Number of words value；
One comparing unit, connects the datarams to read the digital numerical value to be detected and multigroup critical value, to the number
Word digital numerical value to be detected is compared, and export comparison code after store to the datarams；
One command unit, connects the datarams, reads the comparison code；And
One arithmetic logical unit, connects the command unit, wherein the command unit is according to the comparison generation read
Code coordinates the arithmetic logical unit to perform corresponding function program.
Preferably, multigroup critical value of datarams storage is rewritable.
The invention described above is main to increase a comparing unit being made up of hardware circuit newly inside processor, and the comparing unit is first
Digital numerical value to be detected is read from datarams to be compared with critical value, because comparing unit is hardware circuit, therefore can
Rapidly produce and compare code, make the command unit directly perform corresponding function program according to the comparison code；Therefore, handle
Device need not sequentially and step by step compare the digital numerical value and critical value to be detected with firmware program again, and can lift processor comparison
The treatment effeciency of numerical value.
Brief description of the drawings
Fig. 1 is the functional flow diagram of processor of the present invention.
Fig. 2A is the signal wiring schematic diagram of comparing unit of the present invention.
Fig. 2 B are the logical flow charts of comparing unit of the present invention.
Fig. 3 is the flow chart of the digital numerical value range detection efficiency method of present invention lifting processor：
Fig. 4 is the functional flow diagram of existing processor.
Fig. 5 is the flow chart of the digital numerical value range detection method of existing processor.
Main element symbol description
10th, the datarams of 10a processors 11
The accumulator of 12 arithmetic logical unit 121
The command unit of 20 comparing unit 30
The instruction registor of 31 program internal memory 32
The program counter of 33 instruction decoder 34.
Embodiment
Referring initially to shown in Fig. 1, being the functional flow diagrams of processor 10a mono- of the present invention, it is consisted predominantly of in a data
Deposit 11, one comparing unit 20 and a command unit 30；Wherein：The comparing unit 20 is with data/address bus and the datarams 11 and is somebody's turn to do
Command unit 30 is connected.Above-mentioned datarams 11 can be written into and store multigroup critical value, and wherein multigroup critical value is rewritable,
And in after the digital numerical value to be detected that processor 10a receives outside input, kept in the digital numerical value to be detected.
After processor 10a receives digital numerical value to be detected, it is to be detected that the comparison circuit 20 reads this from datarams 11
Digital numerical value and multigroup critical value, due to the comparison circuit 20 be hardware circuit, therefore the digital numerical value to be detected can with it is multigroup
Critical value quickly carries out size comparison, and then produces and store a comparison code.
Now, command unit 30 reads the comparison code (2 bit) produced by comparison circuit 20 again by data/address bus,
And perform corresponding function program according to the comparison code；Specifically, the command unit 30 coordinates a processor 10a calculation
The accumulator 121 of art ALU 12 and one, the program counter 34 of command unit 30 is directly added the comparison generation of 2 bits
Code, to produce new destination address, makes the program internal memory 31, instruction registor 32 and instruction decoder 33 of command unit point to simultaneously
(JUMP) is jumped to the new destination address of the program internal memory 31, to perform function program A, B or C stored by the new address.
Detailed procedure code is as follows：
Judgement is compared with program (firmware) completely accordingly, with respect to existing processor, except reducing during 25 instructions
Between it is outer, also reduce the storage volume for occupying program internal memory 31.
As shown in Figure 2 A and 2 B, it is assumed that receive digital numerical value (HD0) to be detected and upper scale value FD0GT, subscript value
FD0LT, code is compared as 16 carries to export and store, and comparing unit 20 presets the critical value of array more than two (upper scale value
FD0GT, subscript value DF0LT)；Equal 16 carry), to define three detection ranges, therefore the comparing unit 20 includes 48 altogether
Branch inputs pin, and is three detection ranges of reaction, therefore includes 2 output connecting pins；Wherein compare code temporarily order as 00,
01、10；Wherein the comparing unit 20 realizes following comparison step with hardware circuit：Firmware
Digital numerical value HD0 to be detected most-significant byte member HD0H and scale value FD0GT on this most-significant byte are read from datarams 11
(S21) is compared in first FD0GTH, if (HD0H when being more than>FD0GTH), then the digital numerical value HD0 to be detected is represented higher than subscript
Value FD0GT, and export and compare code 10, and store into the address FD0WC of datarams 11；If being not more than, further sentence
It is disconnected the two whether equal (S22)；If unequal, represent that the digital numerical value HD0 to be detected is not greater than scale value FD0GT can
Energy；If equal (HD0H=FD0GTH), the low by 8 of the least-significant byte member HD0L of digital numerical value to be detected and upper scale value is further read
(S23) is compared in bit FD0GTL, if more than (HD0L>FD0GTL), then the digital numerical value HD0 to be detected is similarly represented as to be higher than
Upper scale value FD0GT, and export and compare code 10, and store into the address FD0WC of datarams 11；If being not more than, represent
The digital numerical value HD0 to be detected is not greater than scale value FD0GT possibility.It is not present
When the digital numerical value HD0 to be detected is not greater than upper scale value FD0GT possibility, then carried out with subscript value FD0LT
Size ratio, that is, the most-significant byte member HD0H for reading digital numerical value to be detected compares the most-significant byte member FD0LTH (S24) of the subscript value, if small
In when (HD0H<FD0LTH), then the digital numerical value HD0 to be detected is represented less than subscript value FD0LT, and is produced and compared code 01,
And store into the position FD0WC of datarams；Conversely, then further compare the two whether equal (S25)；If being not equal to,
Represent the digital numerical value HD0 to be detected to fall between upper scale value and subscript value, and produce and compare code 00；If equal (HD0H=
FD0LTH), then the least-significant byte member HD0L and subscript value that further read digital numerical value to be detected least-significant byte member FD0LTL are compared
To (S26), if less than (HD0L<FD0LTL), then the digital numerical value FD0 to be detected is represented less than subscript value, and is produced and compared generation
Code 01；Fall conversely, then representing the digital numerical value HD0 to be detected between upper scale value and subscript value, and produce and compare code 00.
As shown in figure 3, processor 10a judges outside numerical value to be detected the workflow of its detection range, first by number
Group critical value FD0GT, FD0LT is stored in (S10) 11 in processor 10a datarams, after outside numerical value input to be detected,
The comparing unit 20 receives digital numerical value HD0 (S11) to be detected, and read datarams 11 array critical value FD0GT,
FD0LT, it is big compared with array critical value FD0GT, FD0LT or small with hardware structure comparison digital numerical value HD0 to be detected, and export and store up
Comparison code (S12) is deposited, now just will compare code by command unit 30 adds the current address of program counter 34, produces one
New destination locations, point to and perform the function program of the destination address, if being 00 when comparing code using Fig. 2 B to illustrate
(S13) the function program C (S131) of the current signified program address of the program counter 34, is then performed, if it is 01 to compare code
(S14) the function program B (S141) for the destination address that the current signified program address of the program counter 34 plus 1, is then performed；In addition
If the comparison code is 10 (S15), the function for the destination address that the current signified program point of the program counter 34 plus 2 is performed
Program A (S151)；This three sections of function program A~C are stored in program internal memory 31.
It follows that the present invention lifting processor numeric ratio compared with efficiency method in receive a digital digital numerical value to be detected
Afterwards, the digital numerical value to be detected and multigroup preset critical are compared using a comparing unit, and export comparison code；Order
The command unit of processor performs corresponding function program according to comparison code again.
In summary, the main comparing unit being made up of hardware circuit newly-increased inside processor of the present invention, this compares
Unit can input multigroup critical value, be compared with the digital numerical value to be detected changed and exported with the interface circuit, due to than
Be hardware circuit compared with unit, therefore can rapidly produce comparison code, make the ALU need not again with program progressively according to
Sequence judges the detection range of the digital numerical value to be detected, and direct basis compares the program address corresponding to code, and directly holds
The row function program；Consequently, it is possible to detection range is judged more rapidly with firmware program relative to existing processor, and lifting is handled
The treatment effeciency of device；Furthermore, if above-mentioned processor is used for such as contactor control device, signal detection and needs regular detection external signal
Detection range circuit, for a long time perform after, because the procedure code of processor of the present invention effectively subtracts relative to existing processor
It is few, therefore will be helpful to reduce the consumption power of processor.
The foregoing is only presently preferred embodiments of the present invention, all equivalent changes done according to scope of the invention as claimed with
Modification, should all belong to the covering scope of the claims in the present invention.
Claims (8)
1. a kind of numeric ratio for lifting processor includes compared with efficiency method：
An outside input is received to the digital numerical value to be detected of processor via a comparing unit；
Numerical values recited comparison is carried out to the digital numerical value to be detected and multigroup preset critical using the comparing unit, and exports ratio
To code a to command unit；And
Match somebody with somebody the corresponding function program of unification arithmetic logical unit execution according to code is compared by the command unit.
2. the method as described in claim 1, above-mentioned multigroup critical value and comparison code are temporarily stored in the datarams of processor,
Wherein multigroup critical value is rewritable.
3. the bit number of method as claimed in claim 1 or 2, wherein the comparison code is less than the bit of digital numerical value to be detected
Number.
4. method as claimed in claim 3, it is respectively subscript numerical value and subscript numerical value that the comparing unit, which presets two groups of critical values,
Each critical value bit number is identical with the bit number of digital numerical value to be detected, and the comparing unit includes three groups of inputs, to divide
Do not receive digital numerical value to be detected and upper and lower mark numerical value side by side, and include two output ends, represent to compare code with two bits.
5. method as claimed in claim 4, above-mentioned that the digital numerical value to be detected and multigroup preset are faced using the comparing unit
Dividing value carry out numerical values recited comparison, and export comparison code to the command unit the step of include：
The high bit for reading the high bit and scale value on this of digital numerical value to be detected from datarams is compared；If be more than,
The digital numerical value to be detected is then represented higher than upper scale value, output first compares code, and stores into datarams；
If the high bit of digital numerical value to be detected is not more than the high bit of scale value on this, determine whether whether the two is equal；
If unequal, the possibility that the digital numerical value to be detected is not greater than scale value is represented；
If equal, the first low level member with upper scale value of low level for further reading digital numerical value to be detected is compared；
If the low level member of digital numerical value to be detected is higher than upper scale value more than the low level member of upper scale value, the digital numerical value to be detected,
Output first compares code, and stores into datarams；If being not more than, the digital numerical value to be detected is not greater than scale value
Possibility；
The high bit of the high bit and the subscript value that read digital numerical value to be detected is compared；If be less than, this is represented to be checked
Survey digital numerical value and be less than subscript value, produce second and compare code, and store to datarams；Conversely, then further comparing the two
It is whether equal；
If unequal, represent the digital numerical value to be detected and fall between upper scale value and subscript value, produce the 3rd and compare code；
If equal, the low level member and the low level member of subscript value for further reading digital numerical value to be detected are compared；
If the low level member of digital numerical value to be detected represents the digital numerical value to be detected less than subscript less than the low level member of subscript value
Value, produces second and compares code；If being not less than, represent the digital numerical value to be detected and fall between upper scale value and subscript value, produce
Raw 3rd compares code.
6. method as claimed in claim 5, above-mentioned to compare the arithmetic logical operation list with code from command unit foundation
The step of member performs corresponding function program includes：
The multibank capability program that correspondence compares code is stored in the program internal memory of processor；
The program counter of code addition processor will be compared, a new address is obtained, to point to and perform in the program internal memory
The function program of new address.
7. a kind of numerical value comparator processor applied to electronic installation, includes：
One datarams, store multigroup critical value, and receive and temporary outside input to processor a digital number to be detected
Value；
One comparing unit, connects the datarams to read the digital numerical value to be detected and multigroup critical value, to be detected to this
Digital numerical value carry out numerical values recited comparison, and export comparison code after store to the datarams；
One command unit, connects the datarams, reads the comparison code；And
One arithmetic logical unit, connects the command unit, and the wherein command unit is matched somebody with somebody according to the comparison code read
Close the arithmetic logical unit and perform corresponding program function.
8. a kind of numerical value comparator processor applied to electronic installation as claimed in claim 7, it is many that the datarams are stored
Group critical value is rewritable.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101140954A TWI607375B (en) | 2012-11-05 | 2012-11-05 | Numerical comparing method of a processor and the processor applied to an electronic device |
| TW101140954 | 2012-11-05 |
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| Publication Number | Publication Date |
|---|---|
| CN103809958A CN103809958A (en) | 2014-05-21 |
| CN103809958B true CN103809958B (en) | 2017-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210548321.6A Active CN103809958B (en) | 2012-11-05 | 2012-12-17 | Method for improving numerical value comparison efficiency of processor and numerical value comparison processor |
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| TW (1) | TWI607375B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5123108A (en) * | 1989-09-11 | 1992-06-16 | Wang Laboratories, Inc. | Improved cpu pipeline having register file bypass and working register bypass on update/access address compare |
| US5253349A (en) * | 1991-01-30 | 1993-10-12 | International Business Machines Corporation | Decreasing processing time for type 1 dyadic instructions |
| CN1466715A (en) * | 2000-09-28 | 2004-01-07 | ض� | Array search operation |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6795842B2 (en) * | 2000-12-27 | 2004-09-21 | International Business Machines Corporation | Method and apparatus for comparing two binary numbers with a power-of-two threshold |
| US20060236011A1 (en) * | 2005-04-15 | 2006-10-19 | Charles Narad | Ring management |
| US8984231B2 (en) * | 2009-12-22 | 2015-03-17 | Intel Corporation | Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments |
| TWI505104B (en) * | 2010-11-03 | 2015-10-21 | Inventec Corp | Controlling method for baseboard management controller with customization sensor data record |
-
2012
- 2012-11-05 TW TW101140954A patent/TWI607375B/en active
- 2012-12-17 CN CN201210548321.6A patent/CN103809958B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5123108A (en) * | 1989-09-11 | 1992-06-16 | Wang Laboratories, Inc. | Improved cpu pipeline having register file bypass and working register bypass on update/access address compare |
| US5253349A (en) * | 1991-01-30 | 1993-10-12 | International Business Machines Corporation | Decreasing processing time for type 1 dyadic instructions |
| CN1466715A (en) * | 2000-09-28 | 2004-01-07 | ض� | Array search operation |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201419137A (en) | 2014-05-16 |
| TWI607375B (en) | 2017-12-01 |
| CN103809958A (en) | 2014-05-21 |
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