CN103794519B - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN103794519B CN103794519B CN201210422474.6A CN201210422474A CN103794519B CN 103794519 B CN103794519 B CN 103794519B CN 201210422474 A CN201210422474 A CN 201210422474A CN 103794519 B CN103794519 B CN 103794519B
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Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, methods described includes：Semiconductor substrate is provided；Some laminations are formed over the substrate, and the lamination includes gate material layers, gate dielectric, channel layer and the gate dielectric being sequentially depositing；Pattern relative two sides in the lamination, to form the stairstepping gate stack that area is sequentially reduced from the bottom up, and gate material layers described in exposed portion, and then form grid structure, the lamination of the grid structure both sides is patterned, to form the stairstepping source and drain lamination that area is sequentially reduced from the bottom up, and channel layer described in exposed portion, source-drain area is formed further, over the substrate depositing first dielectric layer；The first interlayer dielectric layer is formed on first dielectric layer；Gate electrode and source-drain electrode are eventually formed, and then forms 3D transistors.As the setting of the 3D structures causes the drain current of semiconductor devices to become big, and the aggregation degree increase of device, further increase the performance of device.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and preparation method thereof.
Background technology
The raising of performance of integrated circuits mainly passes through the size for constantly reducing IC-components to improve its speed
Come what is realized.At present, due in high device density, high-performance and low cost is pursued semi-conductor industry have advanced to a nanometer skill
Art process node, particularly when dimensions of semiconductor devices drops to 22nm or following, from manufacture with the challenge of design aspect
Jing result in the development of three dimensional design such as FinFET (FinFET).
Relative to existing planar transistor, the FinFET is in raceway groove control and reduces the side such as shallow ridges channel effect
Face has more superior performance；Planar gate is arranged above the raceway groove, and the grid described in FinFET surround
The fin is arranged, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.In FinFET
The length of grid is obtained by measuring the parallel length of fin, and the width of the grid is the twice and fin of the fin height
Wide sum, the electric current and the electric capacity of grid of the height limitation of fin device, the width of fin can affect the threshold value electricity of device
Pressure and short channel control.
With the continuous development of CMOS technology, occurred in semiconductor devices technology of preparing three grids (Tri-gate),
FinFET, bigrid (Dual gate), or even there is the transistor without node (junction-less), strengthen device
Performance and integrated level.
The transistor without node (junction-less) is had been proposed at present, and the transistor is nano-wire transistor,
In N-shaped is without node transistor, in the source-drain area and raceway groove of the substrate, counterpoise is doped with the N-shaped doping of same type
Agent, in p-type is without node transistor, in the source-drain area and raceway groove of the substrate, counterpoise is doped with the p-type of same type and mixes
Miscellaneous dose.The preparation of the transistor enormously simplify preparation technology, can omit the ring of light/extension in this process and source/drain is noted
The step of entering, it is to avoid the step of formation gate stack carries out activation annealing after ion implanting, it is pre- so as to reduce producing heat
Calculate, while provide in the selection of gate metal and gate dielectric layer material more may.
Therefore, although in prior art, there is the transistor without node (junction-less), but preparation method at present
And the drain current of the transistor for obtaining is less, while as the reduction of size, integrated level are also affected, making semiconductor device
Part performance is restricted, it is therefore desirable to which current preparation method is improved, to eliminate the problems referred to above.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme required for protection
Key feature and essential features, more do not mean that the protection domain for attempting to determine technical scheme required for protection.
The invention provides a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided；
Form some laminations over the substrate, gate material layers that the lamination includes being sequentially depositing, gate dielectric,
Channel layer and gate dielectric；
Relative two sides in the lamination is patterned, is folded with forming the stairstepping grid that area is sequentially reduced from the bottom up
Layer, and gate material layers described in exposed portion, and then grid structure is formed,
The lamination of the grid structure both sides is patterned, is folded with forming the stairstepping source and drain that area is sequentially reduced from the bottom up
Layer, and channel layer described in exposed portion, and then source-drain area is formed,
Depositing first dielectric layer over the substrate, to cover the lamination；
The first interlayer dielectric layer is formed on first dielectric layer；
First interlayer dielectric layer and first dielectric layer are patterned, to form gate contact hole and source and drain contact
Hole；
The gate contact hole and the source and drain contact hole are filled using conductive material, to form gate electrode and source and drain electricity
Pole, and then form 3D transistors.
Preferably, the forming method of the grid structure and source-drain area is：
Some aspect product identical laminations, patterning the superiors lamination, so that the superiors are formed over the substrate
Area of the area of lamination less than lamination below, then lamination of the patterning below the superiors' lamination, by from
On order down pattern the lamination successively, to form stair-stepping laminated construction.
Preferably, the forming method of the grid structure and source-drain area is：
Some aspect product identical laminated construction are formed over the substrate, pattern the lamination of more than the bottom so as to
Area is less than bottom lamination, then patterns the lamination of more than the layer second from the bottom, is schemed by order from the bottom up successively
Lamination described in case, to form stair-stepping laminated construction.
Preferably, the gate stack is followed successively by the gate material layers, gate dielectric layer, described from top to bottom
Channel layer and the gate dielectric layer, gate material layers described in exposed portion between gate stack described in adjacent two layers, to be formed
Stepped grid structure.
Preferably, the source and drain lamination is followed successively by the channel layer, the gate dielectric layer, the grid from top to bottom
Material layer and the gate dielectric layer, channel layer described in exposed portion between source and drain lamination described in adjacent two layers, to form ladder
Shape source and drain.
Preferably, patterning first dielectric layer, with channel layer described in exposed portion, and in the source and drain lamination
Clearance wall is formed on the wall of side.
Preferably, patterning first dielectric layer, with gate material layers described in exposed portion and folded in the grid
Clearance wall is formed on the side wall of layer.
Preferably, methods described is further comprising the steps of：
Over the substrate after depositing first dielectric layer, the second interlayer dielectric layer is formed on first dielectric layer, so
The first interlayer dielectric layer is formed on second interlayer dielectric layer afterwards.
Preferably, patterning first interlayer dielectric layer, second interlayer dielectric layer and described the are then etched
One dielectric layer, to form gate contact hole and source and drain contact hole.
Preferably, methods described also includes the step of being doped to the source-drain area and raceway groove.
Preferably, the doping of peer-level is carried out to the source-drain area and the raceway groove.
Preferably, the doping of not peer-level is carried out to the source-drain area and the raceway groove.
Preferably, the gate material layers are Si.
Preferably, the doping of peer-level is carried out to the source-drain area and raceway groove.
Preferably, the depth and doped level of the adjustment raceway groove, control the threshold value electricity of the semiconductor devices
Pressure.
Preferably, selecting the material of gate material layers, the threshold voltage of the semiconductor devices is controlled.
Preferably, selecting epitaxial growth or atomic layer deposition method to deposit the gate dielectric, the gate material layers
And the channel layer.
Present invention also offers a kind of semiconductor devices, including：
Semiconductor substrate；
Grid structure on substrate, the grid structure include that the grid that some areas from the bottom up are sequentially reduced is folded
Layer, the gate stack include gate material layers, gate dielectric layer, channel layer and the gate dielectric layer for being formed from top to bottom；
Positioned at the source-drain area of the grid structure both sides, the source-drain area includes what some areas from the bottom up were sequentially reduced
Source and drain lamination, the channel layer that the source and drain lamination includes being formed from top to bottom, the gate dielectric layer, the grid material
Layer and the gate dielectric layer；
Gate electrode above grid structure and the source-drain electrode above source-drain area, for forming connection.
Preferably, gate material layers described in exposed portion between some gate stacks, to form grid.
Preferably, channel layer described in exposed portion between some source and drain laminations, to form source-drain area.
Preferably, the source and drain lamination and the gate stack be it is stepped.
Preferably, the device also includes the first dielectric layer on the laminated construction.
Preferably, the device also includes the first interlayer dielectric layer on first dielectric layer, the grid
Electrode and source-drain electrode are located in first interlayer dielectric layer.
Preferably, the device also includes the second interlayer dielectric layer on first dielectric layer, the ground floor
Between dielectric layer be located at second interlayer dielectric layer on.
Preferably, the gate material layers are Si.
The device that the method for the invention is prepared is 3D transistors, has grid material in the 3D transistors
The laminated construction of " sandwich " (sandwich structure) that layer, gate dielectric and channel layer are alternateed, institute
State mutually isolated by the gate dielectric between the structure of " sandwich " (sandwich structure), and institute
The area for stating multiple laminations is stepped reduction from the bottom up, and its section all around in four aspects is stairstepping
Shape, as the setting of the 3D structures causes the drain current of semiconductor devices to become big, and the aggregation degree increase of device, enter one
Step improves the performance of device.Additionally, in the present invention can also be by the depth of raceway groove and doped level, grid material
Select to control threshold voltage (Vth), make the threshold voltage (Vth) of semiconductor devices more stable.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this
Bright embodiment and its description, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 is the top view of semiconductor devices of the present invention and the profile along dotted line direction；
Preparation flow schematic diagrames of the Fig. 2-16 for semiconductor devices of the present invention；
Figure 17 is the process chart of the semiconductor devices for preparing the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without the need for one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, for some technical characteristics well known in the art do not enter
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
Conductor device and preparation method thereof.Obviously, execution of the invention is not limited to the spy is familiar with by the technical staff of semiconductor applications
Different details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have
Other embodiment.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that, when in this manual using term "comprising" and/or " including "
When, which indicates there is the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or many
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, exemplary embodiment of the invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Apply example to implement with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
It is understood by, there is provided these embodiments are in order that disclosure of the invention is thoroughly and complete, and by these exemplary enforcements
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region
Degree, and make to be presented with like reference characters identical element, thus description of them will be omitted.
It is described further with reference to the preparation method of Fig. 2-16 pair of semiconductor devices of the present invention：
First, there is provided Semiconductor substrate；
Specifically, the Semiconductor substrate can be at least one in the following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), it is laminated on insulator on silicon (SSOI), insulator and is laminated SiGe (S-SiGeOI), germanium on insulator SiClx
And germanium on insulator (GeOI) etc. (SiGeOI).Active area can be defined in Semiconductor substrate.May be used also on the active region
To include other active devices, in order to simplify accompanying drawing, described in shown figure, substrate and active device do not have
Sign.
Preferably, isolation structure is formed in the Semiconductor substrate, the isolation structure is that shallow trench isolates (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure.Be also formed with the Semiconductor substrate various traps (well) structure and
The channel layer of substrate surface.
Then some laminations are formed over the substrate, and the lamination includes the gate material layers 103, grid being sequentially depositing
Dielectric layer 102, channel layer 101 and gate dielectric layer 102；
The some laminations of area identical are formed first on substrate in the present invention, is then patterned relative in the lamination
Two sides, to form area is sequentially reduced from the bottom up stairstepping lamination, and gate material layers described in exposed portion, and then shape
Into grid structure；Then the lamination of the grid structure both sides is patterned, to form the ladder that area is sequentially reduced from the bottom up
Shape source and drain lamination, and channel layer described in exposed portion, and then form source-drain area.
Specifically, the gate stack and the source and drain lamination can regard the two-layer that staggered up and down as in the present invention,
The gate stack is followed successively by the gate material layers, the gate dielectric layer, the channel layer and the grid from top to bottom
Dielectric layer, therefore can be with gate material layers described in exposed portion, to form grid structure after etching the gate stack；The source
Leakage lamination is followed successively by the channel layer, the gate dielectric layer, the gate material layers and the gate dielectric layer from top to bottom,
Can be with channel layer described in exposed portion, to form source-drain area after etching the source and drain lamination；
It is described in detail with reference to the forming method of Fig. 2-9 pair of source and drain lamination, wherein forming the source and drain
The method of lamination has two kinds：
With reference first to Fig. 2, the lamination includes sequentially forming gate material layers 103, gate dielectric layer in the present invention
102nd, channel layer 101 and gate dielectric layer 102, in one embodiment of this invention, can be with positioned at uppermost source and drain lamination
It is otherwise varied with intermediary source bottom drain layer, gate material layers and gate dielectric are only included in the source and drain lamination of the superiors,
For forming gate electrode, pattern as shown in Figure 2 is obtained, pattern is the part in the laminated construction wherein shown in Fig. 2, and
Do not limit and pattern shown in Fig. 2.
Wherein described dielectric layer can include following any conventional dielectric：SiO2、Si3N4、SiON、SiON2, such as
TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3High-k dielectric and other the similar oxidations including perofskite type oxide
Thing, but not limited to this.
Bottom lamination is formed over the substrate, is then sequentially depositing gate material layers 103, gate dielectric layer 102, ditch
Channel layer 101 and gate dielectric layer 102 form the first lamination, then further formed on first lamination the second lamination,
Third and fourth lamination, the like, the layer number can be configured according to the needs of device, and this is not restricted.
Then pattern the left and right two sides of the lamination from the bottom up successively, form the stepped knot that area is sequentially reduced
Structure, forms source and drain lamination；Specifically, as shown in Fig. 2 patterning first to the 4th lamination, makes the first to the 4th lamination
Area reduces, and less than the lamination of the bottom, specific patterning method forms photoresist for first on the 4th lamination
Pattern, then etches first to the 4th lamination by mask layer of the pattern, and patterning method below is referred to
The method.
Wherein, the source and drain lamination is followed successively by channel layer, gate dielectric layer, gate material layers and gate dielectric from top to bottom
Layer, in the patterning process, after source and drain lamination is formed, can channel layer, the i.e. bottom and the first lamination described in exposed portion
Between expose is the part channel layer in the bottom, and expose between the first lamination and second lamination is
The part channel layer in one lamination, i.e., in described stairstepping source and drain lamination, step-like platform is channel layer, is formed with this
Source-drain area, as shown in the profile of upside in Fig. 1.
With reference to Fig. 3, second to the 4th lamination is patterned, the area of the second to the 4th lamination is made less than the first lamination
Area, channel layer described in exposed portion.
With reference to Fig. 4, the 3rd to the 4th lamination is patterned, the area of the 3rd to the 4th lamination is made less than the second lamination
Area.
With reference to Fig. 5, the 4th lamination is patterned, make the area of the 4th lamination less than the area of third layer stack, form institute
Source and drain lamination is stated for forming source-drain area.
The method for forming the laminated construction for second is essentially identical with the first, except that the order of patterning is
Carry out from top to bottom, the lamination being initially formed described in Fig. 1, referring next to Fig. 6, first pattern the 4th lamination of the superiors, method
The patterning method being referred in first method, referring next to Fig. 7-9, patterns described three, the second, first successively and folds
Layer, finally obtains laminated construction as shown in Figure 5, and the laminated construction is stepped knot all around on four direction
Structure, the part exposed between lamination are channel layer, form source-drain area with this.
Then to two-sided patternedization before and after the lamination, it is folded that the patterning method also has both of which to be referred to source and drain
The patterning method of layer, except that the gate stack is followed successively by the gate material layers, the grid being from top to bottom situated between
Matter layer, the channel layer and the gate dielectric layer, therefore, the grid after step-like gate stack is formed described in exposed portion
Pole material layer, formed grid structure, in stairstepping gate stack the platform of ladder be gate material layers, the right side in such as Fig. 1
Profile shown in.
Preferably, also including what the source-drain area and raceway groove of the 3D transistors were doped in the method for the invention
Step, can carry out the doping of peer-level in the present invention to the source and drain of the 3D transistors and raceway groove, or to the 3D
The source and drain and raceway groove of transistor carries out the doping of not peer-level specifically, when the gate material layers are Si, to the 3D
The source and drain and raceway groove of transistor carry out the doping of peer-level.
Further in the present invention, can also pass through to adjust the depth and doped level of the raceway groove, control described
The threshold voltage of 3D transistors, or by selecting the material of gate material layers, control the threshold voltage of the 3D transistors.
The forming method of the gate dielectric, gate material layers and channel layer can select atomic layer in the present invention
Deposition (ALD) or epitaxially grown method.
After grid structure and source-drain area is formed, gate electrode and source-drain electrode, the gate electrode and source are subsequently formed
The forming method of drain electrode also has two kinds, illustrates with reference to Fig. 9-16.
There is common step in two ways as shown in figure 9, depositing first dielectric layer 104 over the substrate, described
Dielectric layer can include following any conventional dielectric：SiO2、Si3N4、SiON、SiON2, such as TiO2、Al2O3、ZrO2、
HfO2、Ta2O5、La2O3High-k dielectric and other the similar oxides including perofskite type oxide, but not limited to this.Under
Face is illustrated to the first embodiment with reference to Figure 10-12, deposits the first interlayer dielectric layer 105 over the substrate, is covered
The laminated construction, the interlayer dielectric layer can select material commonly used in the art, repeat no more.
With reference to Figure 11, on the grid and both sides form gate contact hole and source and drain contact hole respectively, specifically,
Can be formed on first interlayer dielectric layer and mask layer and then be etched, etch first interlayer dielectric layer and described
First dielectric layer, to expose the gate material layers in channel layer and grid structure on the source-drain area respectively, while in institute
State and clearance wall is formed on the side wall of source and drain lamination, form clearance wall on the side wall of the gate stack, obtain as shown in figure 11
Contact hole.
With reference to Figure 12, the contact hole is filled from conductive material, to form gate electrode 108 and source-drain electrode 106.
Illustrate with reference to Figure 13-16 pair of second embodiment, first as shown in figure 13, in first dielectric
The second interlayer dielectric layer 107 is deposited on layer, the first interlayer dielectric layer 105 is then deposited again over the substrate.
With reference to Figure 14, first interlayer dielectric layer is etched to second interlayer dielectric layer, specifically, can be initially formed
Mask layer, such as photoresist layer, wherein dielectric layer and second interlayer dielectric layer have larger etching between the ground floor
Select ratio.
Reference picture 15-16, etches second interlayer dielectric layer and first dielectric layer, to expose the source and drain respectively
The gate material layers in interlayer dielectric layer and grid structure in area, while forming gap on the side wall of the source and drain lamination
Wall, forms clearance wall on the side wall of the gate stack, forms gate contact hole and source and drain contact hole respectively, then selects
Conductive material fills the contact hole, to form gate electrode 108 and source-drain electrode 106.
Present invention also offers a kind of semiconductor devices, including：
Semiconductor substrate；
Grid structure on substrate, the grid structure include that the grid that some areas from the bottom up are sequentially reduced is folded
Layer, the gate stack include the gate material layers, the gate dielectric layer, the channel layer and the institute for being formed from top to bottom
State gate dielectric layer；
Positioned at the source-drain area of the grid structure both sides, the source-drain area includes what some areas from the bottom up were sequentially reduced
Source and drain lamination, the channel layer that the source and drain lamination includes being formed from top to bottom, the gate dielectric layer, the grid material
Layer and the gate dielectric layer；
Gate electrode above grid structure and the source-drain electrode above source-drain area, for forming connection.
Specifically, described being stacked on four direction all around is step structure, is 3D structures.
Specifically, as shown in figure 1, wherein described lamination can be divided into gate stack and source and drain lamination, wherein the grid
The profile of lamination as shown in Fig. 1 right part of flg, expose between levels in gate stack for gate material layers, i.e. ladder
It is gate material layers at platform, is consequently formed grid structure.
Profile of the figure for source and drain lamination on the upside of Fig. 1, expose between levels in the source and drain lamination for channel layer,
It is channel layer i.e. at the platform of ladder, is consequently formed source-drain area.
Therefore, in the present invention it is considered that two material layers that mutually stagger between gate stack and the source and drain lamination.
In the present invention, the source and drain lamination and the gate stack are stepped, and the device for obtaining is in four direction
It is stepped.
Further, the device also includes the first dielectric layer on the laminated construction, positioned at first dielectric
The first interlayer dielectric layer on layer, the gate electrode and source-drain electrode are located in first interlayer dielectric layer.
Further, the device also includes the second interlayer dielectric layer on first dielectric layer, first interlayer
Dielectric layer is located on second interlayer dielectric layer.
The device that the method for the invention is prepared is 3D transistors, has raceway groove, dielectric in the 3D transistors
The lamination of " sandwich " (sandwich structure) that layer and gate material layers are alternateed, and it is the plurality of
The area of lamination is stepped reduction from the bottom up, and its section all around in four aspects is stairstepping, due to
The setting of the 3D structures causes the drain current of semiconductor devices to become big, and the aggregation degree increase of device, further improves
The performance of device.Additionally, in the present invention can also by the depth of raceway groove and doped level, grid material selection come
Control threshold voltage (Vth), makes the threshold voltage (Vth) of semiconductor devices more stable.
Figure 17 is to prepare the process chart that the present invention prepares semiconductor devices, is comprised the following steps：
Step 201 provides Semiconductor substrate；
Step 202 forms some laminations over the substrate, and the lamination includes gate material layers, the grid being sequentially depositing
Dielectric layer, channel layer and gate dielectric；
Step 203 patterns relative two sides in the lamination, to form the stairstepping that area is sequentially reduced from the bottom up
Gate stack, and gate material layers described in exposed portion, and then grid structure is formed,
Step 204 patterns the lamination of the grid structure both sides, to form the ladder that area is sequentially reduced from the bottom up
Shape source and drain lamination, and channel layer described in exposed portion, and then source-drain area is formed,
Step 205 depositing first dielectric layer over the substrate, to cover the lamination；
Step 206 forms the first interlayer dielectric layer on first dielectric layer；
Step 207 patterns first interlayer dielectric layer and first dielectric layer, to form gate contact hole and source
Miss contact hole；
Step 208 fills the gate contact hole and the source and drain contact hole using conductive material, to form gate electrode
And source-drain electrode, and then form 3D transistors.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching of the invention can also be made more kinds of
Variants and modifications, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (25)
1. a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided；
Form some laminations over the substrate, gate material layers that the lamination includes being sequentially depositing, gate dielectric, raceway groove
Layer and gate dielectric；
Relative two sides in the lamination is patterned, to form the stairstepping gate stack that area is sequentially reduced from the bottom up, and
Gate material layers described in exposed portion, and then grid structure is formed,
The lamination of the grid structure both sides is patterned, to form the stairstepping source and drain lamination that area is sequentially reduced from the bottom up,
And channel layer described in exposed portion, and then source-drain area is formed,
Depositing first dielectric layer over the substrate, to cover the lamination；
The first interlayer dielectric layer is formed on first dielectric layer；
First interlayer dielectric layer and first dielectric layer are patterned, to form gate contact hole and source and drain contact hole；
The gate contact hole and the source and drain contact hole are filled using conductive material, to form gate electrode and source-drain electrode,
And then form 3D transistors.
2. method according to claim 1, it is characterised in that the forming method of the grid structure and source-drain area is：
Some aspect product identical laminations, patterning the superiors lamination, so that the superiors' lamination are formed over the substrate
Area less than lamination below area, then lamination of the patterning below the superiors' lamination, by from upper past
Under order pattern the lamination successively, to form stair-stepping laminated construction.
3. method according to claim 1, it is characterised in that the forming method of the grid structure and source-drain area is：
Some aspect product identical laminated construction are formed over the substrate, pattern the lamination of more than the bottom so as to area
Less than bottom lamination, the lamination of more than layer second from the bottom is then patterned, patterned by order from the bottom up successively described
Lamination, to form stair-stepping laminated construction.
4. method according to claim 1, it is characterised in that the gate stack is followed successively by the grid material from top to bottom
The bed of material, the gate dielectric layer, the channel layer and the gate dielectric layer, exposed division between gate stack described in adjacent two layers
Divide the gate material layers, to form stepped grid structure.
5. method according to claim 1, it is characterised in that the source and drain lamination is followed successively by the raceway groove from top to bottom
Layer, the gate dielectric layer, the gate material layers and the gate dielectric layer, expose between source and drain lamination described in adjacent two layers
The part channel layer, to form stepped source and drain.
6. method according to claim 1, it is characterised in that patterning first dielectric layer, with described in exposed portion
Channel layer, and clearance wall is formed on the side wall of the source and drain lamination.
7. method according to claim 1, it is characterised in that patterning first dielectric layer, with described in exposed portion
Gate material layers, and clearance wall is formed on the side wall of the gate stack.
8. method according to claim 1, it is characterised in that methods described is further comprising the steps of：
Over the substrate after depositing first dielectric layer, the second interlayer dielectric layer, Ran Hou are formed on first dielectric layer
The first interlayer dielectric layer is formed on second interlayer dielectric layer.
9. method according to claim 8, it is characterised in that patterning first interlayer dielectric layer, then etches institute
The second interlayer dielectric layer and first dielectric layer are stated, to form gate contact hole and source and drain contact hole.
10. method according to claim 1, it is characterised in that methods described also includes entering the source-drain area and raceway groove
The step of row doping.
11. methods according to claim 10, it is characterised in that peer-level is carried out to the source-drain area and the raceway groove
Doping.
12. methods according to claim 10, it is characterised in that not equal water is carried out to the source-drain area and the raceway groove
Flat doping.
13. methods according to claim 1, it is characterised in that the gate material layers are Si.
14. methods according to claim 13, it is characterised in that peer-level is carried out to the source-drain area and raceway groove and is mixed
It is miscellaneous.
15. methods according to claim 1, it is characterised in that the depth and doped level of the adjustment raceway groove, control
Make the threshold voltage of the semiconductor devices.
16. methods according to claim 1, it is characterised in that select the material of gate material layers, control described partly to lead
The threshold voltage of body device.
17. methods according to claim 1, it is characterised in that described from epitaxial growth or atomic layer deposition method deposition
Gate dielectric, the gate material layers and the channel layer.
A kind of 18. semiconductor devices, including：
Semiconductor substrate；
Grid structure on substrate, the grid structure include the gate stack that some areas from the bottom up are sequentially reduced,
The gate stack includes gate material layers, gate dielectric layer, channel layer and the gate dielectric layer for being formed from top to bottom；
Positioned at the source-drain area of the grid structure both sides, the source-drain area includes the source and drain that some areas from the bottom up are sequentially reduced
Lamination, the channel layer that the source and drain lamination includes being formed from top to bottom, the gate dielectric layer, the gate material layers and
The gate dielectric layer；
Gate electrode above grid structure and the source-drain electrode above source-drain area, for forming connection.
19. devices according to claim 18, it is characterised in that grid described in exposed portion between some gate stacks
Pole material layer, to form grid.
20. devices according to claim 18, it is characterised in that ditch described in exposed portion between some source and drain laminations
Channel layer, to form source-drain area.
21. devices according to claim 18, it is characterised in that the source and drain lamination and the gate stack are ladder
Shape.
22. devices according to claim 18, it is characterised in that the device is also included on the laminated construction
First dielectric layer.
23. devices according to claim 22, it is characterised in that the device is also included on first dielectric layer
The first interlayer dielectric layer, the gate electrode and source-drain electrode are located in first interlayer dielectric layer.
24. devices according to claim 23, it is characterised in that the device is also included on first dielectric layer
Second interlayer dielectric layer, first interlayer dielectric layer are located on second interlayer dielectric layer.
25. devices according to claim 18, it is characterised in that the gate material layers are Si.
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