CN103794519A - Semiconductor device and method for preparing same - Google Patents
Semiconductor device and method for preparing same Download PDFInfo
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- CN103794519A CN103794519A CN201210422474.6A CN201210422474A CN103794519A CN 103794519 A CN103794519 A CN 103794519A CN 201210422474 A CN201210422474 A CN 201210422474A CN 103794519 A CN103794519 A CN 103794519A
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 232
- 238000003475 lamination Methods 0.000 claims abstract description 124
- 239000000463 material Substances 0.000 claims abstract description 62
- 238000000059 patterning Methods 0.000 claims abstract description 45
- 239000011229 interlayer Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000010276 construction Methods 0.000 claims description 15
- 238000002360 preparation method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The present invention relates to a semiconductor device and a method for preparing the same. The method comprises the steps of providing a semiconductor substrate on which a plurality of laminations are formed, wherein the laminations comprise a grid material layer, a grid dielectric layer, a channel layer and another one grid dielectric layer which are deposited orderly; patterning the relative two surfaces in the laminations to form a stepped grid lamination of which the area is reduced orderly from bottom to top and expose a part of the grid material layer to thereby form a grid structure, patterning the laminations at the two sides of the grid structure to form a stepped source-drain lamination of which the area is reduced orderly from bottom to top and expose a part of the channel layer to thereby form a source-drain area, and depositing a first dielectric layer on the substrate; forming a first interlayer dielectric layer on the first dielectric layer; and finally forming a grid electrode and a source-drain electrode to thereby form a 3D transistor. With the arrangement of a 3D structure, a drain current and the integration level of the semiconductor device are increased, and further the performance of the device is improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
The raising of performance of integrated circuits is mainly that the size by constantly dwindling integrated circuit (IC)-components realizes with the speed that improves it.At present, because semi-conductor industry in pursuit high device density, high-performance and low cost has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to 22nm or when following, from manufacturing and the challenge of design aspect has caused three dimensional design as the development of FinFET (FinFET).
With respect to existing planar transistor, described FinFET device has more superior performance at aspects such as raceway groove control and reduction shallow channel effects; Planar gate is arranged at described raceway groove top, and in gate loop described in FinFET around described fin setting, therefore can control static from three faces, the performance aspect electrostatic control is also more outstanding.In FinFET, the length of grid obtains by the parallel length of measuring fin, the width of described grid is twice and the wide sum of fin of described fin height, the limitation in height of fin the electric current of device and the electric capacity of grid, the width of fin can affect threshold voltage and the short channel control of device.
Along with the development of CMOS technology, three grids (Tri-gate), FinFET, bigrid (Dual gate) in semiconductor device technology of preparing, are there is, even there is the transistor without node (junction-less), carried out performance and the integrated level of enhance device.
Transistor without node (junction-less) has been proposed at present, described transistor is nano-wire transistor, N-shaped without node transistor in, in the source-drain area of described substrate and raceway groove all heavy doping the N-shaped dopant of same type, p-type without node transistor in, in the source-drain area of described substrate and raceway groove all heavy doping the p-type dopant of same type.Preparation technology has been simplified in described transistorized preparation greatly, in this process, can omit the step that the ring of light/expansion and source/leakage is injected, having avoided forming described gate stack carries out activating the step of annealing after Implantation, produce heat budget thereby reduce, more possibility is provided simultaneously in the selection of gate metal and gate dielectric layer material.
Therefore, although there is the transistor without node (junction-less) in prior art, but current preparation method and the transistorized drain current obtaining are less, reducing along with size simultaneously, integrated level is also affected, performance of semiconductor device is restricted, therefore needs current preparation method to improve, to eliminate the problems referred to above.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The preparation method who the invention provides a kind of semiconductor device, comprising:
Semiconductor substrate is provided;
On described substrate, form some laminations, described lamination comprises gate material layers, gate dielectric, channel layer and the gate dielectric of deposition successively;
Relative two sides in lamination described in patterning, to form the stairstepping gate stack that area reduces successively from the bottom up, and gate material layers described in exposed portions serve, and then form grid structure,
The lamination of grid structure both sides described in patterning, leaks lamination to form the stairstepping source that area reduces successively from the bottom up, and channel layer described in exposed portions serve, and then forms source-drain area,
On described substrate, deposit the first dielectric layer, to cover described lamination;
On described the first dielectric layer, form the first interlayer dielectric layer;
The first interlayer dielectric layer and described the first dielectric layer described in patterning, to form gate contact hole and drain contact hole, source;
Adopt electric conducting material to fill described gate contact hole and drain contact hole, described source, to form gate electrode and source-drain electrode, and then form 3D transistor.
As preferably, the formation method of described grid structure and source-drain area is:
On described substrate, form the long-pending identical lamination of some aspects, patterning the superiors lamination, so that the area of described the superiors lamination is less than the area of the lamination below it, then patterning is positioned at the lamination below described the superiors lamination, by lamination described in order from top to bottom successively patterning, to form stair-stepping laminated construction.
As preferably, the formation method of described grid structure and source-drain area is:
On described substrate, form the long-pending identical laminated construction of some aspects, the lamination more than patterning bottom, make its area be less than bottom lamination, then the above lamination of layer second from the bottom described in patterning, by lamination described in order from the bottom up successively patterning, to form stair-stepping laminated construction.
As preferably, described gate stack is followed successively by described gate material layers, described gate dielectric layer, described channel layer and described gate dielectric layer from top to bottom, gate material layers described in exposed portions serve between gate stack described in adjacent two layers, to form steplike-gate electrode structure.
As preferably, described source is leaked lamination and is followed successively by from top to bottom described channel layer, described gate dielectric layer, described gate material layers and described gate dielectric layer, and channel layer described in exposed portions serve is leaked between lamination in source described in adjacent two layers, leaks to form stepped source.
As preferably, the first dielectric layer described in patterning, with channel layer described in exposed portions serve, and leaks in described source on the sidewall of lamination and forms clearance wall.
As preferably, the first dielectric layer described in patterning with semiconductor material layer described in exposed portions serve, and forms clearance wall on the sidewall of described gate stack.
As preferably, described method is further comprising the steps of:
On described substrate, deposit after the first dielectric layer, on described the first dielectric layer, form the second interlayer dielectric layer, then on described the second interlayer dielectric layer, form the first interlayer dielectric layer.
As preferably, the first interlayer dielectric layer described in patterning, then the second interlayer dielectric layer and described the first dielectric layer described in etching, to form gate contact hole and drain contact hole, source.
As preferably, described method also comprises the step that described source-drain area and raceway groove are adulterated.
As preferably, described source-drain area and described raceway groove are carried out to the doping of peer-level.
As preferably, described source-drain area and described raceway groove are carried out to the not doping of peer-level.
As preferably, described gate material layers is Si.
As preferably, described source-drain area and raceway groove are carried out to the doping of peer-level.
As preferably, adjust the degree of depth and the doped level of described raceway groove, control the threshold voltage of described semiconductor device.
As preferably, select the material of gate material layers, control the threshold voltage of described semiconductor device.
As preferably, select epitaxial growth or atomic layer deposition method to deposit described gate dielectric, described gate material layers and described channel layer.
The present invention also provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the grid structure on substrate, described grid structure comprises the gate stack that some areas from the bottom up reduce successively, and described gate stack comprises the gate material layers, gate dielectric layer, channel layer and the gate dielectric layer that form from top to bottom;
Be positioned at the source-drain area of described grid structure both sides, described source-drain area comprises the source leakage lamination that some areas from the bottom up reduce successively, and described source is leaked lamination and comprised the described channel layer, described gate dielectric layer, described gate material layers and the described gate dielectric layer that form from top to bottom;
The gate electrode and the source-drain electrode that is positioned at source-drain area top that are positioned at grid structure top, be used to form connection.
As preferably, gate material layers described in exposed portions serve between described some gate stacks, to form grid.
As preferably, channel layer described in exposed portions serve is leaked between laminations in described some sources, to form source-drain area.
As preferably, lamination is leaked in described source and described gate stack is stepped.
As preferably, described device also comprises the first dielectric layer being positioned on described laminated construction.
As preferably, described device also comprises the first interlayer dielectric layer being positioned on described the first dielectric layer, and described gate electrode and source-drain electrode are arranged in described the first interlayer dielectric layer.
As preferably, described device also comprises and is positioned at the second interlayer dielectric layer on described the first dielectric layer, and described the first interlayer dielectric layer is positioned on described the second interlayer dielectric layer.
As preferably, described gate material layers is Si.
The device that the method for the invention prepares is 3D transistor, in described 3D transistor, there is gate material layers, " sandwich is sandwich " that gate dielectric and channel layer replace mutually laminated construction (sandwichstructure), between the structure of described " sandwich is sandwich " (sandwich structure), mutually isolate by described gate dielectric, and the area of described multiple laminations is from the bottom up stairstepping and reduces, all around, the cross section in four aspects is stairstepping for it, because the drain current that is arranged so that semiconductor device of described 3D structure becomes large, and the aggregation degree of device increases, further improve the performance of device.In addition, can also control threshold voltage (Vth) by the selection of the degree of depth of raceway groove and doped level, grid material in the present invention, make the threshold voltage (Vth) of semiconductor device more stable.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is the vertical view of semiconductor device of the present invention and the profile along dotted line direction;
Fig. 2-16 are the preparation flow schematic diagram of semiconductor device of the present invention;
Figure 17 is the process chart of preparation semiconductor device of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that semiconductor device of the present invention and preparation method thereof to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Preparation method below in conjunction with Fig. 2-16 pair semiconductor device of the present invention is described further:
First, provide Semiconductor substrate;
Particularly, described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In Semiconductor substrate, can be defined active area.On this active area, can also include other active device, in order to simplify accompanying drawing, shown in substrate described in figure and active device all do not indicate.
As preferably, in described Semiconductor substrate, form isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In described Semiconductor substrate, be also formed with the channel layer of various traps (well) structure and substrate surface.
Then on described substrate, form some laminations, described lamination comprises gate material layers 103, gate dielectric layer 102, channel layer 101 and the gate dielectric layer 102 of deposition successively;
First on substrate, form in the present invention some laminations that area is identical, then relative two sides in lamination described in patterning, to form the stairstepping lamination that area reduces successively from the bottom up, and gate material layers described in exposed portions serve, and then form grid structure; Then the lamination of grid structure both sides described in patterning, leaks lamination to form the stairstepping source that area reduces successively from the bottom up, and channel layer described in exposed portions serve, and then forms source-drain area.
Particularly, in the present invention described gate stack and described source leak lamination can regard as staggered up and down two-layer, described gate stack is followed successively by described gate material layers, described gate dielectric layer, described channel layer and described gate dielectric layer from top to bottom, therefore gate material layers described in can exposed portions serve after gate stack described in etching, to form grid structure; Described source is leaked lamination and is followed successively by from top to bottom described channel layer, described gate dielectric layer, described gate material layers and described gate dielectric layer, described in etching source leak after lamination can exposed portions serve described in channel layer, to form source-drain area;
The formation method of leaking lamination below in conjunction with pair described source, Fig. 2-9 is described in detail, and the method that wherein forms described source leakage lamination has two kinds:
First with reference to Fig. 2, described lamination comprises and forms successively gate material layers 103, gate dielectric layer 102, channel layer 10 and gate dielectric layer 102 in the present invention, in one embodiment of this invention, be positioned at uppermost source leak lamination can with the difference to some extent of intermediary source bottom drain layer, the source leakage lamination that is arranged in the superiors only comprises gate material layers and gate dielectric, be used for forming gate electrode, obtain pattern as shown in Figure 2, wherein pattern shown in Fig. 2 is the part in described laminated construction, does not limit and pattern shown in Fig. 2.
Wherein said dielectric layer can comprise following any conventional dielectric: SiO
2, Si
3n
4, SiON, SiON
2, such as TiO
2, Al
2o
3, ZrO
2, HfO
2, Ta
2o
5, La
2o
3high-k dielectric and comprise other similar oxide of perofskite type oxide, but be not limited to this.
On described substrate, form bottom lamination, then deposition of gate material layer 103, gate dielectric layer 102, channel layer 10 and gate dielectric layer 102 form the first lamination successively, then on described the first lamination, further form the second lamination, third and fourth lamination, the like, described lamination number can arrange according to the needs of device, and this is not restricted.
Then the two sides, left and right of lamination described in patterning successively from the bottom up, forms the step structure that area reduces successively, and lamination is leaked in formation source; Particularly, as shown in Figure 2, the first to the 4th lamination described in patterning, make first to reduce to the area of the 4th lamination, be less than the lamination of the described bottom, concrete patterning method for first forming photoetching agent pattern on described the 4th lamination, and then take described pattern as the first to the 4th lamination described in mask layer etching, patterning method below all can be with reference to the method.
Wherein, described source is leaked lamination and is followed successively by from top to bottom channel layer, gate dielectric layer, gate material layers and gate dielectric layer, in this patterning process, leak after lamination in formation source, channel layer described in meeting exposed portions serve, be that what between the bottom and the first lamination, expose is the described channel layer of part in the bottom, and what between the first lamination and described the second lamination, expose is the described channel layer of part in the first lamination, be that in described stairstepping source leakage lamination, step-like platform is channel layer, form source-drain area with this, as shown in the profile of upside in Fig. 1.
With reference to Fig. 3, the second to the 4th lamination described in patterning, makes second to be less than the area of the first lamination to the area of the 4th lamination, channel layer described in exposed portions serve.
With reference to Fig. 4, the 3rd to the 4th lamination described in patterning, makes the 3rd to be less than the area of the second lamination to the area of the 4th lamination.
With reference to Fig. 5, the 4th lamination described in patterning, makes the area of the 4th lamination be less than the area of the 3rd lamination, forms described source and leaks lamination and be used to form source-drain area.
It is basic identical that the second forms method and the first of described laminated construction, difference is that the order of patterning is to carry out from top to bottom, first form the lamination described in Fig. 1, then with reference to Fig. 6, the 4th lamination of the patterning the superiors of elder generation, method can be with reference to the patterning method in first method, then with reference to Fig. 7-9, successively described in patterning the 3rd, second, the first lamination, finally obtain laminated construction as shown in Figure 5, described laminated construction is step structure on four direction all around, the part of exposing between lamination is channel layer, form source-drain area with this.
Then two-sided patternedization of front and back to described lamination, described patterning method also has two kinds of patterning methods that all can leak with reference to source lamination, difference is that described gate stack is followed successively by described gate material layers, described gate dielectric layer, described channel layer and described gate dielectric layer from top to bottom, therefore, forming the gate material layers described in exposed portions serve after step-like gate stack, form grid structure, in stairstepping gate stack, the platform of ladder is gate material layers, as shown in the profile on the right side in Fig. 1.
As preferably, also comprise the step that the transistorized source-drain area of described 3D and raceway groove are adulterated in the method for the invention, can carry out the doping of peer-level to described 3D transistorized source leakage and raceway groove in the present invention, or to the doping that leaks in the transistorized source of described 3D and raceway groove carries out peer-level not particularly, in the time that described gate material layers is Si, described 3D transistorized source leakage and raceway groove are carried out to the doping of peer-level.
Further in the present invention, can also, by adjusting the degree of depth and the doped level of described raceway groove, control the transistorized threshold voltage of described 3D, or by selecting the material of gate material layers, control the transistorized threshold voltage of described 3D.
The formation method of described gate dielectric, gate material layers and channel layer can be selected ald (ALD) or epitaxially grown method in the present invention.
Forming after grid structure and source-drain area, then form gate electrode and source-drain electrode, the formation method of described gate electrode and source-drain electrode also has two kinds, describes below in conjunction with Fig. 9-16.
Have common step as shown in Figure 9 two kinds of modes, deposit the first dielectric layer 104 on described substrate, described dielectric layer can comprise following any conventional dielectric: SiO
2, Si
3n
4, SiON, SiON
2, such as TiO
2, Al
2o
3, ZrO
2, HfO
2, Ta
2o
5, La
2o
3high-k dielectric and comprise other similar oxide of perofskite type oxide, but be not limited to this.Describe below in conjunction with Figure 10-12 pair the first execution mode, deposit the first interlayer dielectric layer 105 on described substrate, cover described laminated construction, described interlayer dielectric layer can be selected this area common used material, repeats no more.
With reference to Figure 11, on described grid and both sides form respectively gate contact hole and drain contact hole, source, particularly, can on described the first interlayer dielectric layer, form mask layer and then carry out etching, the first interlayer dielectric layer and described the first dielectric layer described in etching, to expose respectively the gate material layers in channel layer and the grid structure on described source-drain area, on the sidewall of described source leakage lamination, form clearance wall simultaneously, on the sidewall of described gate stack, form clearance wall, obtain contact hole as shown in figure 11.
With reference to Figure 12, select electric conducting material to fill described contact hole, to form gate electrode 108 and source-drain electrode 106.
Describe below in conjunction with Figure 13-16 pair the second execution mode, first as shown in figure 13, on described the first dielectric layer, deposit the second interlayer dielectric layer 107, and then on described substrate, deposit the first interlayer dielectric layer 105.
With reference to Figure 14, the first interlayer dielectric layer, to described the second interlayer dielectric layer, particularly, can first form mask layer described in etching, for example photoresist layer, and wherein said the first interlayer dielectric layer and described the second interlayer dielectric layer have larger etching selectivity.
With reference to Figure 15-16, the second interlayer dielectric layer and described the first dielectric layer described in etching, to expose respectively the gate material layers in interlayer dielectric layer and the grid structure on described source-drain area, on the sidewall of described source leakage lamination, form clearance wall simultaneously, on the sidewall of described gate stack, form clearance wall, form respectively gate contact hole and drain contact hole, source, then select electric conducting material to fill described contact hole, to form gate electrode 108 and source-drain electrode 106.
The present invention also provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the grid structure on substrate, described grid structure comprises the gate stack that some areas from the bottom up reduce successively, and described gate stack comprises the described gate material layers, described gate dielectric layer, described channel layer and the described gate dielectric layer that form from top to bottom;
Be positioned at the source-drain area of described grid structure both sides, described source-drain area comprises the source leakage lamination that some areas from the bottom up reduce successively, and described source is leaked lamination and comprised the described channel layer, described gate dielectric layer, described gate material layers and the described gate dielectric layer that form from top to bottom;
The gate electrode and the source-drain electrode that is positioned at source-drain area top that are positioned at grid structure top, be used to form connection.
Particularly, described in be stacked in all around and be step structure on four direction, be 3D structure.
Particularly, as shown in Figure 1, wherein said lamination can be divided into gate stack and lamination is leaked in source, the profile of wherein said gate stack is as shown in Fig. 1 right part of flg, what in gate stack, between levels, expose is gate material layers, the platform place that is ladder is gate material layers, forms thus grid structure.
Fig. 1 upside figure is the profile that lamination is leaked in source, and what in described source leakage lamination, between levels, expose is channel layer, and the platform place of ladder is channel layer, forms thus source-drain area.
Therefore, can think that in the present invention gate stack and described source leak two material layers that mutually stagger between lamination.In the present invention, described source leakage lamination and described gate stack are stepped, and the device obtaining is stepped at four direction.
Further, described device also comprises the first dielectric layer being positioned on described laminated construction, is positioned at the first interlayer dielectric layer on described the first dielectric layer, and described gate electrode and source-drain electrode are arranged in described the first interlayer dielectric layer.
Further, described device also comprises and is positioned at the second interlayer dielectric layer on described the first dielectric layer, and described the first interlayer dielectric layer is positioned on described the second interlayer dielectric layer.
The device that the method for the invention prepares is 3D transistor, in described 3D transistor, there is " sandwich is sandwich " that raceway groove, dielectric layer and gate material layers replace mutually lamination (sandwichstructure), and the area of described multiple laminations is from the bottom up stairstepping and reduces, all around, the cross section in four aspects is stairstepping for it, because the drain current that is arranged so that semiconductor device of described 3D structure becomes large, and the aggregation degree of device increases, further improve the performance of device.In addition, can also control threshold voltage (Vth) by the selection of the degree of depth of raceway groove and doped level, grid material in the present invention, make the threshold voltage (Vth) of semiconductor device more stable.
Figure 17 is the process chart that preparation the present invention prepares semiconductor device, comprises the following steps:
Step 201 provides Semiconductor substrate;
Step 202 forms some laminations on described substrate, and described lamination comprises gate material layers, gate dielectric, channel layer and the gate dielectric of deposition successively;
Relative two sides in lamination described in step 203 patterning, to form the stairstepping gate stack that area reduces successively from the bottom up, and gate material layers described in exposed portions serve, and then form grid structure,
The lamination of grid structure both sides described in step 204 patterning, leaks lamination to form the stairstepping source that area reduces successively from the bottom up, and channel layer described in exposed portions serve, and then forms source-drain area,
Step 205 deposits the first dielectric layer on described substrate, to cover described lamination;
Step 206 forms the first interlayer dielectric layer on described the first dielectric layer;
The first interlayer dielectric layer and described the first dielectric layer described in step 207 patterning, to form gate contact hole and drain contact hole, source;
Step 208 adopts electric conducting material to fill described gate contact hole and drain contact hole, described source, to form gate electrode and source-drain electrode, and then forms 3D transistor.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (25)
1. a preparation method for semiconductor device, comprising:
Semiconductor substrate is provided;
On described substrate, form some laminations, described lamination comprises gate material layers, gate dielectric, channel layer and the gate dielectric of deposition successively;
Relative two sides in lamination described in patterning, to form the stairstepping gate stack that area reduces successively from the bottom up, and gate material layers described in exposed portions serve, and then form grid structure,
The lamination of grid structure both sides described in patterning, leaks lamination to form the stairstepping source that area reduces successively from the bottom up, and channel layer described in exposed portions serve, and then forms source-drain area,
On described substrate, deposit the first dielectric layer, to cover described lamination;
On described the first dielectric layer, form the first interlayer dielectric layer;
The first interlayer dielectric layer and described the first dielectric layer described in patterning, to form gate contact hole and drain contact hole, source;
Adopt electric conducting material to fill described gate contact hole and drain contact hole, described source, to form gate electrode and source-drain electrode, and then form 3D transistor.
2. method according to claim 1, is characterized in that, the formation method of described grid structure and source-drain area is:
On described substrate, form the long-pending identical lamination of some aspects, patterning the superiors lamination, so that the area of described the superiors lamination is less than the area of the lamination below it, then patterning is positioned at the lamination below described the superiors lamination, by lamination described in order from top to bottom successively patterning, to form stair-stepping laminated construction.
3. method according to claim 1, is characterized in that, the formation method of described grid structure and source-drain area is:
On described substrate, form the long-pending identical laminated construction of some aspects, the lamination more than patterning bottom, make its area be less than bottom lamination, then the above lamination of layer second from the bottom described in patterning, by lamination described in order from the bottom up successively patterning, to form stair-stepping laminated construction.
4. method according to claim 1, it is characterized in that, described gate stack is followed successively by described gate material layers, described gate dielectric layer, described channel layer and described gate dielectric layer from top to bottom, gate material layers described in exposed portions serve between gate stack described in adjacent two layers, to form steplike-gate electrode structure.
5. method according to claim 1, it is characterized in that, described source is leaked lamination and is followed successively by from top to bottom described channel layer, described gate dielectric layer, described gate material layers and described gate dielectric layer, described in adjacent two layers, channel layer described in exposed portions serve is leaked between lamination in source, leaks to form stepped source.
6. method according to claim 1, is characterized in that, the first dielectric layer described in patterning with channel layer described in exposed portions serve, and leaks in described source on the sidewall of lamination and forms clearance wall.
7. method according to claim 1, is characterized in that, the first dielectric layer described in patterning with semiconductor material layer described in exposed portions serve, and forms clearance wall on the sidewall of described gate stack.
8. method according to claim 1, is characterized in that, described method is further comprising the steps of:
On described substrate, deposit after the first dielectric layer, on described the first dielectric layer, form the second interlayer dielectric layer, then on described the second interlayer dielectric layer, form the first interlayer dielectric layer.
9. method according to claim 8, is characterized in that, the first interlayer dielectric layer described in patterning, and then the second interlayer dielectric layer and described the first dielectric layer described in etching, to form gate contact hole and drain contact hole, source.
10. method according to claim 1, is characterized in that, described method also comprises the step that described source-drain area and raceway groove are adulterated.
11. methods according to claim 10, is characterized in that, described source-drain area and described raceway groove are carried out to the doping of peer-level.
12. methods according to claim 10, is characterized in that, described source-drain area and described raceway groove are carried out to the not doping of peer-level.
13. methods according to claim 1, is characterized in that, described gate material layers is Si.
14. methods according to claim 13, is characterized in that, described source-drain area and raceway groove are carried out to the doping of peer-level.
15. methods according to claim 1, is characterized in that, adjust the degree of depth and the doped level of described raceway groove, control the threshold voltage of described semiconductor device.
16. methods according to claim 1, is characterized in that, select the material of gate material layers, control the threshold voltage of described semiconductor device.
17. methods according to claim 1, is characterized in that, select epitaxial growth or atomic layer deposition method to deposit described gate dielectric, described gate material layers and described channel layer.
18. 1 kinds of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the grid structure on substrate, described grid structure comprises the gate stack that some areas from the bottom up reduce successively, and described gate stack comprises the gate material layers, gate dielectric layer, channel layer and the gate dielectric layer that form from top to bottom;
Be positioned at the source-drain area of described grid structure both sides, described source-drain area comprises the source leakage lamination that some areas from the bottom up reduce successively, and described source is leaked lamination and comprised the described channel layer, described gate dielectric layer, described gate material layers and the described gate dielectric layer that form from top to bottom;
The gate electrode and the source-drain electrode that is positioned at source-drain area top that are positioned at grid structure top, be used to form connection.
19. devices according to claim 18, is characterized in that, gate material layers described in exposed portions serve between described some gate stacks, to form grid.
20. devices according to claim 18, is characterized in that, channel layer described in exposed portions serve between described some sources leakage laminations, to form source-drain area.
21. devices according to claim 18, is characterized in that, lamination is leaked in described source and described gate stack is stepped.
22. devices according to claim 18, is characterized in that, described device also comprises the first dielectric layer being positioned on described laminated construction.
23. devices according to claim 22, is characterized in that, described device also comprises the first interlayer dielectric layer being positioned on described the first dielectric layer, and described gate electrode and source-drain electrode are arranged in described the first interlayer dielectric layer.
24. devices according to claim 22, is characterized in that, described device also comprises and be positioned at the second interlayer dielectric layer on described the first dielectric layer, and described the first interlayer dielectric layer is positioned on described the second interlayer dielectric layer.
25. devices according to claim 18, is characterized in that, described gate material layers is Si.
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| KR20120006843A (en) * | 2010-07-13 | 2012-01-19 | 삼성전자주식회사 | Semiconductor devices and methods of fabricating the same |
| CN102468282A (en) * | 2010-11-17 | 2012-05-23 | 三星电子株式会社 | 3D semiconductor device and method for fabricating the same |
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| CN102169899A (en) * | 2010-02-10 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Layer structure for an n type or p type channel transistor and plane reverse circuit |
| KR20120006843A (en) * | 2010-07-13 | 2012-01-19 | 삼성전자주식회사 | Semiconductor devices and methods of fabricating the same |
| CN102468282A (en) * | 2010-11-17 | 2012-05-23 | 三星电子株式会社 | 3D semiconductor device and method for fabricating the same |
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