CN103780265A - Deserializers - Google Patents

Deserializers Download PDF

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Publication number
CN103780265A
CN103780265A CN201310302936.5A CN201310302936A CN103780265A CN 103780265 A CN103780265 A CN 103780265A CN 201310302936 A CN201310302936 A CN 201310302936A CN 103780265 A CN103780265 A CN 103780265A
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data
clock signal
internal clock
signal
aligned data
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CN201310302936.5A
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CN103780265B (en
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宋根洙
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SK Hynix Inc
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Hynix Semiconductor Inc
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Priority claimed from KR1020120118497A external-priority patent/KR101914297B1/en
Priority claimed from KR1020120118498A external-priority patent/KR20140052417A/en
Priority claimed from KR1020120137369A external-priority patent/KR101886671B1/en
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A deserializer is provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Description

Deserializer
The cross reference of related application
It is the priority of the priority of korean patent application of 10-2012-0118497,10-2012-0118498 and the application number submitted to Department of Intellectual Property of Korea S on November 29th, 2012 korean patent application that is 10-2012-0137369 that the application requires application number that on October 24th, 2012 submits to Department of Intellectual Property of Korea S, and its full content is incorporated herein by reference.
Technical field
Exemplary embodiment of the present invention relates to semiconductor circuit, more specifically, relates to deserializer.
Background technology
Along with semiconductor system is developed to high speed operation, the demand that forms the high data rate (or data communication of high bandwidth) between the semiconductor chip of each semiconductor system is increased gradually.In response to this demand, the various schemes of looking ahead (pre-fetch scheme) are proposed.The scheme of looking ahead can be with the data of latch serial input and the designing technique of output latch data is corresponding concurrently.In order to obtain parallel data, in semiconductor chip, produce and there is the clock signal (for example, multi-phase clock signal) of out of phase, and input or output data with multi-phase clock signal.
Summary of the invention
Embodiment is for deserializer.
According to various embodiment, a kind of deserializer comprises data alignment device, selective signal generator and selection output unit.Data alignment device be configured in response to mutually have out of phase internal clock signal and by data alignment, to produce high aligned data and low aligned data.The phase place of one that selective signal generator is configured to detect in response to phase detection signal in internal clock signal is selected signal to produce.Phase detection signal comprises according to writing command signal and writing the pulse that latent time, signal produced.Select output unit to be configured to export in response to selecting signal high aligned data or low aligned data as choosing aligned data.
According to other embodiment, a kind of deserializer comprises: internal clock generator, and described internal clock generator is configured to data strobe signal and complementary data gating signal frequency division to produce internal clock signal; Data alignment device, described data alignment device is configured in response to internal clock signal data alignment to produce high aligned data and low aligned data; Phase detection signal generator, described phase detection signal generator is configured to produce phase detection signal, and described phase detection signal comprises according to writing command signal and writing the pulse that latent time, signal produced; Selective signal generator, described selective signal generator is configured to detect in response to phase detection signal the phase place of in internal clock signal, to produce selection signal; And selection output unit, described selection output unit is configured to export in response to selecting signal high aligned data or low aligned data as choosing aligned data.
According to other embodiment, a kind of deserializer comprises: selective signal generator, the phase place of one that described selective signal generator is configured to detect in response to phase detection signal in internal clock signal selects signal, described phase detection signal to comprise according to writing command signal and writing the pulse producing latent time to produce; Clock phase controller, the inversion signal that described clock phase controller is configured to export internal clock signal or internal clock signal in response to selecting signal is as change over clock signal; And data alignment device, described data alignment device is configured in response to change over clock signal data alignment to produce aligned data.
According to other embodiment, a kind of deserializer comprises: internal clock generator, and described internal clock generator is configured to data strobe signal and complementary data gating signal frequency division to produce internal clock signal; Phase detection signal generator, described phase detection signal generator is configured to produce phase detection signal, and described phase detection signal comprises according to writing command signal and writing the pulse producing latent time; Selective signal generator, described selective signal generator is configured to detect in response to phase detection signal the phase place of in internal clock signal, to produce selection signal; Clock phase controller, the inversion signal that described clock phase controller is configured to export internal clocking or internal clocking in response to selecting signal is as change over clock signal; And data alignment device, described data alignment device is configured in response to change over clock signal data alignment to produce aligned data.
According to other embodiment, a kind of deserializer comprises: selective signal generator, the phase place of one that described selective signal generator is configured to detect in internal clock signal in response to phase detection signal selects signal, described phase detection signal to comprise according to writing command signal and writing the first pulse producing latent time to produce; First selector, described first selector is configured to export the first aligned data group in response to selecting signal or the second aligned data group is chosen aligned data group as first; And second selector, described second selector is configured to export the first aligned data group in response to selecting signal or the second aligned data group is chosen aligned data group as second.
According to other embodiment, a kind of deserializer comprises: phase controller, data selector and internal data generator.Phase controller is configured to produce phase detection signal, the first data input clock signal and the second data input clock signal, and phase detection signal, the first data input clock signal and the second data input clock signal comprise according to writing command signal and writing the corresponding pulses in the first pulse, the second pulse and the 3rd pulse producing latent time.Data selector is configured to export the first aligned data group or the second aligned data group is chosen aligned data group as first in response to selecting signal, and exports the first aligned data group in response to selecting signal or the second aligned data group is chosen aligned data group as second.Selection signal is that the phase place of by detecting in response to phase detection signal in the first internal clock signal to the four internal clock signals produces.Internal data generator is configured to that latch first chooses aligned data group to produce the first internal data group in response to the first data input clock signal, and is configured to that latch second chooses aligned data group to produce the second internal data group in response to the second data input clock signal.
According to other embodiment, a kind of method of unstringing comprises the following steps: in response to mutually have out of phase internal clock signal and by data alignment, for producing high aligned data and low aligned data; The phase place of one detecting in response to phase detection signal in the first internal clock signal to the four internal clock signals selects signal, described phase detection signal to comprise according to writing command signal and writing the pulse that latent time, signal produced to produce; And export high aligned data or low aligned data in response to selecting signal as choosing aligned data.
Accompanying drawing explanation
With appended detailed description, the embodiment of the present invention's design will become clearer by reference to the accompanying drawings, wherein:
Fig. 1 is that explanation is according to the block diagram of the configuration of the deserializer of an embodiment;
Fig. 2 is the block diagram of the data alignment device that comprises of the deserializer of key diagram 1;
Fig. 3 and Fig. 4 are the sequential charts of the operation of the deserializer shown in key diagram 1;
Fig. 5 is that explanation is according to the block diagram of the configuration of the deserializer of an embodiment;
Fig. 6 is the block diagram of the data alignment device that comprises of the deserializer of key diagram 5;
Fig. 7 and Fig. 8 are the sequential charts of the operation of the deserializer shown in key diagram 5;
Fig. 9 is that explanation is according to the block diagram of the configuration of the deserializer of an embodiment;
Figure 10 is the block diagram of the configuration of the data alignment device that comprises of the deserializer of key diagram 9;
Figure 11 is the block diagram of the configuration of the data selector that comprises of the deserializer of key diagram 9; And
Figure 12 and Figure 13 are the sequential charts of the operation of the deserializer shown in key diagram 9.
Embodiment
The various embodiment of the present invention's design are more fully described hereinafter with reference to the accompanying drawings.But various embodiment described herein only for purposes of illustration, are not intended to limit the scope of the present invention's design.
Fig. 1 is that explanation is according to the block diagram of the configuration of the deserializer of various embodiment.
As shown in fig. 1, can be configured to comprise according to the deserializer of various embodiment: internal clock generator 1, data alignment device 2, phase detection signal generator 3, selective signal generator 4 and selection output unit 5.
Internal clock generator 1 can be by data strobe signal DQS and complementary data gating signal DQSB frequency division to produce the first internal clock signal IDQS, the second internal clock signal QDQS, the 3rd internal clock signal IDQSB and the 4th internal clock signal QDQSB.Internal clock generator 1 can be configured to comprise frequency divider.Therefore, the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can for example, be the twices of data strobe signal DQS and complementary data gating signal DQSB by producing generating period (, cycle time).The first internal clock signal IDQS can lead over the phase place of the second internal clock signal QDQS90 degree, the second internal clock signal QDQS can lead over the phase place of the 3rd internal clock signal IDQSB90 degree, and the 3rd internal clock signal IDQSB can lead over the phase place of the 4th internal clock signal QDQSB90 degree.
Data alignment device 2 can be aimed at data DIN in response to the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB, to produce the first high aligned data ALIGNA<1:8> of high aligned data to the eight and the low aligned data ALIGNB<1:8> of the first low aligned data to the eight.When the phase place of the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is while being normal, the high aligned data ALIGNA<1:8> of the first high aligned data to the eight can be properly aligned.On the contrary, when the phase place of the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is while being anti-phase, the low aligned data ALIGNB<1:8> of the first low aligned data to the eight can be properly aligned.With reference to Fig. 2, the configuration to data aligner 2 and operation are described in detail subsequently.
Phase detection signal generator 3 can receive and write command signal WT and write signal WLS latent time, with light from the time of write signal WT input through writing latent time WL(Fig. 3 and the WL of Fig. 4) and doubly after (wherein, " N " represents positive integer) corresponding scheduled time, produce phase detection signal IWT_PD with " N " in cycle of clock signal clk.According to the present embodiment, for sensing or detect the phase place of the second internal clock signal QDQS, can the time that is applied to phase detection signal generator 3 from writing command signal WT light through writing latent time WL and the twice in cycle of clock signal clk after produce phase detection signal IWT_PD.In various embodiments, can produce phase detection signal IWT_PD with one in the phase place of sensing or detection the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB.
Selective signal generator 4 can be selected signal SEL with of detecting in the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB to produce in response to phase detection signal IWT_PD.In the present embodiment, select the logic level of signal SEL to determine according to the phase place of time point the second internal clock signal QDQS producing at phase detection signal IWT_PD.; when the second internal clock signal QDQS is in the time that the rising edge of phase detection signal IWT_PD has logic " height " level; select signal SEL to be produced into and there is logic " height " level; and when the second internal clock signal QDQS is in the time that the rising edge of phase detection signal IWT_PD has logic " low " level, select signal SEL to be produced into and there is logic " low " level.
Select output unit 5 to export the first high aligned data ALIGNA<1:8> of high aligned data to the eight or the low aligned data ALIGNB<1:8> of the first low aligned data to the eight chooses aligned data to the eight to choose aligned data ALIGNSEL<1:8> as first according to the logic level of selecting signal SEL.In the present embodiment, in the time selecting signal SEL to there is logic " height " level, selecting output unit 5 can export the high aligned data ALIGNA<1:8> of the first high aligned data to the eight chooses aligned data to the eight to choose aligned data ALIGNSEL<1:8> as first, and in the time selecting signal SEL to there is logic " low " level, selecting output unit 5 can export the low aligned data ALIGNB<1:8> of the first low aligned data to the eight chooses aligned data to the eight to choose aligned data ALIGNSEL<1:8> as first.
Fig. 2 is the block diagram of the configuration of the data alignment device 2 that comprises of the deserializer of key diagram 1.
As shown in Figure 2, data alignment device 2 can be configured to comprise data buffer 21, the first aligner 22 and the second aligner 23.Data buffer 21 can be configured to comprise the first buffer 211, the second buffer 212, the 3rd buffer 213 and the 4th buffer 214.The first aligner 22 can be configured to comprise the first latch portion 221, the second latch portion 222, the 3rd latch portion 223, the 4th latch portion 224, the 5th latch portion 225, the 6th latch portion 226, the 7th latch portion 227 and the 8th latch portion 228.The second aligner 23 can be configured to comprise the 9th latch portion 231, the tenth the 232, the 11 the 233, the 12 the 234, the 13 the 235, the 14 the 236, the 15 the 237 and the 16 latch portion 238 of latch portion of latch portion of latch portion of latch portion of latch portion of latch portion.
The first buffer 211 can with the rising edge of the first internal clock signal IDQS synchronously buffered data DIN to export the first buffered data BD<1>.The second buffer 212 can with the rising edge of the second internal clock signal QDQS synchronously buffered data DIN to export the second buffered data BD<2>.The 3rd buffer 213 can with the rising edge of the 3rd internal clock signal IDQSB synchronously buffered data DIN to export the 3rd buffered data BD<3>.The 4th buffer 214 can with the rising edge of the 4th internal clock signal QDQSB synchronously buffered data DIN to export the 4th buffered data BD<4>.Each can being realized as in the first buffer to the four buffers 211,212,213 and 214 comprises trigger.Thereby each in the first buffer to the four buffers 211,212,213 and 214 can latch and cushioned its input data, and can export the input data that are latched and cushion.
The first latch portion 221 can with the synchronously latch export the first buffered data BD<1> of the rising edge of the second internal clock signal QDQS.The second latch portion 222 can with the synchronously latch export the second buffered data BD<2> of the rising edge of the 3rd internal clock signal IDQSB.The 3rd latch portion 223 can with the synchronously latch export the 3rd buffered data BD<3> of the rising edge of the 4th internal clock signal QDQSB.The 4th latch portion 224 can with the synchronously latch export the output signal of the second latch portion 222 of the rising edge of the 4th internal clock signal QDQSB.The 5th latch portion 225 can with the synchronously latch export the output signal of the first latch portion 221 of the rising edge of the 4th internal clock signal QDQSB.The 6th latch portion 226 can with the synchronously latch export the output signal of the 4th latch portion 224 of the rising edge of the 4th internal clock signal QDQSB.The 7th latch portion 227 can with the synchronously latch export the output signal of the 3rd latch portion 223 of the rising edge of the 4th internal clock signal QDQSB.The 8th latch portion 228 can with the synchronously latch export the 4th buffered data BD<4> of the rising edge of the 4th internal clock signal QDQSB.Each can being realized as in the first eight latch portions 221,222,223,224,225,226,227 and 228 of latch portion to the comprises trigger.Thereby each in the first eight latch portions 221,222,223,224,225,226,227 and 228 of latch portion to the can latch and cushioned its input data, and can export the input data that are latched and cushion.
The output signal of the first latch portion 221 can be corresponding with the 5th high aligned data ALIGNA<5>, and the output signal of the 5th latch portion 225 can be corresponding with the first high aligned data ALIGNA<1>.In addition, the output signal of the 4th latch portion 224 can be corresponding with the 6th high aligned data ALIGNA<6>, and the output signal of the 6th latch portion 226 can be corresponding with the second high aligned data ALIGNA<2>.In addition, the output signal of the 3rd latch portion 223 can be corresponding with the 7th high aligned data ALIGNA<7>, and the output signal of the 7th latch portion 227 can be corresponding with third high aligned data ALIGNA<3>.In addition, the 4th buffered data BD<4> can be corresponding with the 8th high aligned data ALIGNA<8>, and the output signal of the 8th latch portion 228 can be corresponding with the 4th high aligned data ALIGNA<4>.
The 9th latch portion 231 can with the synchronously latch export the 3rd buffered data BD<3> of the rising edge of the 4th internal clock signal QDQSB.The tenth latch portion 232 can with the synchronously latch export the 4th buffered data BD<4> of the rising edge of the first internal clock signal IDQS.The 11 latch portion 233 can with the synchronously latch export the first buffered data BD<1> of the rising edge of the second internal clock signal QDQS.The 12 latch portion 234 can with the synchronously latch export the output signal of the tenth latch portion 232 of the rising edge of the second internal clock signal QDQS.The 13 latch portion 235 can with the synchronously latch export the output signal of the 9th latch portion 231 of the rising edge of the second internal clock signal QDQS.The 14 latch portion 236 can with the synchronously latch export the output signal of the 12 latch portion 234 of the rising edge of the second internal clock signal QDQS.The 15 latch portion 237 can with the synchronously latch export the output signal of the 11 latch portion 233 of the rising edge of the second internal clock signal QDQS.The 16 latch portion 238 can with the synchronously latch export the second buffered data BD<2> of the rising edge of the second internal clock signal QDQS.Each can being realized as in the 9th 16 latch portions 231,232,233,234,235,236,237 and 238 of latch portion to the comprises trigger.Thereby each in the 9th 16 latch portions 231,232,233,234,235,236,237 and 238 of latch portion to the can latch and cushioned its input data, and can export the input data that are latched and cushion.
The output signal of the 9th latch portion 231 can be corresponding with the 5th low aligned data ALIGNB<5>, and the output signal of the 13 latch portion 235 can be corresponding with the first low aligned data ALIGNB<1>.In addition, the output signal of the 12 latch portion 234 can be corresponding with the 6th low aligned data ALIGNB<6>, and the output signal of the 14 latch portion 236 can be corresponding with the second low aligned data ALIGNB<2>.In addition, the output signal of the 11 latch portion 233 can be corresponding with the 7th low aligned data ALIGNB<7>, and the output signal of the 15 latch portion 237 can be corresponding with the 3rd low aligned data ALIGNB<3>.In addition, the second buffered data BD<2> can be corresponding with the 8th low aligned data ALIGNB<8>, and the output signal of the 16 latch portion 238 can be corresponding with the 4th low aligned data ALIGNB<4>.
As the first internal clock signal to the four internal clock signal IDQS, QDQS, when the phase place of IDQSB and QDQSB is normal at the time point of data DIN input, data alignment device 2 can carry out sequentially latch and aim at the first buffered data BD<1> via the first aligner 22, the second buffered data BD<2>, the 3rd buffered data BD<3> and the 4th buffered data BD<4> are to produce the high aligned data ALIGNA<1:8> of the first high aligned data to the eight.Alternatively, as the first internal clock signal to the four internal clock signal IDQS, QDQS, when the phase place of IDQSB and QDQSB is anti-phase at the time point of data DIN input, data alignment device 2 can carry out sequentially latch and aim at the 3rd buffered data BD<3> via the second aligner 23, the 4th buffered data BD<4>, the first buffered data BD<1> and the second buffered data BD<2> are to produce the low aligned data ALIGNB<1:8> of the first low aligned data to the eight.
The operation of aforementioned deserializer is more fully described with reference to Fig. 3 and Fig. 4 hereinafter.To the operation that be produced into the operation of deserializer while having normal phase place and produced into deserializer while having anti-phase phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB be described respectively.In the present embodiment, for explaining simple and object easily, suppose to write latent time WL and be configured to " 2 ", leading time tWPRE(for example, the time " tDQSS ") be configured to " 1tCK ".Leading time tWPRE may be defined as the time point that writes WL termination latent time to the period of the time point of data DIN input.Although leading time tWPRE is the single cycle time (tCK or 1tCK) that the time " tDQSS " is configured to have clock signal clk in the present embodiment, in other embodiment, leading time tWPRE can be configured to have " tDQSS+ positive integer × tCK ".
Now, will with reference to Fig. 3, the operation that is produced into deserializer while having normal phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB be described hereinafter.
If writing command signal WT inputs at time point t11, data DIN can from time point t11 through writing latent time WL and the time point t13 of time tDQSS be imported into data alignment device 2, and phase detection signal IWT_PD can from write latent time WL stop time point t12 elapsed time 2tCK(for example, two cycle times of clock signal clk) time point t15 produce.
The first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can normally produce from the time point t13 of elapsed time tDQSS from time point t12.; the first internal clock signal IDQS can be created on and have predetermined cycle time after time point t13 by product, and the second internal clock signal QDQS can be created on after time point t13 has postponed the time point t14 of 90 degree phase places and have predetermined cycle time by product.In addition, the 3rd internal clock signal IDQSB can be created on after time point t14 has postponed the time point t15 of 90 degree phase places and have predetermined cycle time by product, and the 4th internal clock signal QDQSB can be produced into have postponed 90 from time point t15 and have predetermined cycle time after spending the time point t16 of phase places.
As shown in Figure 3, the second internal clock signal QDQS can have logic " height " level at the time point t15 corresponding with the rising edge of phase detection signal IWT_PD.Thereby, select signal SEL to be produced into and from time point t15, there is logic " height " level.Result, select output unit 5 can select the high aligned data ALIGNA<1:8> of the first high aligned data to the eight in the first high aligned data ALIGNA<1:8> of high aligned data to the eight and the low aligned data ALIGNB<1:8> of the first low aligned data to the eight, export thus the high aligned data ALIGNA<1:8> of the first high aligned data to the eight and choose aligned data to the eight to choose aligned data ALIGNSEL<1:8> as first.As shown in Figure 3, the high aligned data ALIGNA<1:8> of the first high aligned data to the eight can with via sequentially latch and to aim at concurrently the signal of the first buffered data to the four buffered data BD<1:4> corresponding of the first aligner (22 in Fig. 2).In Fig. 3, Reference numeral t17, t18, t19, t20, t21, t22, t23 and t24 represent respectively sequentially to have postponed the time point of the half period of clock signal clk from time point t16.
With reference to Fig. 4, the operation that is produced into deserializer while having anti-phase phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is described hereinafter.
If writing command signal WT inputs at time point t31, data DIN can from time point t31 through writing latent time WL and the time point t33 of time tDQSS be input to data alignment device 2, and phase detection signal IWT_PD can from write latent time WL stop time point t32 elapsed time 2tCK(for example, two cycle times of clock signal clk) time point t35 produce.
The first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be produced into from writing the time point t32 that latent time, WL stopped has anti-phase phase place., the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can sequentially be produced into and from time point t32, be had anti-phase phase place.Particularly, the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be shifted the phase place of 180 degree compared with the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and the QDQSB shown in Fig. 3.
As shown in Figure 4, the second internal clock signal QDQS can have logic " low " level at the time point t35 corresponding with the rising edge of phase detection signal IWT_PD.Thereby, select output unit 5 can select the low aligned data ALIGNB<1:8> of the first low aligned data to the eight in the first high aligned data ALIGNA<1:8> of high aligned data to the eight and the low aligned data ALIGNB<1:8> of the first low aligned data to the eight, export thus the low aligned data ALIGNB<1:8> of the first low aligned data to the eight and choose aligned data to the eight to choose aligned data ALIGNSEL<1:8> as first.As shown in Figure 4, the low aligned data ALIGNB<1:8> of the first low aligned data to the eight can with via sequentially latch and to aim at concurrently the signal of the 3rd buffered data BD<3>, the 4th buffered data BD<4>, the first buffered data BD<1> and the second buffered data BD<2> corresponding of the second aligner (23 in Fig. 2).
As mentioned above, no matter be that internal clock signal is produced into while having normal phase place or internal clock signal is produced into while having anti-phase phase place, can be by the data alignment of serial input according to the deserializer of the present embodiment, and can detect sometime and put the phase place of in internal clock signal, optionally to export the aligned data of particular group.Therefore, there is anti-phase phase place even if internal clock signal produces into, also can not aim at mistakenly input data.
Fig. 5 is explanation according to various other the block diagrams of configuration of deserializer of embodiment.
As shown in Figure 5, can be configured to comprise according to the deserializer of an embodiment: internal clock generator 6, clock phase controller 7, phase detection signal generator 8, selective signal generator 9 and data alignment device 10.
Internal clock generator 6 can be by data strobe signal DQS and complementary data gating signal DQSB frequency division to produce the first internal clock signal IDQS, the second internal clock signal QDQS, the 3rd internal clock signal IDQSB and the 4th internal clock signal QDQSB.Internal clock generator 6 can be configured to comprise frequency divider.Therefore, the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can for example, be the twice of data strobe signal DQS and complementary data gating signal DQSB by producing generating period (, cycle time).The first internal clock signal IDQS can lead over the phase place of the second internal clock signal QDQS90 degree, the second internal clock signal QDQS can lead over the phase place of the 3rd internal clock signal IDQSB90 degree, and the 3rd internal clock signal IDQSB can lead over the phase place of the 4th internal clock signal QDQSB90 degree.
The inversion signal that clock phase controller 7 can be exported the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB or the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB in response to selecting signal SEL is as the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT.For example, in the time selecting signal SEL to there is logic " height " level, clock phase controller 7 can be exported the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB are as the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT, and in the time selecting signal SEL to there is logic " low " level, clock phase controller 7 can be exported the first internal clock signal to the four internal clock signal IDQS, QDQS, the inversion signal of IDQSB and QDQSB is as the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT.
Phase detection signal generator 8 can receive and write command signal WT and write signal WLS latent time, with light from the time that writes command signal WT input through writing latent time WL(Fig. 7 and the WL of Fig. 8) and doubly after (wherein, " N " represents positive integer) corresponding scheduled time, produce phase detection signal IWT_PD with " N " in cycle of clock signal of system CLK.According to the present embodiment, for sensing or detect the phase place of the second internal clock signal QDQS, can the time that is applied to phase detection signal generator 8 from writing command signal WT light through writing latent time WL and the one-period (1tCK) of clock signal of system CLK produce afterwards phase detection signal IWT_PD.In various embodiments, can produce phase detection signal IWT_PD with one in the phase place of sensing or detection the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB.
Selective signal generator 9 can detect in response to phase detection signal IWT_PD in the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB one and select signal SEL to produce.In the present embodiment, select the logic level of signal SEL to determine according to the phase place of time point the second internal clock signal QDQS producing at phase detection signal IWT_PD.; when the second internal clock signal QDQS is in the time that the rising edge of phase detection signal IWT_PD has logic " height " level; select signal SEL to be produced into and there is logic " height " level; and when the second internal clock signal QDQS is in the time that the rising edge of phase detection signal IWT_PD has logic " low " level, select signal SEL to be produced into and there is logic " low " level.
Data alignment device 10 can aim to produce the first aligned data to the eight aligned data ALIGN<1:8> by data DIN in response to the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT.Configuration and operation with reference to Fig. 6 to data aligner 10 are described in detail.
Fig. 6 is the block diagram of the configuration of the data alignment device 10 that comprises of the deserializer of key diagram 5.
As shown in Figure 6, data alignment device 10 can be configured to comprise data buffer 101 and aligner 102.Data buffer 101 can be configured to comprise the first buffer 1011, the second buffer 1012, the 3rd buffer 1013 and the 4th buffer 1014.Aligner 102 can be configured to comprise the first latch portion 1021, the second latch portion 1022, the 3rd latch portion 1023, the 4th latch portion 1024, the 5th latch portion 1025, the 6th latch portion 1026, the 7th latch portion 1027 and the 8th latch portion 1028.
The first buffer 1011 can with the rising edge of the first change over clock signal IDQST synchronously buffered data DIN to export the first buffered data BD<1>.The second buffer 1012 can with the rising edge of the second change over clock signal QDQST synchronously buffered data DIN to export the second buffered data BD<2>.The 3rd buffer 1013 can with the rising edge of the 3rd change over clock signal IDQSBT synchronously buffered data DIN to export the 3rd buffered data BD<3>.The 4th buffer 1014 can with the rising edge of the 4th change over clock signal QDQSBT synchronously buffered data DIN to export the 4th buffered data BD<4>.Each can being realized as in the first buffer to the four buffers 1011,1012,1013 and 1014 comprises trigger.Thereby each in the first buffer to the four buffers 1011,1012,1013 and 1014 can latch and cushioned its input data, and can export the input data that are latched and cushion.
The first latch portion 1021 can with the synchronously latch export the first buffered data BD<1> of the rising edge of the second change over clock signal QDQST.The second latch portion 1022 can with the synchronously latch export the second buffered data BD<2> of the rising edge of the 3rd change over clock signal IDQSBT.The 3rd latch portion 1023 can with the synchronously latch export the 3rd buffered data BD<3> of the rising edge of the 4th change over clock signal QDQSBT.The 4th latch portion 1024 can with the synchronously latch export the output signal of the second latch portion 1022 of the rising edge of the 4th change over clock signal QDQSBT.The 5th latch portion 1025 can with the synchronously latch export the output signal of the first latch portion 1021 of the rising edge of the 4th change over clock signal QDQSBT.The 6th latch portion 1026 can with the synchronously latch export the output signal of the 4th latch portion 1024 of the rising edge of the 4th change over clock signal QDQSBT.The 7th latch portion 1027 can with the synchronously latch export the output signal of the 3rd latch portion 1023 of the rising edge of the 4th change over clock signal QDQSBT.The 8th latch portion 1028 can with the synchronously latch export the 4th buffered data BD<4> of the rising edge of the 4th change over clock signal QDQSBT.
The output signal of the first latch portion 1021 can be corresponding with the 5th aligned data ALIGN<5>, and the output signal of the 5th latch portion 1025 can be corresponding with the first aligned data ALIGN<1>.In addition, the output signal of the 4th latch portion 1024 can be corresponding with the 6th aligned data ALIGN<6>, and the output signal of the 6th latch portion 1026 can be corresponding with the second aligned data ALIGN<2>.In addition, the output signal of the 3rd latch portion 1023 can be corresponding with the 7th aligned data ALIGN<7>, and the output signal of the 7th latch portion 1027 can be corresponding with third high aligned data ALIGN<3>.In addition, the 4th buffered data BD<4> can be corresponding with the 8th aligned data ALIGN<8>, and the output signal of the 8th latch portion 1028 can be corresponding with the 4th aligned data ALIGN<4>.
Data alignment device 10 can be at the time point of data DIN input in response to the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT and buffered data DIN, and can carry out sequentially latch and aim at the first buffered data to the four buffered data BD<1> via aligner 102, BD<2>, BD<3> and BD<4> are to produce the first aligned data to the eight aligned data ALIGN<1:8>.
The operation of aforesaid deserializer is more fully described with reference to Fig. 7 and Fig. 8 hereinafter.To the operation that be produced into the operation of deserializer while having normal phase place and produced into deserializer while having anti-phase phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB be described respectively.In the present embodiment, for explaining simple and object easily, suppose to write latent time WL and be configured to " 2 ", leading time tWPRE is configured to four cycles " 4tCK " of clock signal of system CLK.Leading time tWPRE may be defined as the period writing between time point and the time point of data DIN input that latent time, WL stopped.Although leading time tWPRE is configured to have four cycle times " 4tCK " of clock signal of system CLK in the present embodiment, in other embodiment, leading time tWPRE can be configured to have " positive integer × tCK ".
Now, with reference to Fig. 7, the operation that is produced into deserializer while having normal phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is described hereinafter.
If writing command signal WT inputs at time point t51, data DIN can from time point t51 through writing latent time WL and the time point t56 of leading time tWPRE be imported into data alignment device 10, and phase detection signal IWT_PD can produce at the time point t54 through the one-period time 1tCK of clock signal of system CLK from writing the time point t52 that latent time, WL stopped.
The first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be produced into from writing the time point t52 that latent time, WL stopped has normal phase place.; the first internal clock signal IDQS can be created on and have predetermined cycle time after time point t52 by product, and the second internal clock signal QDQS can be created on after time point t52 has postponed the time point t53 of 90 degree phase places and have predetermined cycle time by product.In addition, the 3rd internal clock signal IDQSB can be created on after time point t53 has postponed the time point t54 of 90 degree phase places and have predetermined cycle time by product, and the 4th internal clock signal QDQSB can be created on and postpone 90 from time point t54 and have predetermined cycle time after spending the time point t55 of phase places by product.
As shown in Figure 7, the second internal clock signal QDQS can have logic " height " level at the time point t54 corresponding with the rising edge of phase detection signal IWT_PD.Thereby, select signal SEL to be produced into and from time point t54, there is logic " height " level.As a result, clock phase controller 7 can be exported the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB as the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT.
Data alignment device 10 can aim to produce the first aligned data to the eight aligned data ALIGN<1:8> by data DIN in response to the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT.In Fig. 7, Reference numeral t57, t58, t59, t60, t61, t62, t63, t64, t65, t66 and t67 represent respectively the time point of the half period that has sequentially postponed clock signal of system CLK from time point t56.
With reference to Fig. 8, the operation that is produced into deserializer while having anti-phase phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is described hereinafter.
If writing command signal WT inputs at time point t71, data DIN can from time point t71 through writing latent time WL and the time point t77 of leading time tWPRE be imported into data alignment device 10, and phase detection signal IWT_PD can produce at the time point t73 through the one-period time 1tCK of clock signal of system CLK from writing the time point t72 that latent time, WL stopped.
The first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be produced into from writing the time point t72 that latent time, WL stopped has anti-phase phase place., the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can sequentially be produced into and from time point t72, be had anti-phase phase place.Particularly, the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be shifted the phase place of 180 degree compared with the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and the QDQSB shown in Fig. 7.
As shown in Figure 8, the second internal clock signal QDQS can have logic " low " level at the time point t73 corresponding with the rising edge of phase detection signal IWT_PD.Thereby, select signal SEL to be produced into and there is logic " low " level.Result, clock phase controller 7 can be by anti-phase to the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB, and the inversion signal that can export the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is as the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT., even the first internal clock signal to the four internal clock signal IDQS of Fig. 8, QDQS, IDQSB and QDQSB have the first internal clock signal to the four internal clock signal IDQS of Fig. 7, QDQS, the inverted phases of IDQSB and QDQSB, the first change over clock signal to the four change over clock signal IDQST that export from the clock phase controller 7 of Fig. 8, QDQST, IDQSBT and QDQSBT also can be produced into the first change over clock signal to the four change over clock signal IDQST that have with Fig. 7, QDQST, the phase place that IDQSBT and QDQSBT are identical and cycle.
Data alignment device 10 can aim to produce the first aligned data to the eight aligned data ALIGN<1:8> by data DIN in response to the first change over clock signal to the four change over clock signal IDQST, QDQST, IDQSBT and QDQSBT.In Fig. 8, Reference numeral t74, t75 and t76 represent respectively the time point of the half period that has sequentially postponed clock signal of system CLK from time point t73.In addition, Reference numeral t78, t79, t80, t81, t82, t83, t84, t85, t86, t87 and t88 represent respectively the time point of the half period that has sequentially postponed clock signal of system CLK from time point t77.
As mentioned above, when internal clock signal is produced into while having anti-phase phase place singularly, can be by the reverse-phase of internal clock signal to produce change over clock signal according to the deserializer of the present embodiment, and can be by the input data alignment of serial input with output parallel data.Therefore, there is anti-phase phase place even if internal clock signal produces into singularly, also can not cushion mistakenly and aim at concurrently input data.
Fig. 9 is explanation according to various other the block diagrams of configuration of deserializer of embodiment.
As shown in Figure 9, can be configured to comprise internal clock generator 11, data alignment device 12, phase controller 13, selective signal generator 14, data selector 15 and internal data generator 16 according to the deserializer of various embodiment.
Internal clock generator 11 can be by data strobe signal DQS and complementary data gating signal DQSB frequency division to produce the first internal clock signal IDQS, the second internal clock signal QDQS, the 3rd internal clock signal IDQSB and the 4th internal clock signal QDQSB.Internal clock generator 11 can be configured to comprise frequency divider.Therefore, the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be produced into the twice that be data strobe signal DQS and complementary data gating signal DQSB cycle time.The first internal clock signal IDQS can lead over the phase place of the second internal clock signal QDQS90 degree, the second internal clock signal QDQS can lead over the phase place of the 3rd internal clock signal IDQSB90 degree, and the 3rd internal clock signal IDQSB can lead over the phase place of the 4th internal clock signal QDQSB90 degree.
Data alignment device 12 can aim to produce the first aligned data to the eight aligned data ALIGN<1:8> by data DIN in response to the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB.With reference to Figure 10, configuration to data aligner 12 and the detailed description of operation are described subsequently.
Phase controller 13 can receive and write command signal WT and write signal WLS latent time, to produce the phase detection signal IWT_PD that comprises the first pulse, described the first pulse light from the time that writes command signal WT input through writing latent time WL(Figure 12 and the WL of Figure 13) and doubly after (wherein, " N " represents positive integer) corresponding scheduled time slot, produce with " N " in cycle of clock signal of system CLK.According to the present embodiment, for sensing or detect the phase place of the second internal clock signal QDQS, can light through writing WL and two cycles (2tCK) of clock signal of system CLK the first pulse of producing afterwards phase detection signal IWT_PD latent time in the time that is applied to phase controller 13 from writing command signal WT.The first pulse can be produced into has the pulse corresponding with the one-period (1tCK) of clock signal of system CLK.In addition, phase controller 13 can receive and write command signal WT and write signal WLS latent time, to produce the first data input clock signal DINCLK<1> that comprises the second pulse and the second data input clock signal DINCLK<2> that comprises the 3rd pulse, the second pulse and the 3rd pulse can from write time that latent time, WL stopped light through with " N " in cycle of clock signal of system CLK doubly (wherein, " N " represents positive integer) corresponding other scheduled time slot generation afterwards.In the present embodiment, can light and producing afterwards the second pulse through four cycles (4tCK) of clock signal of system CLK from writing time that latent time, WL stopped, and can light and produce afterwards the 3rd pulse through five cycles (5tCK) of clock signal of system CLK from writing time that latent time, WL stopped.The second pulse can be produced into and be had the pulse duration corresponding with the half period of clock signal of system CLK with the 3rd pulse.But in various embodiments, rising edge point and the pulse duration of the first pulse to the three pulses can change according to design.
Selective signal generator 14 can detect in response to phase detection signal IWT_PD in the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB one and select signal SEL to produce.In the present embodiment, select the logic level of signal SEL to determine according to the phase place of time point the second internal clock signal QDQS producing at phase detection signal IWT_PD.; when the second internal clock signal QDQS is in the time that the rising edge of phase detection signal IWT_PD has logic " height " level; select signal SEL to be produced into and there is logic " height " level; and when the second internal clock signal QDQS is in the time that the rising edge of phase detection signal IWT_PD has logic " low " level, select signal SEL to be produced into and there is logic " low " level.In the time selecting signal SEL to be produced into there is logic " height " level, can light and sequentially produce the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB from the time of data DIN input.That is, there is normal phase place if the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB produce into, select signal SEL to be produced into and there is logic " height " level.Alternatively, in the time selecting signal SEL to be produced into there is logic " low " level, can light and sequentially produce the 3rd internal clock signal IDQSB, the 4th internal clock signal QDQSB, the first internal clock signal IDQS and the second internal clock signal QDQS from the time of data DIN input.That is, there is anti-phase phase place if the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB produce into, select signal SEL to be produced into and there is logic " low " level.In various embodiments, selective signal generator 14 can be configured to detect in response to phase detection signal IWT_PD in the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB any one select signal SEL to produce.
Data selector 15 can receive the first aligned data to the eight aligned data ALIGN<1:8>, optionally to export first and to choose aligned data to the eight to choose aligned data ALIGNSEL<1:8> according to selecting the logic level of signal SEL.In the present embodiment, in the time selecting signal SEL to have logic " height " level, data selector 15 can be exported the first aligned data group and choose aligned data group as first, and can export the second aligned data group and choose aligned data group as second.The first aligned data group can comprise: the first aligned data ALIGN<1>, the second aligned data ALIGN<2>, the 5th aligned data ALIGN<5> and the 6th aligned data ALIGN<6>, the second aligned data group can comprise: the 3rd aligned data ALIGN<3>, the 4th aligned data ALIGN<4>, the 7th aligned data ALIGN<7> and the 8th aligned data ALIGN<8>.First chooses aligned data group to comprise: first chooses aligned data ALIGNSEL<1>, second chooses aligned data ALIGNSEL<2>, the 5th chooses aligned data ALIGNSEL<5> and the 6th to choose aligned data ALIGNSEL<6>, second chooses aligned data group to comprise: the 3rd chooses aligned data ALIGNSEL<3>, the 4th chooses aligned data ALIGNSEL<4>, the 7th chooses aligned data ALIGNSEL<7> and the 8th to choose aligned data ALIGNSEL<8>.In the present embodiment, in the time selecting signal SEL to have logic " low " level, data selector 15 can be exported the first aligned data group and choose aligned data group as second, and can export the second aligned data group and choose aligned data group as first.Configuration and operation with reference to Figure 11 to data selector 15 are described in detail.
Internal data generator 16 can with the first data input clock signal and the second data input clock signal DINCLK<1:2> synchronously latch first choose aligned data to the eight to choose aligned data ALIGNSEL<1:8> to produce the first internal data to the eight internal data IDATA<1:8>.In the present embodiment, internal data generator 16 can with the first data input clock signal DINCLK<1> synchronously latch first choose aligned data group to produce the first internal data group, and can with the second data input clock signal DINCLK<2> synchronously latch second choose aligned data group to produce the second internal data group.The first internal data group can comprise: the first internal data IDATA<1>, the second internal data IDATA<2>, the 5th internal data IDATA<5> and the 6th internal data IDATA<6>, the second internal data group can comprise: the 3rd internal data IDATA<3>, the 4th internal data IDATA<4>, the 7th internal data IDATA<7> and the 8th internal data IDATA<8>.
Figure 10 is the block diagram of the configuration of explanation data alignment device 12.
As shown in Figure 10, data alignment device 12 can be configured to comprise data buffer 121 and aligner 122.Data buffer 121 can be configured to comprise the first buffer 1211, the second buffer 1212, the 3rd buffer 1213 and the 4th buffer 1214.Aligner 122 can be configured to comprise the first latch portion 1221, the second latch portion 1222, the 3rd latch portion 1223, the 4th latch portion 1224, the 5th latch portion 1225 and the 6th latch portion 1226.
The first buffer 1211 can with the rising edge of the first internal clock signal IDQS synchronously buffered data DIN to export the first aligned data ALIGN<1>.The second buffer 1212 can with the rising edge of the second internal clock signal QDQS synchronously buffered data DIN to export the second aligned data ALIGN<2>.The 3rd buffer 1213 can with the rising edge of the 3rd internal clock signal IDQSB synchronously buffered data DIN to export the 3rd aligned data ALIGN<3>.The 4th buffer 1214 can with the rising edge of the 4th internal clock signal QDQSB synchronously buffered data DIN to export the 4th aligned data ALIGN<4>.In the present embodiment, each can being realized as in the first buffer to the four buffers 1211,1212,1213 and 1214 comprises trigger.Thereby each in the first buffer to the four buffers 1211,1212,1213 and 1214 can latch and cushioned its input data, and can export the input data that are latched and cushion.
The first latch portion 1221 can with the synchronously latch export the first aligned data ALIGN<1> of the rising edge of the 3rd internal clock signal IDQSB.The second latch portion 1222 can with the synchronously latch export the output signal of the first latch portion 1221 of the rising edge of the 4th internal clock signal QDQSB.The 3rd latch portion 1223 can with the synchronously latch export the second aligned data ALIGN<2> of the rising edge of the 4th internal clock signal QDQSB.The 4th latch portion 1224 can with the synchronously latch export the 3rd aligned data ALIGN<3> of the rising edge of the first internal clock signal IDQS.The 5th latch portion 1225 can with the synchronously latch export the output signal of the 4th latch portion 1224 of the rising edge of the 4th internal clock signal QDQSB.The 6th latch portion 1226 can with the synchronously latch export the 4th aligned data ALIGN<4> of the rising edge of the second internal clock signal QDQS.The output signal of the second latch portion 1222 can be corresponding with the 5th aligned data ALIGN<5>, and the output signal of the 3rd latch portion 1223 can be corresponding with the 6th aligned data ALIGN<6>.In addition, the output signal of the 5th latch portion 1225 can be corresponding with the 7th aligned data ALIGN<7>, and the output signal of the 6th latch portion 1226 can be corresponding with the 8th aligned data ALIGN<8>.In the present embodiment, each can being realized as in the first six latch portions 1221,1222,1223,1224,1225 and 1226 of latch portion to the comprises trigger.Thereby each in the first six latch portions 1221,1222,1223,1224,1225 and 1226 of latch portion to the can latch and cushioned its input data, and can export the input data that are latched and cushion.
In the time selecting signal SEL to there is logic " height " level, data alignment device 12 can with the synchronously data DIN of latch serial input sequentially of the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB, produce the first aligned data to the four aligned data ALIGN<1:4> with the intervening sequences ground of the half period at clock signal of system CLK (0.5tCK).In addition, in the time selecting signal SEL to there is logic " height " level, data alignment device 12 can be by a half period (1.5tCK) of the first aligned data ALIGN<1> delay system clock signal clk to produce the 5th aligned data ALIGN<5>, can be by the one-period (1tCK) of the second aligned data ALIGN<2> delay system clock signal clk to produce the 6th aligned data ALIGN<6>, can be by a half period (1.5tCK) of the 3rd aligned data ALIGN<3> delay system clock signal clk to produce the 7th aligned data ALIGN<7>, and can be by the one-period (1tCK) of the 4th aligned data ALIGN<4> delay system clock signal clk to produce the 8th aligned data ALIGN<8>.Alternatively, in the time selecting signal SEL to there is logic " low " level, data alignment device 12 can with the first internal clock signal to the four internal clock signal IDQS, QDQS, the synchronously data DIN of latch serial input sequentially of IDQSB and QDQSB, intervening sequences ground with the half period at clock signal of system CLK (0.5tCK) produces the 3rd aligned data ALIGN<3>, the 4th aligned data ALIGN<4>, the first aligned data ALIGN<1> and the second aligned data ALIGN<2>.In addition, in the time selecting signal SEL to there is logic " low " level, data alignment device 12 can be by a half period (1.5tCK) of the 3rd aligned data ALIGN<3> delay system clock signal clk to produce the 7th aligned data ALIGN<7>, can be by the one-period (1tCK) of the 4th aligned data ALIGN<4> delay system clock signal clk to produce the 8th aligned data ALIGN<8>, can be by a half period (1.5tCK) of the first aligned data ALIGN<1> delay system clock signal clk to produce the 5th aligned data ALIGN<5>, and can be by the one-period (1tCK) of the second aligned data ALIGN<2> delay system clock signal clk to produce the 6th aligned data ALIGN<6>.
Figure 11 is the block diagram of the configuration of explanation data selector 15.
As shown in Figure 11, data selector 15 can be configured to comprise first selector 151 and second selector 152.In the time selecting signal SEL to there is logic " height " level, first selector 151 can be exported the first aligned data group ALIGN<1, 2, 5, 6> chooses aligned data group ALIGNSEL<1 as first, 2, 5, 6>, and in the time selecting signal SEL to there is logic " low " level, first selector 151 can be exported the second aligned data group ALIGN<3, 4, 7, 8> chooses aligned data group ALIGNSEL<1 as first, 2, 5, 6>.In the time selecting signal SEL to there is logic " height " level, second selector 152 can be exported the second aligned data group ALIGN<3, 4, 7, 8> chooses aligned data group ALIGNSEL<3 as second, 4, 7, 8>, and in the time selecting signal SEL to there is logic " low " level, second selector 152 can be exported the first aligned data group ALIGN<1, 2, 5, 6> chooses aligned data group ALIGNSEL<3 as second, 4, 7, 8>.
The operation of aforementioned deserializer is more fully described with reference to Figure 12 and Figure 13 hereinafter.Describe the operation of deserializer in the time that the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB have normal phase place and have the selection signal SEL of logic " height " level to produce with reference to Figure 12, and describe the operation of deserializer in the time that the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB have singularly anti-phase phase place and have the selection signal SEL of logic " low " level with generation with reference to Figure 13.In the present embodiment, for explaining simple and object easily, suppose to write latent time WL and be configured to " 2 ", and time tDQSS is configured to the one-period " 1tCK " of clock signal of system CLK.Time tDQSS represents restriction or the standard of the territory intersection nargin (domain crossing margin) between data strobe signal DQS and clock signal of system CLK., time tDQSS can be defined as synchronously producing the needed minimum period of active data gating signal DQS with clock signal of system CLK.Leading time tWPRE can be defined as writing the period between time point and the time point of data DIN input that latent time, WL stopped.Although leading time tWPRE is configured to equal time tDQSS in the present embodiment, leading time tWPRE can be configured to have " tDQSS+ positive integer × tCK " in various embodiments.
Now, will with reference to Figure 12, the operation that is produced into deserializer while having normal phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB be described hereinafter.
If writing command signal WT inputs at time point t101, data DIN can from time point t101 through writing latent time WL and the time point t103 of time tDQSS be imported into data alignment device 12, and the first pulse of phase detection signal IWT_PD can produce at the time point t105 through two cycles (2tCK) of clock signal of system CLK from writing the time point t102 that latent time, WL stopped.Because the second internal clock signal QDQS has logic " height " level at the time point t105 corresponding with the rising edge of phase detection signal IWT_PD, from time point t105, there is logic " height " level so select signal SEL to be produced into.The second pulse of the first data input clock signal DINCLK<1> can produce at the time point t109 through four cycles (4tCK) of clock signal of system CLK from writing the time point t102 that latent time, WL stopped.In addition, the 3rd pulse of the second data input clock signal DINCLK<2> can produce at the time point t111 through five cycles (5tCK) of clock signal of system CLK from writing the time point t102 that latent time, WL stopped.
The first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can normally produce from the time point t103 of elapsed time tDQSS after writing the time point t102 that latent time, WL stopped.; the first internal clock signal IDQS can normally be produced into has predetermined cycle time from time point t103, and the second internal clock signal QDQS can normally be produced into the time point t104 that has postponed 90 degree phase places from time point t103 has predetermined cycle time.In addition, the 3rd internal clock signal IDQSB can normally be produced into the time point t105 that has postponed 90 degree phase places from time point t104 has predetermined cycle time, and the 4th internal clock signal QDQSB can normally be produced into the time point t106 that has postponed 90 degree phase places from time point t105 has predetermined cycle time.
Data alignment device 12 can with the synchronously data DIN of latch serial input sequentially of clock signal of system CLK, produce the first aligned data to the four aligned data ALIGN<1:4> with the intervening sequences ground of the half period at clock signal of system CLK (0.5tCK).Can by from time point t103 until from time point t103 through the first data of the time point t107 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t107 until from time point t107 the 5th data through the time point t111 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the first aligned data ALIGN<1>.Can by from time point t104 until from time point t104 through the second data of the time point t108 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t108 until from time point t108 the 6th data through the time point t112 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the second aligned data ALIGN<2>.Can by from time point t105 until from time point t105 through the 3rd data of the time point t109 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t109 until from time point t109 the 7th data through the time point t113 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the 3rd aligned data ALIGN<3>.Can by from time point t106 until from time point t106 through the 4th data of the time point t110 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t110 until from time point t110 the 8th data through the time point t114 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the 4th aligned data ALIGN<4>.
Data alignment device 12 can be by a half period (1.5tCK) of the first aligned data ALIGN<1> delay system clock signal clk to produce the 5th aligned data ALIGN<5>, can be by the one-period (1tCK) of the second aligned data ALIGN<2> delay system clock signal clk to produce the 6th aligned data ALIGN<6>, can be by a half period (1.5tCK) of the 3rd aligned data ALIGN<3> delay system clock signal clk to produce the 7th aligned data ALIGN<7>, and can be by the one-period (1tCK) of the 4th aligned data ALIGN<4> delay system clock signal clk to produce the 8th aligned data ALIGN<8>.Result, can by from time point t106 until the first data of time point t110 latch data DIN and from time point t110 until the 5th data of time point t114 latch data DIN produce the 5th aligned data ALIGN<5>, and can by from time point t106 until the second data of time point t110 latch data DIN and from time point t110 until the 6th data of time point t114 latch data DIN produce the 6th aligned data ALIGN<6>.In addition, can by from time point t108 until the 3rd data of time point t112 latch data DIN and from time t112 until produce the 7th aligned data ALIGN<7> from time point t112 through the 7th data of the time point t115 latch data DIN in two cycles (2tCK) of clock signal of system CLK, and can by from time point t108 until the 4th data of time point t112 latch data DIN and from time point t112 until the 8th data of time point t115 latch data DIN produce the 8th aligned data ALIGN<8>.
Data selector 15 can receive the selection signal SEL with logic " height " level, to export the first aligned data group ALIGN<1,2,5,6> chooses aligned data group ALIGNSEL<1 as first, 2,5,6>, and output the second aligned data group ALIGN<3,4,7,8> chooses aligned data group ALIGNSEL<3,4 as second, 7,8>.
The time point t109 that internal data generator 16 can be inputted with the second pulse of the first data input clock signal DINCLK<1> synchronously latch first chooses aligned data group ALIGNSEL<1,2,5,6>, produce thus the first internal data group IDATA<1,2,5,6>.In addition, the time point t111 that data selector 15 can be inputted with the 3rd pulse of the second data input clock signal DINCLK<2> synchronously latch second chooses aligned data group ALIGNSEL<3,4,7,8>, produces the second internal data group IDATA<3,4 thus, 7,8>.
With reference to Figure 13, the operation that is produced into deserializer while having anti-phase phase place as the first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB is described hereinafter.
If writing command signal WT inputs at time point t121, data DIN can from time point t121 through writing latent time WL and the time point t123 of time tDQSS be imported into data alignment device 12, and the first pulse of phase detection signal IWT_PD can produce at the time point t125 through two cycles (2tCK) of clock signal of system CLK from writing the time point t122 that latent time, WL stopped.Because the second internal clock signal QDQS has logic " low " level at the time point t125 corresponding with the rising edge of phase detection signal IWT_PD, from time point t125, there is logic " low " level so select signal SEL to be produced into.The second pulse of the first data input clock signal DINCLK<1> can produce at the time point t129 through four cycles (4tCK) of clock signal of system CLK from writing the time point t122 that latent time, WL stopped.In addition, the 3rd pulse of the second data input clock signal DINCLK<2> can produce at the time point t131 through five cycles (5tCK) of clock signal of system CLK from writing the time point t122 that latent time, WL stopped.
The first internal clock signal to the four internal clock signal IDQS, QDQS, IDQSB and QDQSB can be produced into from the time point t123 of elapsed time tDQSS after writing the time point t122 that latent time, WL stopped singularly has anti-phase phase place.; the 3rd internal clock signal IDQSB can be produced into singularly has predetermined cycle time from time point t123, and the 4th internal clock signal QDQSB can be produced into the time point t124 that has postponed 90 degree phase places from time point t123 singularly has predetermined cycle time.In addition, the first internal clock signal IDQS can be produced into the time point t125 that has postponed 90 degree phase places from time point t124 singularly has predetermined cycle time, and the second internal clock signal QDQS can be produced into the time point t126 that has postponed 90 degree phase places from time point t125 singularly has predetermined cycle time.
Data alignment device 12 can with the synchronously data DIN of latch serial input sequentially of clock signal of system CLK, with intervening sequences ground generation the 3rd, the 4th, the first and second aligned data ALIGN<3 of the half period at clock signal of system CLK (0.5tCK), 4,1,2>.Can by from time point t123 until from time point t123 through the first data of the time point t127 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t127 until from time point t127 the 5th data through the time point t131 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the 3rd aligned data ALIGN<3>.Can by from time point t124 until from time point t124 through the second data of the time point t128 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t128 until from time point t128 the 6th data through the time point t132 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the 4th aligned data ALIGN<4>.Can by from time point t125 until from time point t125 through the 3rd data of the time point t129 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t129 until from time point t129 the 7th data through the time point t133 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the first aligned data ALIGN<1>.Can by from time point t126 until from time point t126 through the 4th data of the time point t130 latch data DIN in two cycles (2tCK) of clock signal of system CLK and from time point t130 until from time point t130 the 8th data through the time point t134 latch data DIN in two cycles (2tCK) of clock signal of system CLK, produce the second aligned data ALIGN<2>.
Data alignment device 12 can be by a half period (1.5tCK) of the first aligned data ALIGN<1> delay system clock signal clk to produce the 5th aligned data ALIGN<5>, can be by the one-period (1tCK) of the second aligned data ALIGN<2> delay system clock signal clk to produce the 6th aligned data ALIGN<6>, can be by a half period (1.5tCK) of the 3rd aligned data ALIGN<3> delay system clock signal clk to produce the 7th aligned data ALIGN<7>, and can be by the one-period (1tCK) of the 4th aligned data ALIGN<4> delay system clock signal clk to produce the 8th aligned data ALIGN<8>.Result, can by from time point t126 until the first data of time point t130 latch data DIN and from time point t130 until the 5th data of time point t134 latch data DIN produce the 7th aligned data ALIGN<7>, and can by from time point t126 until the second data of time point t130 latch data DIN and from time point t130 until the 6th data of time point t134 latch data DIN produce the 8th aligned data ALIGN<8>.In addition, can by from time point t128 until the 3rd data of time point t132 latch data DIN and from time point t132 until produce the 5th aligned data ALIGN<5> from time point t132 through the 7th data of the time point t135 latch data DIN in two cycles (2tCK) of clock signal of system CLK, and can by from time point t128 until the 4th data of time point t132 latch data DIN and from time point t132 until the 8th data of time point t135 latch data DIN produce the 6th aligned data ALIGN<6>.
Data selector 15 can receive the selection signal SEL with logic " low " level, to export the second aligned data group ALIGN<3,4,7,8> chooses aligned data group ALIGNSEL<1 as first, 2,5,6>, and output the first aligned data group ALIGN<1,2,5,6> chooses aligned data group ALIGNSEL<3,4 as second, 7,8>.
The time point t129 that internal data generator 16 can be inputted with the second pulse of the first data input clock signal DINCLK<1> synchronously latch first chooses aligned data group ALIGNSEL<1,2,5,6>, produce thus the first internal data group IDATA<1,2,5,6>.In addition, the time point t131 that data selector 15 can be inputted with the 3rd pulse of the second data input clock signal DINCLK<2> synchronously latch second chooses aligned data group ALIGNSEL<3,4,7,8>, produces the second internal data group IDATA<3,4 thus, 7,8>.
As mentioned above, according to the deserializer of embodiment can be at internal clock signal normal or abnormal produce in any case all by data alignment, and the data of aligning can be divided into two groups optionally to export parallel aligned data.Therefore, even if producing into singularly, internal clock signal there is anti-phase phase place, and also can be without any aligned data concurrently mistakenly.
The various embodiment of the present invention's design are below disclosed for illustrative object.Those skilled in the art will appreciate that, in the case of not departing from the scope and spirit of the disclosed the present invention's design of claims, can carry out different modifications, increase and replacement.
Can find out by above embodiment, the application provides following technical scheme.
1. 1 kinds of deserializers of technical scheme, comprising:
Data alignment device, described data alignment device be configured in response to mutually have out of phase internal clock signal and by data alignment, to produce high aligned data and low aligned data;
Selective signal generator, the phase place of one that described selective signal generator is configured to detect in response to phase detection signal in described internal clock signal selects signal, described phase detection signal to comprise according to writing command signal and writing the pulse that latent time, signal produced to produce; And
Select output unit, described selection output unit is configured to export in response to described selection signal described high aligned data or described low aligned data as choosing aligned data.
The deserializer of technical scheme 2. as described in technical scheme 1, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals.
The deserializer of technical scheme 3. as described in technical scheme 2, wherein, described data alignment device is correctly aimed at described high aligned data in the time that the phase place of described the 4th internal clock signal is normal at described the first internal clock signal, and in the time that the phase place of described the 4th internal clock signal is anti-phase, correctly aims at described low aligned data at described the first internal clock signal.
The deserializer of technical scheme 4. as described in technical scheme 2, wherein, described the first internal clock signal to described the 4th internal clock signal by data strobe signal and complementary data gating signal frequency division are produced.
The deserializer of technical scheme 5. as described in technical scheme 4, wherein, described the first internal clock signal to described the 4th internal clock signal is produced the twice that generating period is described data strobe signal and described complementary data gating signal.
The deserializer of technical scheme 6. as described in technical scheme 2, wherein, described the first internal clock signal is led over the phase place that described the second internal clock signal 90 is spent, described the second internal clock signal is led over the phase place that described the 3rd internal clock signal 90 is spent, and described the 3rd internal clock signal is led over the phase place that described the 4th internal clock signal 90 is spent.
The deserializer of technical scheme 7. as described in technical scheme 6, wherein, described data alignment device comprises data buffer, described data buffer be configured to described the first internal clock signal to described the 4th internal clock signal synchronously sequentially buffered data to produce the first buffered data to the four buffered datas.
The deserializer of technical scheme 8. as described in technical scheme 7, wherein, described data alignment device be configured to described the second internal clock signal and described the 4th internal clock signal synchronously described in latch the first buffered data to produce the first high aligned data and the 5th high aligned data, be configured to described the 3rd internal clock signal and described the 4th internal clock signal synchronously described in latch the second buffered data to produce the second high aligned data and the 6th high aligned data, be configured to described the 4th internal clock signal synchronously described in latch the 3rd buffered data to produce third high aligned data and the 7th high aligned data, and be configured to described the 4th internal clock signal synchronously described in latch the 4th buffered data to produce the 4th high aligned data and the 8th high aligned data.
The deserializer of technical scheme 9. as described in technical scheme 8, wherein, described data alignment device be configured to described the second internal clock signal and described the 4th internal clock signal synchronously described in latch the 3rd buffered data to produce the first low aligned data and the 5th low aligned data, be configured to described the first internal clock signal and described the second internal clock signal synchronously described in latch the 4th buffered data to produce the second low aligned data and the 6th low aligned data, be configured to described the second internal clock signal synchronously described in latch the first buffered data to produce the 3rd low aligned data and the 7th low aligned data, and be configured to described the second internal clock signal synchronously described in latch the second buffered data to produce the 4th low aligned data and the 8th low aligned data.
The deserializer of technical scheme 10. as described in technical scheme 2, also comprises:
Phase detection signal generator, described phase detection signal generator is configured to produce described phase detection signal, and described phase detection signal comprises according to said write command signal and the said write pulse that latent time, signal produced;
Wherein, " N " that described phase detection signal is lighted the cycle through writing latent time and clock signal in the time that is input to described phase detection signal generator from said write command signal doubly after generation, wherein, " N " represents positive integer.
The deserializer of technical scheme 11. as described in technical scheme 10, wherein, the logic level of described selection signal and described phase detection signal are synchronously determined according to the phase place of described the second internal clock signal.
The deserializer of technical scheme 12. as described in technical scheme 11, wherein, described selection output unit is configured to: in the time that described selection signal has the first logic level, export described high aligned data as the described aligned data of choosing.
The deserializer of technical scheme 13. as described in technical scheme 12, wherein, described selection output unit is configured to: in the time that described selection signal has second logic level different from described the first logic level, export described low aligned data as the described aligned data of choosing.
14. 1 kinds of deserializers of technical scheme, comprising:
Internal clock generator, described internal clock generator is configured to data strobe signal and complementary data gating signal frequency division to produce internal clock signal;
Data alignment device, described data alignment device is configured in response to described internal clock signal data alignment to produce high aligned data and low aligned data;
Phase detection signal generator, described phase detection signal generator is configured to produce phase detection signal, and described phase detection signal comprises according to writing command signal and writing the pulse that latent time, signal produced;
Selective signal generator, the phase place of that described selective signal generator is configured to detect in response to described phase detection signal in described internal clock signal is selected signal to produce; And
Select output unit, described selection output unit is configured to export in response to described selection signal described high aligned data or described low aligned data as choosing aligned data.
The deserializer of technical scheme 15. as described in technical scheme 14, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals.
16. 1 kinds of deserializers of technical scheme, comprising:
Selective signal generator, the phase place of one that described selective signal generator is configured to detect in response to phase detection signal in internal clock signal selects signal, described phase detection signal to comprise according to writing command signal and writing the pulse that latent time, signal produced to produce;
Clock phase controller, the inversion signal that described clock phase controller is configured to export described internal clock signal or described internal clock signal in response to described selection signal is as change over clock signal; And
Data alignment device, described data alignment device is configured in response to described change over clock signal data alignment to produce aligned data.
The deserializer of technical scheme 17. as described in technical scheme 16, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals, described change over clock signal comprises the first change over clock signal to the four change over clock signals.
The deserializer of technical scheme 18. as described in technical scheme 17, wherein, described the first internal clock signal to described the 4th internal clock signal by data strobe signal and complementary data gating signal frequency division are produced.
The deserializer of technical scheme 19. as described in technical scheme 18, wherein, described the first internal clock signal to described the 4th internal clock signal is produced the twice that generating period is described data strobe signal and described complementary data gating signal.
The deserializer of technical scheme 20. as described in technical scheme 18, wherein, described the first internal clock signal is led over the phase place that described the second internal clock signal 90 is spent, described the second internal clock signal is led over the phase place that described the 3rd internal clock signal 90 is spent, and described the 3rd internal clock signal is led over the phase place that described the 4th internal clock signal 90 is spent.
The deserializer of technical scheme 21. as described in technical scheme 20, also comprises:
Phase detection signal generator, described phase detection signal generator is configured to produce described phase detection signal, and described phase detection signal comprises according to said write command signal and the said write pulse that latent time, signal produced;
Wherein, " N " that described phase detection signal is lighted the cycle through writing latent time and clock signal of system in the time that is input to described phase detection signal generator from said write command signal doubly after generation, wherein, " N " represents positive integer.
The deserializer of technical scheme 22. as described in technical scheme 21, wherein, the logic level of described selection signal and described phase detection signal are synchronously determined according to the phase place of described the second internal clock signal.
The deserializer of technical scheme 23. as described in technical scheme 22, wherein, described clock phase controller be configured to export in the time that described selection signal has the first logic level described the first internal clock signal to described the 4th internal clock signal as described the first change over clock signal to described the 4th change over clock signal, and be configured to export in the time that described selection signal has the second logic level different from described the first logic level described the first internal clock signal to the inversion signal of described the 4th internal clocking as described the first change over clock signal to described the 4th change over clock signal.
The deserializer of technical scheme 24. as described in technical scheme 20, wherein, described data alignment device is configured to comprise data buffer, described data buffer and described the first change over clock signal to described the 4th change over clock signal synchronously sequentially buffered data to produce the first buffered data to the four buffered datas.
The deserializer of technical scheme 25. as described in technical scheme 24,
Wherein, described aligned data comprises the first aligned data to the eight aligned data; And
Wherein, described data alignment device and described the second change over clock signal and described the 4th change over clock signal synchronously described in latch the first buffered data to produce the first aligned data and the 5th aligned data, with described the 3rd change over clock signal and described the 4th change over clock signal synchronously described in latch the second buffered data to produce described the second aligned data and described the 6th aligned data, with described the 4th change over clock signal synchronously described in latch the 3rd buffered data to produce described the 3rd aligned data and described the 7th aligned data, and with described the 4th change over clock signal synchronously described in latch the 4th buffered data to produce described the 4th aligned data and described the 8th aligned data.
26. 1 kinds of deserializers of technical scheme, comprising:
Internal clock generator, described internal clock generator is configured to data strobe signal and complementary data gating signal frequency division to produce internal clock signal;
Phase detection signal generator, described phase detection signal generator is configured to produce phase detection signal, and described phase detection signal comprises according to writing command signal and writing the pulse that latent time, signal produced;
Selective signal generator, the phase place of that described selective signal generator is configured to detect in response to described phase detection signal in described internal clock signal is selected signal to produce;
Clock phase controller, the inversion signal that described clock phase controller is configured to export described internal clock signal or described internal clock signal in response to described selection signal is as change over clock signal; And
Data alignment device, described data alignment device is configured in response to described change over clock signal data alignment to produce aligned data.
The deserializer of technical scheme 27. as described in technical scheme 26, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals, described change over clock signal comprises the first change over clock signal to the four change over clock signals.
28. 1 kinds of deserializers of technical scheme, comprising:
Selective signal generator, the phase place of one that described selective signal generator is configured to detect in response to phase detection signal in internal clock signal selects signal, described phase detection signal to comprise according to writing command signal and writing the first pulse producing latent time to produce;
First selector, described first selector is configured to export the first aligned data group in response to described selection signal or the second aligned data group is chosen aligned data group as first; And
Second selector, described second selector is configured to export described the first aligned data group in response to described selection signal or described the second aligned data group is chosen aligned data group as second.
The deserializer of technical scheme 29. as described in technical scheme 28, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals.
The deserializer of technical scheme 30. as described in technical scheme 29, wherein, described the first internal clock signal to described the 4th internal clock signal by data strobe signal and complementary data gating signal frequency division are produced.
The deserializer of technical scheme 31. as described in technical scheme 30, wherein, described the first internal clock signal to described the 4th internal clock signal is produced the twice that generating period is described data strobe signal and described complementary data gating signal.
The deserializer of technical scheme 32. as described in technical scheme 30, wherein, described the first internal clock signal is led over the phase place that described the second internal clock signal 90 is spent, described the second internal clock signal is led over the phase place that described the 3rd internal clock signal 90 is spent, and described the 3rd internal clock signal is led over the phase place that described the 4th internal clock signal 90 is spent.
The deserializer of technical scheme 33. as described in technical scheme 29,
Wherein, described the first aligned data group comprises: the first aligned data, the second aligned data, the 5th aligned data and the 6th aligned data;
Wherein, described the second aligned data group comprises: the 3rd aligned data, the 4th aligned data, the 7th aligned data and the 8th aligned data; And
Wherein, described the first aligned data by with described the first internal clock signal synchronously buffered data produce, described the second aligned data by with described the second internal clock signal synchronously buffered data produce, described the 3rd aligned data by with described the 3rd internal clock signal synchronously buffered data produce, described the 4th aligned data by with described the 4th internal clock signal synchronously buffered data produce, described the 5th aligned data by with described the 3rd internal clock signal and described the 4th internal clock signal synchronously described in latch the first aligned data produce, described the 6th aligned data by with described the 4th internal clock signal synchronously described in latch the second aligned data produce, described the 7th aligned data by with described the first internal clock signal and described the 4th internal clock signal synchronously described in latch the 3rd aligned data produce, described the 8th aligned data by with described the second internal clock signal synchronously described in latch the 4th aligned data produce.
The deserializer of technical scheme 34. as described in technical scheme 33,
Wherein, when lighting from the time of data inputs while sequentially producing described the first internal clock signal to described the 4th internal clock signal, described selection signal has the first logic level; And
Wherein, when lighting from the time of data inputs while sequentially producing described the 3rd internal clock signal, described the 4th internal clock signal, described the first internal clock signal and described the second internal clock signal, described selection signal has the second logic level.
The deserializer of technical scheme 35. as described in technical scheme 34, wherein, described first selector is configured to: in the time that described selection signal has described the first logic level, export described the first aligned data group and choose aligned data group as described first.
The deserializer of technical scheme 36. as described in technical scheme 35, wherein, described second selector is configured to: in the time that described selection signal has described the first logic level, export described the second aligned data group and choose aligned data group as described second.
The deserializer of technical scheme 37. as described in technical scheme 36, wherein, described first selector is configured to: in the time that described selection signal has described the second logic level, export described the second aligned data group and choose aligned data group as described first.
The deserializer of technical scheme 38. as described in technical scheme 37, wherein, described second selector is configured to: in the time that described selection signal has described the second logic level, export described the first aligned data group and choose aligned data group as described second.
The deserializer of technical scheme 39. as described in technical scheme 29, wherein, the first pulse of described phase detection signal produces lighting from the time of said write command signal input through the positive integer in cycle of said write latent time and clock signal of system time point doubly.
The deserializer of technical scheme 40. as described in technical scheme 29, also comprise internal data generator, described internal data generator is configured in response to the first data input clock signal described in latch first and chooses aligned data group to produce the first internal data group, and described the first data input clock signal comprises the second pulse producing latent time according to said write command signal and said write.
The deserializer of technical scheme 41. as described in technical scheme 40, wherein, described internal data generator is configured in response to the second data input clock signal described in latch second and chooses aligned data group to produce the second internal data group, and described the second data input clock signal comprises the 3rd pulse producing latent time according to said write command signal and said write.
The deserializer of technical scheme 42. as described in technical scheme 41, wherein, the second pulse of described the first data input clock signal produces lighting from the time of said write command signal input through the positive integer in cycle of said write latent time and clock signal of system time point doubly.
The deserializer of technical scheme 43. as described in technical scheme 42, wherein, the 3rd pulse of described the second data input clock signal was lighted through the positive integer in cycle of described clock signal of system time point doubly and is produced in the time producing from described the second pulse.
44. 1 kinds of deserializers of technical scheme, comprising:
Phase controller, described phase controller is configured to produce phase detection signal, the first data input clock signal and the second data input clock signal, and described phase detection signal, described the first data input clock signal and described the second data input clock signal comprise according to writing command signal and writing the corresponding pulses in the first pulse, the second pulse and the 3rd pulse producing latent time;
Data selector, described data selector is configured to: export the first aligned data group or the second aligned data group is chosen aligned data group as first in response to selecting signal, and export described the first aligned data group in response to described selection signal or described the second aligned data group is chosen aligned data group as second, described selection signal is that the phase place of by detecting in response to described phase detection signal in the first internal clock signal to the four internal clock signals produces; And
Internal data generator, described internal data generator is configured to: described in latch, first choose aligned data group to produce the first internal data group in response to described the first data input clock signal, and described in latch, second choose aligned data group to produce the second internal data group in response to described the second data input clock signal.
45. 1 kinds of methods of unstringing of technical scheme, comprise the following steps:
In response to mutually have out of phase internal clock signal and by data alignment, for producing high aligned data and low aligned data;
The phase place of one detecting in response to phase detection signal in the first internal clock signal to the four internal clock signals selects signal, described phase detection signal to comprise according to writing command signal and writing the pulse that latent time, signal produced to produce; And
Export described high aligned data or described low aligned data in response to described selection signal as choosing aligned data.
The method of technical scheme 46. as described in technical scheme 45, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals.
The method of technical scheme 47. as described in technical scheme 46, further comprising the steps of:
When described the first internal clock signal to the phase place of described the 4th internal clock signal is while being normal, aim at described high aligned data; And
When described the first internal clock signal to the phase place of described the 4th internal clock signal is while being anti-phase, aim at described low aligned data.
The method of technical scheme 48. as described in technical scheme 46, wherein, by data strobe signal and complementary data gating signal frequency division are produced to described the first internal clock signal to described the 4th internal clock signal.
The method of technical scheme 49. as described in technical scheme 48, wherein, described the first internal clock signal to described the 4th internal clock signal is produced the twice that generating period is described data strobe signal and described complementary data gating signal.
The method of technical scheme 50. as described in technical scheme 46, wherein, described the first internal clock signal is led over the phase place that described the second internal clock signal 90 is spent, described the second internal clock signal is led over the phase place that described the 3rd internal clock signal 90 is spent, and described the 3rd internal clock signal is led over the phase place that described the 4th internal clock signal 90 is spent.
The method of technical scheme 51. as described in technical scheme 50, further comprising the steps of:
With described the first internal clock signal to synchronously buffered data sequentially of described the 4th internal clock signal, for producing the first buffered data to the four buffered datas.
The method of technical scheme 52. as described in technical scheme 51, further comprising the steps of:
With synchronously the first buffered data described in latch of described the second internal clock signal and described the 4th internal clock signal, for producing the first high aligned data and the 5th high aligned data;
With synchronously the second buffered data described in latch of described the 3rd internal clock signal and described the 4th internal clock signal, for producing the second high aligned data and the 6th high aligned data;
With synchronously the 3rd buffered data described in latch of described the 4th internal clock signal, for producing third high aligned data and the 7th high aligned data; And
With synchronously the 4th buffered data described in latch of described the 4th internal clock signal, for producing the 4th high aligned data and the 8th high aligned data.
The method of technical scheme 53. as described in technical scheme 52, further comprising the steps of:
With synchronously the 3rd buffered data described in latch of described the second internal clock signal and described the 4th internal clock signal, for producing the first low aligned data and the 5th low aligned data;
With synchronously the 4th buffered data described in latch of described the first internal clock signal and described the second internal clock signal, for producing the second low aligned data and the 6th low aligned data;
With synchronously the first buffered data described in latch of described the second internal clock signal, for producing the 3rd low aligned data and the 7th low aligned data; And
With synchronously the second buffered data described in latch of described the second internal clock signal, for producing the 4th low aligned data and the 8th low aligned data.
The method of technical scheme 54. as described in technical scheme 46, further comprising the steps of:
Produce described phase detection signal via phase detection signal generator, described phase detection signal comprises according to said write command signal and the said write pulse that latent time, signal produced;
Wherein, " N " that described phase detection signal is lighted the cycle through writing latent time and clock signal in the time that is input to described phase detection signal generator from said write command signal doubly after generation, wherein, " N " represents positive integer.
The method of technical scheme 55. as described in technical scheme 54, further comprising the steps of:
Synchronously determine the logic level of described selection signal according to the phase place of described the second internal clock signal with described phase detection signal.
The method of technical scheme 56. as described in technical scheme 55, further comprising the steps of:
In the time that described selection signal has the first logic level, export described high aligned data as the described aligned data of choosing.
The method of technical scheme 57. as described in technical scheme 56, further comprising the steps of:
In the time that described selection signal has second logic level different from described the first logic level, export described low aligned data as the described aligned data of choosing.

Claims (10)

1. a deserializer, comprising:
Data alignment device, described data alignment device be configured in response to mutually have out of phase internal clock signal and by data alignment, to produce high aligned data and low aligned data;
Selective signal generator, the phase place of one that described selective signal generator is configured to detect in response to phase detection signal in described internal clock signal selects signal, described phase detection signal to comprise according to writing command signal and writing the pulse that latent time, signal produced to produce; And
Select output unit, described selection output unit is configured to export in response to described selection signal described high aligned data or described low aligned data as choosing aligned data.
2. deserializer as claimed in claim 1, wherein, described internal clock signal comprises the first internal clock signal to the four internal clock signals.
3. deserializer as claimed in claim 2, wherein, described data alignment device is correctly aimed at described high aligned data in the time that the phase place of described the 4th internal clock signal is normal at described the first internal clock signal, and in the time that the phase place of described the 4th internal clock signal is anti-phase, correctly aims at described low aligned data at described the first internal clock signal.
4. deserializer as claimed in claim 2, wherein, described the first internal clock signal to described the 4th internal clock signal by data strobe signal and complementary data gating signal frequency division are produced.
5. deserializer as claimed in claim 4, wherein, described the first internal clock signal to described the 4th internal clock signal is produced the twice that generating period is described data strobe signal and described complementary data gating signal.
6. deserializer as claimed in claim 2, wherein, described the first internal clock signal is led over the phase place that described the second internal clock signal 90 is spent, described the second internal clock signal is led over the phase place that described the 3rd internal clock signal 90 is spent, and described the 3rd internal clock signal is led over the phase place that described the 4th internal clock signal 90 is spent.
7. deserializer as claimed in claim 6, wherein, described data alignment device comprises data buffer, described data buffer be configured to described the first internal clock signal to described the 4th internal clock signal synchronously sequentially buffered data to produce the first buffered data to the four buffered datas.
8. deserializer as claimed in claim 7, wherein, described data alignment device be configured to described the second internal clock signal and described the 4th internal clock signal synchronously described in latch the first buffered data to produce the first high aligned data and the 5th high aligned data, be configured to described the 3rd internal clock signal and described the 4th internal clock signal synchronously described in latch the second buffered data to produce the second high aligned data and the 6th high aligned data, be configured to described the 4th internal clock signal synchronously described in latch the 3rd buffered data to produce third high aligned data and the 7th high aligned data, and be configured to described the 4th internal clock signal synchronously described in latch the 4th buffered data to produce the 4th high aligned data and the 8th high aligned data.
9. deserializer as claimed in claim 8, wherein, described data alignment device be configured to described the second internal clock signal and described the 4th internal clock signal synchronously described in latch the 3rd buffered data to produce the first low aligned data and the 5th low aligned data, be configured to described the first internal clock signal and described the second internal clock signal synchronously described in latch the 4th buffered data to produce the second low aligned data and the 6th low aligned data, be configured to described the second internal clock signal synchronously described in latch the first buffered data to produce the 3rd low aligned data and the 7th low aligned data, and be configured to described the second internal clock signal synchronously described in latch the second buffered data to produce the 4th low aligned data and the 8th low aligned data.
10. deserializer as claimed in claim 2, also comprises:
Phase detection signal generator, described phase detection signal generator is configured to produce described phase detection signal, and described phase detection signal comprises according to said write command signal and the said write pulse that latent time, signal produced;
Wherein, " N " that described phase detection signal is lighted the cycle through writing latent time and clock signal in the time that is input to described phase detection signal generator from said write command signal doubly after generation, wherein, " N " represents positive integer.
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US20140340247A1 (en) 2014-11-20

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