CN103780258B - Digital double-line delay phase lock loop - Google Patents
Digital double-line delay phase lock loop Download PDFInfo
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- CN103780258B CN103780258B CN201410043906.1A CN201410043906A CN103780258B CN 103780258 B CN103780258 B CN 103780258B CN 201410043906 A CN201410043906 A CN 201410043906A CN 103780258 B CN103780258 B CN 103780258B
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Abstract
The invention discloses a digital double-line delay phase lock loop which comprises a delay cell remainder line, a phase detector, a locking control cell and two delay lines. The two delay lines include the delay line composed of a plurality of delay cells and the compensation line composed of a plurality of compensation delay cells, and the delay cells include the rough adjustment line delay cells and the fine adjustment line delay cells, wherein the rough adjustment line delay cells and the fine adjustment line delay cells are arranged in a stagger and reversal mode. A reference clock sequentially passes through the rough adjustment line delay cells and the fine adjustment line delay cells, the rough adjustment line delay cells are used for inputting the reference clock, and the fine adjustment line delay cells are used for outputting the reference clock; meanwhile, the reference clock passes through the compensation delay cells of the compensation line, the phase detector compares a clock output by the compensation line with the reference clock and outputs the phase detecting result, the output clock is adjusted by the locking control cell according to the phase detecting result, if the output clock is ahead of the reference clock, the delay time is prolonged, and the output clock is delayed, the reverse is also true till the phase detector detects that the two clock signals are synchronous, and system locking is carried out.
Description
Technical field
The present invention relates to DLL, more particularly to a kind of digital double-strand delay phase-locked loop.
Background technology
DLL is the abbreviation of Delay Lock Loop, and the effect of DLL is the phase place for adjusting a clock signal, is usually used in place
The clock synchronization of reason device memorizer.
For single-stranded DLL, reference clock is connected on the input of all delay cells simultaneously, and phase discriminator is to reference clock and instead
The phase place of feedback clock is compared, if feedback clock is faster than reference clock, control shift register is moved to left, and time delay adds
Greatly, until reference clock and feedback clock synchronization, vice versa.Have the disadvantage that locking time is long, precision is low.
For simulation DLL, phase discriminator comparison reference clock and feedback clock phase place, according to phase contrast produce control signal come
The electric current of control charge pump is to filter capacity charge or discharge, the high frequency letter that phase discriminator and charge pump are produced by low pass filter
Number filter, generate control voltage, the time delay of voltage controlled delay line is adjusted so as to change feedback clock by changing the magnitude of voltage
Phase place.Have the disadvantage that power consumption is big, speed is slow.
At a high speed, in the communication system of parallel chip chamber, in order to realize the clock synchronization of each interchannel, and complete reliability
Data sampling, urgent demand is proposed to high speed Orthogonal clock generation system.And in order to coordinate different communication protocol
Require, it is desirable to provide the range of application of support and the orthogonal clock generation system that can be extended to different frequency.
The content of the invention
In order to solve above-mentioned technical problem, object of the present invention is to provide digital double-strand delay phase-locked loop, using height
Fast quadrature clock systems, it is ensured that the requirements for high precision of orthogonal clock, disclosure satisfy that high speed, the requirement of wide range of frequencies locking, right
Technique, voltage, the change of temperature have very strong adaptability and reliability.
Specifically, the invention discloses a kind of digital double-strand delay phase-locked loop, the digital double-strand delay phase-locked loop includes
Delay cell remainder chain, phase discriminator, locking control unit and two delay chains, wherein, two delay chains include being prolonged by multiple
The compensated chain that the delay chain and Multilevel compensating delay cell of unit composition is constituted late, delay cell include staggeredly overturning the thick of setting
Adjust chain delay cell and fine tuning chain delay cell；
Reference clock successively prolongs through coarse adjustment chain delay cell and fine tuning chain from first delay cell input of delay chain
Slow unit, subsequently into next delay cell, the input of coarse adjustment chain delay cell, fine tuning chain delay cell output, through postponing
Select into phase discriminator or phase discriminator is entered by delay cell remainder chain, meanwhile, multistage benefit of the reference clock through compensated chain
Delay cell is repaid, phase discriminator is entered through delay compensation, compensated chain output clock is compared with reference clock by phase discriminator,
Output identified result, according to the identified result by control unit adjustment output clock is locked, if output clock leads over reference
Clock, then be increased time delay, and output clock is postponed, and vice versa, until phase discriminator identifies two clock signal synchronizations,
System lock.
The multiple delay cells of two delay chains and Multilevel compensating delay cell are placed equidistant, to obtain preferable dutycycle.
The data wire that coarse adjustment chain delay cell and fine tuning chain delay cell are exported respectively is Bus structures.
Delay cell in delay cell remainder chain is identical with coarse adjustment chain delay cell structure.
Reference clock is a pair of differential clocks.
The metal routing length of differential clock signal is the same.
The difference of output clock and reference clock is locked in less than in the range of half clock cycle.
A kind of digital double-strand postpones phase-lock technique, comprises the steps：
1）Two delay chains are set, are constituted including the delay chain and Multilevel compensating delay cell being made up of multiple delay cells
Compensated chain；
2）The coarse adjustment chain delay cell and fine tuning chain delay cell that each delay cell is set is overturned staggeredly；
3）First delay cell input of the reference clock from delay chain, successively through coarse adjustment chain delay cell and fine tuning chain
Delay cell, subsequently into next delay cell, the input of coarse adjustment chain delay cell, the output of fine tuning chain delay cell, Jing Guoyan
Select into phase discriminator late or phase discriminator is entered by delay cell remainder chain, meanwhile, reference clock is through the multistage of compensated chain
Compensation delay cell, enters phase discriminator through delay compensation, compares compensated chain output clock with reference clock by phase discriminator
Compared with output identified result；
4）According to the identified result by control unit adjustment output clock is locked, if output clock is led over when referring to
Clock, then be increased time delay, and output clock is postponed, and vice versa, until phase discriminator identifies two clock signal synchronizations, is
System locking.
A kind of processor or memorizer and clock synchronizer part using above-mentioned DDL.
The technique effect of the present invention：
The synchronization walked circuit Jing, keep two signals mainly for differential clocks CKN/CKP, although prolong through different
Unit, still can obtain preferable synchronous effect late
Description of the drawings
Fig. 1 present invention numeral double-strand delay phase-locked loop block diagrams；
The single-stranded circuit diagram of Fig. 2 coarse adjustment chain delay cells of the present invention；
Fig. 3 coarse adjustment chain delay cell difference channel figures of the present invention.
Wherein, reference
1 is locking control unit；
2 is phase discriminator；
3 is the delayed selection culture；
4 is delay compensation；
5 is delay cell remainder chain；
6 are compensation delay cell；
7 is coarse adjustment chain delay cell；
8 is fine tuning chain delay cell.
Specific embodiment
The digital double-strand delay phase-locked loop DLL of the present invention, referring to Fig. 1, main functional unit includes：Compensation delay cell
6（DelayLine）, coarse adjustment chain delay cell 7（Delaycell CT）, fine tuning chain delay cell 8（Delaycell FT）, phase demodulation
Device 2（PhaseDetect）, delay compensation 4, the delayed selection culture 3, delay cell remainder chain 5 and locking control unit 1
（LockControl）.
Two delay chains include the compensation that the delay chain being made up of multiple delay cells and Multilevel compensating delay cell 6 are constituted
Chain, delay cell adopt duplex structure, including coarse adjustment chain delay cell 7（Delaycell CT）With fine tuning chain delay cell 8
（Delaycell FT）.The benefit of this duplex structure can be to reduce locking time and reduce static phase error.During locking
Between be the key parameter for evaluating DLL design quality.
In order to realize that orthogonal clock is produced, identical 4 delay cell is designed with, 4 delay cells are adopted
The precision of identical coarse adjustment code and the control of fine tuning code, coarse adjustment and fine tuning is 4 times of wall scroll delay chain.
Reference clock CKP/CKN（A pair of differential clocks）, inputs of the CKP/CKN from first delay cell Delaycell,
Successively through coarse adjustment chain delay cell 7（Delaycell CT）With fine tuning chain delay cell 8（Delaycell FT）, subsequently into
Next stage postpones, coarse adjustment chain delay cell 7（Delaycell CT）Enter, fine tuning chain delay cell 8（Delaycell FT）Go out, slightly
Adjust chain delay cell 7（Delaycell CT）Can step-length greatly the digital double-strand delay phase-locked loop DLL of realization itself fast lock
It is fixed, after digital double-strand delay phase-locked loop DLL quick lock ins, by coarse adjustment chain delay cell 7（Delaycell CT）Regulation code
Fallback mechanism and fine tuning chain delay cell 8（Delaycell FT）Fine-tune and realize digital double-strand delay phase-locked loop DLL's
High accuracy is locked again, so as to meet broadband quick lock in and high-precision characteristic.Referring to Fig. 1, coarse adjustment chain delay cell 7
（DelaycellCT）With fine tuning chain delay cell 8（DelaycellFT）Staggeredly it is placed upside down, so arranging first benefit is
CKP/CKN postpones to export from afterbody via identical path completely, and second benefit is differential clocks edge on delay chain
Shortest path is directly entered next stage delay, the 3rd benefit be advantageous for keeping it is not at the same level between equidistant requirement.
In addition, coarse adjustment chain delay cell 7（Delaycell CT）/ fine tuning chain delay cell 8（Delaycell FT）Also divide
8 position datawires are not outputed, due to coarse adjustment chain delay cell 7（Delaycell CT）/ fine tuning chain delay cell 8（Delaycell
FT）It is placed upside down, therefore, by the horizontal main data line connection being placed between unit, the wire laying mode during data output
For the structure of a Bus.
It should be noted that this delay chain path, principle of equidistance, i.e. delay chain are all followed strictly between per grade equidistant
Place, to obtain preferable dutycycle.In order to ensure delay cell Delaycell phase contrast at different levels for 90 degree, delays at different levels
Structure is needed unanimously, and cabling is needed uniformly, keeps differential signal path consistent.
At the same time, the reference clock CKP/CKN of input also through other one by compensation delay cell 6
（DelayLine）The compensated chain of composition, reaches the outfan of this delay chain.This is to compensate for intrinsic delay when high frequency is used
（The delay of delay cell when i.e. coarse adjustment code and fine tuning code are 0）Impact, specially designed 4 grades of compensated chains.
CKP/CKN（Differential clocks）Respectively from after the output of above-mentioned two delay chains, reference clock CKP5/CKN5 is through postponing
Compensation 4 enters phase discriminator 2, and is directly entered phase discriminator 2 through the delayed selection culture 3 by comparison clock CKP4/CKN4, or by postponing
Unit remainder chain 5 enters phase discriminator 2.
In this process, between a pair of differential signals, track lengths need to keep highly consistent, illustrate, and compensation postpones
Unit 6（DelayLine）Output signal output to delay compensation 4 when, due to CKP to delay compensation 4 than CKN closer to, therefore
In layout design, the cabling of CKP need to be deliberately elongated, to ensure the matching of two differential lines.
In order that phase error is more accurate, after coarse adjustment completes locking, a lock detecting signal is set to height, essence by low
The fine-tuning process of Du Genggao starts, and until system is finally locked, the difference for exporting clock and reference clock is locked in less than half
In the range of clock cycle, i.e., the error of output clock and reference clock is less than the dead band of phase discriminator 2.
In order to solve, under conditions of precision and lock speed is ensured, to meet the PGC demodulation of better frequency, in fine tuning chain
Delay cell 8（Delaycell FT）Afterwards, using 5 structure of delay cell remainder chain.Delay list in delay cell remainder chain 5
Unit adopts and coarse adjustment chain delay cell 7（Delaycell CT）Identical structure.
After coarse tuning process, delay cell remainder chain 5 realizes 1,2,3,4 grades of coarse adjustment chains under the control of remainder regulation code
Delay cell 7（Delaycell CT）Delay adjust, when delay cell remainder chain 5 delay to reach 4 grades of coarse adjustment chains postpone it is single
Unit 7（Delaycell CT）When, carry while delay cell remainder chain 5 resets increases a coarse adjustment code CT, so ensures
With a coarse adjustment chain delay cell 7 in whole coarse tuning process（Delaycell CT）Precision continuously adjust, when reaching coarse adjustment
During locking, the delay of delay cell remainder chain 5 is bypassed using the delayed selection culture 3, and the delayed selection culture 3 itself is compensated in clock phase discrimination
Delay.
In ensuing two unit phase discriminators 2（PD）With locking control unit 1（LockControl）, differential signal is still
Symmetry is kept, until differential clocks enter locking control unit 1（LockControl）.
Reference clock compensates delay cell 6 through 4 grades（Delayline）Afterwards, will compensation delay cell 6 by phase discriminator 2
（Delayline）Output clock make comparisons with reference clock, lock control unit 1（LockControl）According to identified result
Adjustment output clock, if output clock leads over reference clock, is increased time delay, and output clock is postponed, otherwise
It is as the same, until phase discriminator 2 identifies two signal synchronizations, system lock.
The single-stranded circuit diagram of Fig. 2 coarse adjustment chain delay cells of the present invention；Fig. 3 coarse adjustment chain delay cell difference channel figures of the present invention.
To sum up, a kind of digital double-strand delay phase-locked loop, the digital double-strand delay phase-locked loop include delay cell remainder chain 5,
Phase discriminator 2, locking control unit 1 and two delay chains, wherein, two delay chains are included by prolonging that multiple delay cells are constituted
Slow chain and Multilevel compensating delay cell 6（Delayline）The compensated chain of composition, delay cell include the coarse adjustment for staggeredly overturning setting
Chain delay cell 7（Delaycell CT）With fine tuning chain delay cell 8（Delaycell FT）；
First delay cell input of the reference clock from delay chain, successively through coarse adjustment chain delay cell 7
（Delaycell CT）With fine tuning chain delay cell 8（Delaycell FT）, subsequently into next delay cell, coarse adjustment chain prolongs
Slow unit 7（Delaycell CT）Input, fine tuning chain delay cell 8（Delaycell FT）Output, enters through the delayed selection culture 3
Phase discriminator 2 enters phase discriminator 2 by delay cell remainder chain 5, meanwhile, reference clock postpones through the Multilevel compensating of compensated chain
Unit 6（Delayline）, phase discriminator 2 is entered through delay compensation 4, compensated chain is exported into clock and reference clock by phase discriminator 2
It is compared, exports identified result, according to the identified result by locking control unit 1（LockControl）Adjustment output clock,
If output clock leads over reference clock, it is increased time delay, output clock is postponed, and vice versa, until phase demodulation
Device 2 identifies two clock signal synchronizations, system lock.
The multiple delay cells of two delay chains and Multilevel compensating delay cell 6（Delayline）It is placed equidistant, to be managed
The dutycycle thought.
Coarse adjustment chain delay cell 7（Delaycell CT）With fine tuning chain delay cell 8（Delaycell FT）Export respectively
Data wire be Bus structures.
Delay cell in delay cell remainder chain 5 and coarse adjustment chain delay cell 7（Delaycell CT）Structure is identical.
Reference clock is a pair of differential clocks.The metal routing length of differential clock signal is the same.
The difference of output clock and reference clock is locked in less than in the range of half clock cycle.
Invention additionally discloses a kind of digital double-strand postpones phase-lock technique, comprise the steps：
1）Two delay chains are set, including the delay chain and Multilevel compensating delay cell 6 that are made up of multiple delay cells
（Delayline）The compensated chain of composition；
2）The coarse adjustment chain delay cell 7 that each delay cell is set is overturned staggeredly（Delaycell CT）Prolong with fine tuning chain
Slow unit 8（Delaycell FT）；
3）First delay cell input of the reference clock from delay chain, successively through coarse adjustment chain delay cell 7
（Delaycell CT）With fine tuning chain delay cell 8（Delaycell FT）, subsequently into next delay cell, coarse adjustment chain prolongs
Slow unit 7（Delaycell CT）Input, fine tuning chain delay cell 8（Delaycell FT）Output, enters through the delayed selection culture 3
Phase discriminator 2 enters phase discriminator 2 by delay cell remainder chain 5, meanwhile, reference clock postpones through the Multilevel compensating of compensated chain
Unit 6（Delayline）, phase discriminator 2 is entered through delay compensation 4, compensated chain is exported into clock and reference clock by phase discriminator 2
It is compared, exports identified result；
4）According to the identified result by locking control unit 1（LockControl）Adjustment output clock, if output clock
Reference clock is led over, is then increased time delay, output clock is postponed, and vice versa, when phase discriminator 2 identifies two
Clock signal synchronization, system lock.
Using the processor or memorizer or clock synchronizer part of above-mentioned DDL.
Claims (9)
1. a kind of digital double-strand delay phase-locked loop, it is characterised in that the digital double-strand delay phase-locked loop includes delay cell remainder
Chain, phase discriminator, locking control unit and two delay chains, wherein, two delay chains include what is be made up of multiple delay cells
The compensated chain of delay chain and Multilevel compensating delay cell composition, delay cell include the coarse adjustment chain delay cell for staggeredly overturning setting
With fine tuning chain delay cell；
First delay cell input of the reference clock from delay chain, successively postpones through coarse adjustment chain delay cell and fine tuning chain single
Unit, subsequently into next delay cell, the input of coarse adjustment chain delay cell, fine tuning chain delay cell output, through the delayed selection culture
Phase discriminator is entered into phase discriminator or by delay cell remainder chain, meanwhile, reference clock prolongs through the Multilevel compensating of compensated chain
Unit, enters phase discriminator through delay compensation late, compensated chain output clock is compared with reference clock by phase discriminator, is exported
Identified result, according to the identified result by control unit adjustment output clock is locked, if output clock leads over reference clock,
Then it is increased time delay, output clock is postponed, and vice versa, until phase discriminator identifies two clock signal synchronizations, system
Locking, wherein the reference clock is a pair of differential clocks, respectively differential clocks CKP and differential clocks CKN, by the difference
Clock CKP is elongated, to ensure which is matched with the differential clocks CKN.
2. as claimed in claim 1 numeral double-strand delay phase-locked loop, it is characterised in that multiple delay cells of two delay chains and many
Level compensation delay cell is placed equidistant, to obtain preferable dutycycle.
3. as claimed in claim 1 numeral double-strand delay phase-locked loop, it is characterised in that coarse adjustment chain delay cell and fine tuning chain postpone
The data wire that unit is exported respectively is Bus structures.
4. as claimed in claim 1 numeral double-strand delay phase-locked loop, it is characterised in that the delay cell in delay cell remainder chain
It is identical with coarse adjustment chain delay cell structure.
5. as claimed in claim 1 numeral double-strand delay phase-locked loop, it is characterised in that the metal routing length of differential clock signal
Equally.
6. as claimed in claim 1 numeral double-strand delay phase-locked loop, it is characterised in that the difference locking of output clock and reference clock
In the range of less than half clock cycle.
7. a kind of digital double-strand postpones phase-lock technique, it is characterised in that comprise the steps：
1) two delay chains are set, including the benefit that the delay chain and Multilevel compensating delay cell being made up of multiple delay cells is constituted
Repay chain；
2) staggeredly overturn the coarse adjustment chain delay cell and fine tuning chain delay cell that each delay cell is set；
3) reference clock successively postpones through coarse adjustment chain delay cell and fine tuning chain from first delay cell input of delay chain
Unit, subsequently into next delay cell, the input of coarse adjustment chain delay cell, fine tuning chain delay cell output, through postponing choosing
Select into phase discriminator or phase discriminator is entered by delay cell remainder chain, meanwhile, Multilevel compensating of the reference clock through compensated chain
Delay cell, enters phase discriminator through delay compensation, compensated chain output clock is compared with reference clock by phase discriminator, defeated
Go out identified result, wherein the reference clock is a pair of differential clocks, respectively differential clocks CKP and differential clocks CKN, by institute
Differential clocks CKP elongations are stated, to ensure which is matched with the differential clocks CKN；
4) according to the identified result by control unit adjustment output clock is locked, if output clock leads over reference clock,
Time delay is increased, and output clock is postponed, and vice versa, until phase discriminator identifies two clock signal synchronizations, system lock
It is fixed.
8. the processor or memorizer of digital double-strand delay phase-locked loop described in a kind of employing claim 1-6 any one.
9. the clock synchronizer part of digital double-strand delay phase-locked loop described in a kind of employing claim 1-6 any one.
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| CN201410043906.1A CN103780258B (en) | 2013-06-28 | 2014-01-29 | Digital double-line delay phase lock loop |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105322923B (en) * | 2014-05-29 | 2018-09-11 | 上海兆芯集成电路有限公司 | Delay line and semiconductor integrated circuit |
| CN108551342B (en) * | 2018-03-20 | 2022-04-01 | 上海集成电路研发中心有限公司 | Delay phase-locked loop with wide frequency input range |
| CN109933127A (en) * | 2019-03-07 | 2019-06-25 | 中科亿海微电子科技（苏州）有限公司 | Programmable delay cellular construction |
| CN112260686B (en) * | 2020-10-27 | 2023-11-10 | 西安芯辉光电科技有限公司 | Low-locking-error delay chain phase-locked loop |
| CN113835332B (en) * | 2021-09-29 | 2022-08-23 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
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| EP1179821A1 (en) * | 1996-04-30 | 2002-02-13 | Mitsumi Electric Co., Ltd. | Servo circuit |
| CN1731681A (en) * | 2005-08-12 | 2006-02-08 | 北京大学 | Double-loop frequency synthesizer and method for tuning coarse loop |
| CN101951260A (en) * | 2010-10-11 | 2011-01-19 | 上海电力学院 | Digital delay phase locked loop circuit |
| CN102664623A (en) * | 2012-05-09 | 2012-09-12 | 龙芯中科技术有限公司 | Digital delay device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1179821A1 (en) * | 1996-04-30 | 2002-02-13 | Mitsumi Electric Co., Ltd. | Servo circuit |
| CN1731681A (en) * | 2005-08-12 | 2006-02-08 | 北京大学 | Double-loop frequency synthesizer and method for tuning coarse loop |
| CN101951260A (en) * | 2010-10-11 | 2011-01-19 | 上海电力学院 | Digital delay phase locked loop circuit |
| CN102664623A (en) * | 2012-05-09 | 2012-09-12 | 龙芯中科技术有限公司 | Digital delay device |
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