CN112511158A

CN112511158A - Output delay line and delay-locked loop

Info

Publication number: CN112511158A
Application number: CN202011460683.0A
Authority: CN
Inventors: 杨雪; 刘飞; 霍宗亮; 叶甜春
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2021-03-16
Anticipated expiration: 2040-12-11
Also published as: CN112511158B

Abstract

The application discloses an output delay line and a delay phase-locked loop, the output delay line is composed of a plurality of delay blocks, each delay block comprises a configurable coarse adjustment delay line and a configurable fine adjustment delay line, the coarse adjustment delay line and the fine adjustment delay line select unit delay according to configuration selection signals, so that delay time parameters are matched with the configuration selection signals, the purpose of meeting the delay time of the delay phase-locked loop required under different frequency bands is achieved, and all time modes defined by an ONFI 4.2 international protocol can be supported. In addition, the delay locked loop based on the output delay line has good expandability, can meet all time sequence mode requirements specified in the current ONFI 4.2 international protocol, can also cover a wider frequency range, and meets the future development requirements. Furthermore, the output delay line provided by the embodiment of the application does not need to change other structures, and the problem of long delay chains caused by a large frequency locking range is effectively solved.

Description

Output delay line and delay-locked loop

Technical Field

The present invention relates to the field of signal processing technologies, and in particular, to an output delay line and a delay locked loop.

Background

A Delay-locked loop (DLL) is a clock generation and synchronization circuit that generates a multiphase clock output, and referring to fig. 1, fig. 1 shows a four-phase output clock signal generated by a DLL with phases of-90 °, +90 °, -180 °, and +180 °, respectively.

Delay locked loops are commonly used in NAND Flash controllers to provide multiphase clock signals to the NAND Flash controllers.

In the international standard ONFI (Open NAND Flash Interface) 4.2 published in 2020, all time modes Mode 0-Mode 15 of NAND Flash are specified, and the locking range of the delay locked loop must cover all time modes of NAND Flash operation specified by the ONFI protocol, so according to the design requirements of the international standard ONFI 4.2, the design requirements of the delay locked loop need to be satisfied: the locking range must cover the frequency range of 33 MHz-800 MHz, and the frequency range of the existing delay locked loop design which can work is far different from the frequency range of 33 MHz-800 MHz, so that the requirement of the frequency range specified by ONFI 4.2 cannot be met.

Disclosure of Invention

In order to solve the above technical problem, the present application provides an output delay line and a delay locked loop, which adjust a delay time parameter of a single coarse tuning delay unit and a delay time parameter of a single fine tuning delay unit in a configurable coarse tuning delay line and a configurable fine tuning delay line, so as to achieve the purpose that the functional frequency range of the delay locked loop covers 33MHz to 800MHz by adjusting the total delay time of the output delay line on the premise of keeping other circuits unchanged.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

an output delay line for a delay locked loop, the output delay line comprising: a plurality of delay blocks, each of the delay blocks comprising a coarse delay line and a fine delay line connected in series, wherein,

the coarse delay line comprises a plurality of stages of coarse delay units, each coarse delay unit comprises a plurality of stages of coarse configuration delay units, and each coarse delay unit is used for receiving a configuration selection signal and adjusting the stage number of the coarse configuration delay unit connected to a loop according to the configuration selection signal so as to adjust the delay of the coarse delay unit and enable the delay time parameter of the coarse delay line to be matched with the configuration selection signal;

the fine delay line comprises a plurality of stages of fine delay units, each fine delay unit comprises a plurality of stages of fine configuration delay units, and each fine delay unit is used for receiving the configuration selection signal and adjusting the stage number of the fine configuration delay unit of the access loop according to the configuration selection signal, so that the delay of the fine delay unit is adjusted, and the delay time parameter of the fine delay line is matched with the configuration selection signal.

Optionally, the coarse delay unit includes: the delay circuit comprises a first delay branch, a second delay branch and a first selector;

the first delay branch comprises a plurality of first switches and the multi-stage coarse configuration delay units, and when each first switch is conducted, the first delay branch is used for short-circuiting different numbers of the coarse configuration delay units;

the second delay branch comprises a second switch;

the first delay branch and the second delay branch are connected in parallel to form a first parameter adjusting structure, one end of the first parameter adjusting structure is used for receiving an input signal, and the other end of the first parameter adjusting structure is connected with the first selector;

the configuration selection signal is determined according to the frequency of a clock signal input into the delay locked loop, and when the frequency of the clock signal is smaller than a first preset value, the configuration selection signal is a first type control signal, and the first type control signal corresponds to the frequency band to which the clock signal belongs; when the frequency of the clock signal is greater than or equal to the first preset value, the configuration selection signal is a second type control signal;

the second type of control signal is used for controlling the first selector to connect the second delay branch into the loop and controlling the second switch to be conducted, so that the second delay branch short-circuits the first delay branch and the delay time parameter of the coarse delay line is minimized;

the first type of control signal is used for controlling the first selector to connect the first delay branch into the loop, and is used for controlling the second switch corresponding to the first type of control signal to be conducted, so that the delay time parameter of the coarse delay line is matched with the configuration selection signal.

Optionally, the multi-stage coarse configuration delay units are sequentially connected in series;

the first ends of the first switches are connected with the output end of the first delay branch circuit;

and the second end of each first switch is respectively connected with the connection nodes of every two coarse configuration delay units.

Optionally, the coarse configuration delay unit includes two inverters connected in series.

Optionally, the coarse configuration delay unit includes two inverters and two capacitors;

the two phase inverters are sequentially connected in series, the first ends of the two capacitors are respectively connected with the output ends of the two phase inverters, and the second ends of the two capacitors are grounded.

Optionally, the coarse delay unit further includes: a first logic structure, a second logic structure, a third logic structure, and a fourth logic structure; wherein the content of the first and second substances,

the first input ends of the first logic structure and the second logic structure are connected with the output end of the first selector;

a second input end of the first logic structure is used for receiving a first coarse tuning control code, and an output end of the first logic structure is used as an output end of the coarse tuning delay line pair of the next stage coarse tuning delay line;

a second input end of the second logic structure is used for receiving a second coarse tuning control code, the first coarse tuning control code and the second coarse tuning control code are in opposite phases, and an output end of the second logic structure is connected with first input ends of the third logic structure and the fourth logic structure;

a second input end of the third logic structure is connected with a second input end of the fourth logic structure and serves as an input end of the coarse tuning delay line for receiving an output signal of a next-stage coarse tuning delay line;

and the output end of the third logic structure is used for outputting the output signal of the coarse tuning delay line.

Optionally, the fine tuning delay unit includes: a third delay branch, a fourth delay branch and a second selector;

the third delay branch comprises a plurality of third switches and a plurality of stages of first fine configuration delay units, and when each third switch is turned on, the third delay branch is used for short-circuiting different numbers of the first fine configuration delay units;

the fourth delay branch comprises a fourth switch and a second fine configuration delay unit;

the third delay branch and the fourth delay branch are connected in parallel to form a second parameter adjusting structure, one end of the second parameter adjusting structure is used for receiving an input signal, and the other end of the second parameter adjusting structure is connected with the second selector;

the second type of control signal is further configured to control the second selector to switch the fourth delay branch into the loop, and to control the fourth switch to be turned on, so that the fourth delay branch short-circuits the third delay branch, and the delay time parameter of the fine delay line is minimized and matched with the delay time parameter of the coarse delay unit;

the first type of control signal is further used for controlling the second selector to switch the third delay branch into the loop, and for controlling the third switch corresponding to the first type of control signal to be turned on, so that the delay time parameter of the fine delay line is matched with the delay time parameter of the coarse delay unit.

Optionally, the delay time parameter of the fine delay line and the delay time parameter of the coarse delay unit satisfy a first preset formula;

the first preset formula includes:

wherein tFDU represents a unit fine delay time of the fine delay line, tCDU represents a unit coarse delay time of the coarse delay unit, and N represents a total number of fine delay units in the fine delay line.

Optionally, the value range of N is 8-32.

A delay locked loop comprising an output delay line as claimed in any preceding claim.

It can be seen from the above technical solutions that the present application provides an output delay line and a delay locked loop, wherein the output delay line is composed of a plurality of delay blocks, each of the delay blocks includes a configurable coarse delay line and a fine delay line, specifically, the coarse delay line includes a plurality of coarse delay units, the fine delay line includes a plurality of fine delay units, the respective delay time parameters of the coarse delay unit and the fine delay unit can be adjusted by configuring a selection signal to adjust the coarse configuration delay unit and the fine configuration delay unit of the access loop, so that the delay time parameters of the coarse delay line are matched with the configuration selection signal, and the delay time parameters of the fine delay line are matched with the delay time parameters of the coarse delay unit, thereby achieving the purpose of satisfying the delay times of the delay locked loops required in different frequency bands, the working frequency range of 33 MHz-800 MHz is realized by segments, and all time modes defined by the ONFI 4.2 international protocol can be supported.

In addition, the delay locked loop based on the output delay line has good expandability, can meet all time sequence mode requirements of NV-DDR2/3 interfaces in the current ONFI 4.2 international protocol, can also cover a wider frequency range, and meets the development requirements of future ONFI new standards.

Furthermore, the output delay line provided by the embodiment of the application does not need to change other structures, and the problem of long delay chains caused by a large frequency locking range is effectively solved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a four-phase output clock signal;

FIG. 2 is a schematic diagram of the phase relationship between data DQ and clock DQS of a NAND Flash interface specified by the ONFI protocol under read/write operations;

FIG. 3 shows the NAND Flash all time modes Mode 0-Mode 15 specified by the ONFI 4.2 international standard;

FIG. 4 is a prior art architecture of a delay locked loop for generating four-phase clock signals;

FIG. 5 is a schematic diagram of a coarse delay unit;

FIG. 6 is a schematic diagram of a coarse delay line formed by the coarse delay cells shown in FIG. 5;

FIG. 7 is a schematic diagram of a configurable output delay line according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a configurable coarse delay unit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a multi-stage coarse configuration delay unit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a multi-stage coarse configuration delay unit according to another embodiment of the present application;

fig. 11 is a schematic structural diagram of a fine delay line according to an embodiment of the present application;

fig. 12 and 13 are simulation results of the output delay line in the shortest delay state and the longest delay state, respectively, when the configuration selection signal is the first type control signal;

fig. 14 and 15 are simulation results of the output delay line in the shortest delay state and the longest delay state, respectively, when the configuration selection signal is the second type control signal.

Detailed Description

In order to satisfy the high-speed DDR (Double Data Rate) Data transceiving function in the NAND Flash interface circuit, a multi-phase output is usually required to be realized, and a typical value is a four-phase output as shown in fig. 1.

The NAND Flash high-speed interface, NV-DDR/DDR2/3 mode, can realize data transceiving on the rising edge or the falling edge, so that a multi-phase complementary clock taking a global clock CLK as a source, typically a four-phase clock, needs to be generated. The ONFI protocol specifies that the NAND Flash interface has different phase relations between data DQ and clock DQS under read/write operation. Referring to FIG. 2, taking high speed NV-DDR2/DDR3 as an example: when reading data, the NAND sends source synchronized DQ and DQS information (as noted in the rectangular box labeled in FIG. 2), with the DQS edge aligned with the DQ edge.

In order to ensure the accuracy of data sampling and to accommodate jitter of uncertain data (still referring to the rectangular frame labeled part in fig. 2), the edge of the clock DQS is aligned with the middle position of the data DQ.

The ONFI 4.2 international standard published in 2020 specifies all time modes Mode 0-Mode 15 of NAND Flash, which are shown in fig. 3, and it can be seen from fig. 3 that in order to meet the latest ONFI 4.2 international standard requirements, the design requirements of the delay locked loop are as follows: (1) the locking range must cover the frequency range of 33 MHz-800 MHz; (2) four-phase clock signals can be generated.

Referring to fig. 4, fig. 4 shows a possible structure of a delay locked loop for generating a four-phase clock signal, which includes a Phase Detector (PD), a control logic, an N-bit coarse lock controller, an M-bit fine lock controller, and a four-phase output delay line (DCDL), where the four-phase output delay line is composed of 4 identical delay blocks (HDL), each of which is composed of a Coarse Delay Line (CDL) and a Fine Delay Line (FDL), and each of the delay blocks is controlled by the same coarse and fine control codes, i.e., the delays generated by them are identical.

After the delay phase-locked loop is normally started, the N-bit coarse lock controller/M-bit fine lock controller starts to work, a rough locking position is determined, a coarse tuning control code and a fine tuning control code are generated, and the coarse tuning control code and the fine tuning control code control a four-phase output delay line to generate corresponding delay.

The input clock CLKin gets four-phase output clocks CLK90, CLK180, CLK270, and CLK360 through four-phase output delay lines.

The clock signal CLK360 is fed back to the phase detector, which compares the phase relationship between CLK360 and CLKin and outputs an UP/DN signal. And the UP/DN signal is sent into the control logic module, so that the N-bit coarse lock controller/M-bit fine lock controller adjusts the coarse adjustment control code and/or the fine adjustment control code according to the information of the UP/DN signal. And after the delay of the four-phase output delay line is adjusted according to the coarse adjustment control code and/or the fine adjustment control code, the obtained CLK360 is continuously fed back to the phase discriminator to be compared with the CLKin, if the UP/DN is different, the delay needs to be further adjusted, namely the steps are repeated, and if the UP/DN is the same, the CLK360 is aligned with the CLKin, and the delay phase-locked loop is locked.

The inventor researches and finds that the frequency locking range of the delay-locked loop is limited by the delay range of a four-phase output delay line, the shortest delay of the four-phase output delay line determines the upper frequency locking limit, and the longest delay of the four-phase output delay line determines the lower frequency locking limit.

As shown in FIG. 5, a typical coarse delay cell consists of 4 NAND gates and 1 inverter, and the complementary control codes Ci/Ci determine the propagation path length, thereby controlling the unit time of the coarse delay. In fig. 5, in and out represent the input and output of the coarse delay unit, respectively, next in represents the input connected to the next coarse delay unit, and next out represents the output connected to the next coarse delay unit.

The coarse delay line is composed of a plurality of coarse delay units connected in series, and the frequency locking range of the delay-locked loop determines the number of the coarse delay units (i.e. the total delay time). The number of coarse delay units is equal to the number of bits of the coarse control code, and as shown in fig. 6, a specific structure of a coarse delay line is shown, where the number of coarse delay units is 16, which is selected for comprehensive consideration of power consumption and area.

Similarly, the fine delay line is also composed of a plurality of fine delay cells connected in series. And the power consumption, the area and the precision factor are also comprehensively considered, and the number of the fine delay unit stages is selected to be 16.

To ensure that the logic is correct and the delay locked loop can lock properly, the total delay of the fine delay line must cover one unit of coarse delay time, and then the unit of fine delay time is equal to the total delay/16 of the fine delay line ≈ unit of coarse delay/16.

The four-phase output delay line consists of 4 delay blocks connected in series, so that the four-phase output delay line comprises 64 stages of coarse delay units and 64 stages of fine delay units in total.

The shortest delay (DCDL, min) of the four-phase output delay line is (intrinsic delay of coarse delay line + intrinsic delay of fine delay line) × 4; the longest delay (DCDL, max) of the four-phase output delay line is DCDL, min + (16 × tCDU +16 × tFDU) × 4.

Taking a 28nm CMOS Process adopted by most of the existing controller chips as an example, after design optimization, the DCDL is obtained by simulation under the condition of typical PVT (Process, Voltage, Temperature; tt corner,0.9V,25 ℃), wherein min is 802.6ps, and max is 6.72 ns.

In addition to the delay line circuits, intrinsic delays (approximately 30ps) are also present in other circuit blocks within the DLL system. Therefore, the DLL can lock the clock with the minimum period of about 833ps and the maximum period of about 6.75 ns; the frequency range in which it can operate is approximately 148MHz, 1.2 GHz.

Therefore, it can be seen that even through system optimization, the locking range of the four-phase delay-locked loop cannot meet the requirement of [33MHz,800MHz ] frequency range specified by ONFI 4.2. If the length and the precision of the extension line are simply increased, the number of transistors and the complexity of a control circuit are increased sharply, and the area and the power consumption are unacceptable.

The ONFI 4.2 international protocol standard specifies a minimum clock frequency of 33MHz (mode0), and a delay-locked loop must increase the delay time of a four-phase output delay line to achieve low-frequency locking. If the delay of the delay units in the coarse delay line and the fine delay line is increased, the upper limit of the frequency lock will be reduced, and the requirement of wide-band input still cannot be realized.

If the four-phase output delay line is extended by increasing the number of delay units in the coarse delay line and the fine delay line, DCDL needs to be realized, and 30MHz low-frequency locking can be realized only when max is about 30ns, so the four-phase output delay line needs to be enlarged by about 4.5 times (30ns/6.72ns), and the number of stages of the coarse delay unit and the fine delay unit needs to be enlarged to 286. This greatly increases the area of the delay line, and at the same time, the number of bits of the controller is enlarged, and the area of the controller is also greatly increased. This approach is not feasible in practical physical design due to area and power consumption considerations.

If the requirement of the maximum clock frequency 800MHz (mode15) specified by the ONFI 4.2 protocol needs to be met, the unit delay time needs to be shortened to improve the precision, which further increases the number of delay units in the four-phase output delay line, resulting in larger power consumption and area.

In view of this, an embodiment of the present application provides an output delay line, where the output delay line is composed of a plurality of delay blocks, each of the delay blocks includes a configurable coarse delay line and a fine delay line, specifically, the coarse delay line includes a plurality of coarse delay units, the fine delay line includes a plurality of fine delay units, and the adjusting of the respective delay time parameters of the coarse delay unit and the fine delay unit can be implemented by adjusting the stages of the coarse delay unit and the fine delay unit of the access circuit through a configuration selection signal, so that the delay time parameter of the coarse delay line matches the configuration selection signal, and the delay time parameter of the fine delay line matches the delay time parameter of the coarse delay unit, thereby implementing the purpose of satisfying the delay time of the delay locked loop required in different frequency bands, and implementing the operating frequency range of 33MHz to 800MHz in segments, all time patterns defined by the ONFI 4.2 international protocol can be supported.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

An embodiment of the present application provides an output delay line, as shown in fig. 7, applied to a delay locked loop, where the output delay line includes: a plurality of delay blocks 10, each of said delay blocks 10 comprising a coarse delay line 11 and a fine delay line 12 connected in series, wherein,

the coarse delay line 11 comprises a plurality of coarse delay units, each coarse delay unit comprises a plurality of coarse configuration delay units, and each coarse delay unit is configured to receive a configuration selection signal S and adjust the stage number of the coarse configuration delay unit connected to the loop according to the configuration selection signal S, so as to adjust the delay of the coarse delay unit, and thus the delay time parameter of the coarse delay line 11 is matched with the configuration selection signal S;

the fine delay line 12 includes a plurality of fine delay units, each of which includes a plurality of fine configuration delay units, and the fine delay units are configured to receive the configuration selection signal S and adjust the number of stages of the fine configuration delay units connected to the loop according to the configuration selection signal S, so as to adjust the delay of the fine delay units, and thus the delay time parameter of the fine delay line 12 is matched with the configuration selection signal S and the delay time parameter of the coarse delay unit.

The output delay line provided by the embodiment of the application adopts the configurable delay structure on the premise of not adjusting other circuits or controllers and not prolonging the 10 levels of the delay blocks in the output delay line, utilizes the configuration selection signal S to switch the required delay lines under different frequency bands, and can ensure that the final working range of the delay phase-locked loop can completely cover the requirements of the ONFI 4.2 international standard through the mutual overlapping of different working frequency bands, and effectively solves the problem of long delay chains caused by a large frequency locking range. In fig. 7, CLKin represents the clock signal input to the output delay line.

Further, fig. 7 shows delay control signals C <15:0> and F <15:0> supplied to the coarse delay line and the fine control line, respectively, the delay control signals C <15:0> determining the length of the propagation path of the coarse delay line, and the number of stages of the coarse delay cells in the propagation path being equal to the number of significant bits of the delay control signals C <15:0 >. Similarly, the delay control signal F <15:0> is used to determine the propagation path length of the fine delay line, and the number of fine delay cells in the propagation path is equal to the effective number of bits of the delay control signal F <15:0 >.

A specific possible structure of the output delay line provided in the embodiments of the present application is described below.

Referring to fig. 8, the coarse delay unit in the coarse delay line 11 includes: a first delay branch 111, a second delay branch 112 and a first selector 113;

the first delay branch 111 comprises a plurality of first switches S1 and the multi-stage coarse configuration delay units 1141, and when each of the first switches S1 is turned on, the first delay branch is used for short-circuiting different numbers of the coarse configuration delay units 1141;

the second delay branch 112 comprises a second switch S2;

the first delay branch 111 and the second delay branch 112 are connected in parallel to form a first parameter adjusting structure, one end of the first parameter adjusting structure is used for receiving an input signal, and the other end of the first parameter adjusting structure is connected to the first selector 113;

the configuration selection signal S is determined according to the frequency of a clock signal input into the delay locked loop, and when the frequency of the clock signal is smaller than a first preset value, the configuration selection signal S is a first class control signal corresponding to the frequency band to which the clock signal belongs; when the frequency of the clock signal is greater than or equal to the first preset value, the configuration selection signal S is a second type control signal;

the second type of control signal is used for controlling the first selector 113 to switch the second delay branch 112 into the loop, and for controlling the second switch S2 to be turned on, so that the second delay branch 112 short-circuits the first delay branch 111, and the delay time parameter of the coarse delay line 11 is minimized;

the first type of control signal is used to control the first selector 113 to switch the first delay branch 111 into the loop, and is used to control the second switch S2 corresponding to the first type of control signal to be turned on, so that the delay time parameter of the coarse delay line 11 matches with the configuration selection signal S.

In fig. 8, 114 denotes a delay unit 1141 composed of a plurality of stages of the coarse configuration.

The configuration selection signal S may be determined by a frequency detector of the delay locked loop, which detects the frequency range of the incoming clock signal before the delay locked loop starts the locking process, thereby determining the configuration of the delay line. In addition, the delay-locked loop may determine the arrangement of the delay line by determining a frequency range of the input clock signal in a predetermined timing pattern.

The first preset value depends on the upper limit of the required operating frequency range of the output delay line and the specific device parameters of the first selector 113. In general, when the frequency of the input clock signal is smaller than a first preset value, the input clock signal may be considered as a low-frequency clock signal, and the first selector 113 selects the first delay branch 111 to access the loop to perform delay processing on the input clock signal. When the frequency of the input clock signal is greater than or equal to the first preset value, the input clock signal can be considered as a high-frequency clock signal, and the first selector 113 selects the second delay branch 112 to be connected into the loop.

Since the first delay branch 111 includes a plurality of first switches S1 and a plurality of coarse configuration delay units 1141, the number of feasible values of the first type of control signal is the same as the number of stages of the plurality of coarse configuration delay units 1141 and the number of the plurality of first switches S1, a value of one first type of control signal corresponds to one first switch S1, and the first type of control signal turns on the first switch S1 corresponding to the first type of control signal, so that the first switch S1 short-circuits the coarse configuration delay units 1141 of a corresponding number, thereby implementing multi-stage adjustment of the delay time parameter of the coarse tuning delay line 11.

Alternatively, referring to fig. 9, the multiple stages of coarse configuration delay units 1141 are connected in series in sequence;

first ends of the plurality of first switches S1 are all connected to the output end of the first delay branch 111;

a second end of each of the first switches S1 is connected to a connection node of every two coarse delay units 1141.

Also shown in fig. 9 is a possible construction of a particularly coarsely configured delay cell 1141, which in fig. 9 includes two inverters connected in series.

In an alternative embodiment of the present application, referring to fig. 10, fig. 10 shows the composition of another possible coarse configuration delay unit 1141, in fig. 10, the coarse configuration delay unit 1141 includes two inverters and two capacitors;

In fig. 10, in addition to adjusting the delay time by adjusting the number of stages of the coarse configuration delay units 1141 accessing the loop, the adjustment of the delay time can be realized by adjusting the size of the capacitor in each coarse configuration delay unit 1141. Specifically, the delay time t of each coarse configuration delay unit 1141 is R × C, where R is the equivalent resistance of the coarse configuration delay unit 1141, and C represents the size of the capacitor, and when R remains unchanged, increasing the capacitance of the capacitor may increase the delay time t, and decreasing the capacitance of the capacitor may decrease the delay time t.

Still referring to fig. 8, fig. 8 also shows another possible structure of the coarse delay line 11, and in fig. 8, the coarse delay unit further includes: a first logic structure 117, a second logic structure 115, a third logic structure 116, and a fourth logic structure 118; wherein the content of the first and second substances,

first inputs of the first logic structure 117 and the second logic structure 115 are both connected to an output of the first selector 113;

a second input end of the first logic structure 117 is configured to receive a first coarse control code C , and an output end of the first logic structure 117 is used as an output end of the coarse tuning delay line 11 to a next coarse tuning delay line 11;

a second input end of the second logic structure 115 is configured to receive a second coarse control code-C , the first coarse control code C and the second coarse control code-C are in opposite phase, and an output end of the second logic structure 115 is connected to first input ends of the third logic structure 116 and the fourth logic structure 118;

a second input terminal of the third logic structure 116 is connected to a second input terminal of the fourth logic structure 118, and serves as an input terminal of the coarse tuning delay line 11 for receiving an output signal of the next coarse tuning delay line 11;

the output of the third logic structure 116 is used to output the output signal of the coarse delay line 11.

The first logic structure 117, the second logic structure 115, the third logic structure 116, and the fourth logic structure 118 may all be nand gates. FIG. 8 also shows the generation of the first coarse control code C and the second coarse control code C , i.e., the first coarse control code C gets the second coarse control code C by inputting an inverter.

Accordingly, the structure of the fine delay line 12 can refer to the structure of the coarse delay line 11, and optionally, referring to fig. 11, the fine delay unit includes: a third delay branch 121, a fourth delay branch 122 and a second selector 123;

the third delay branch 121 includes a plurality of third switches S3 and a plurality of stages of first fine configuration delay units, and each of the third switches S3 is turned on to short-circuit a different number of the first fine configuration delay units;

the fourth delay branch 122 includes a fourth switch S4 and a second fine configuration delay cell;

the third delay branch 121 and the fourth delay branch 122 are connected in parallel to form a second parameter adjusting structure, one end of the second parameter adjusting structure is used for receiving an input signal, and the other end of the second parameter adjusting structure is connected to the second selector 123;

the second type of control signal is further configured to control the second selector 123 to switch the fourth delay branch 122 into the loop, and to control the fourth switch S4 to be turned on, so that the fourth delay branch 122 short-circuits the third delay branch 121, and the delay time parameter of the fine delay line 12 is minimized and matches the delay time parameter of the coarse delay line 11;

the first type of control signal is further used to control the second selector 123 to switch the third delay branch 121 into the loop, and to control the third switch S3 corresponding to the first type of control signal to be turned on, so that the delay time parameter of the fine delay line 12 matches the delay time parameter of the coarse delay line 11.

In fig. 11, 1211 denotes a plurality of stages of the first fine configuration delay unit. 1221 denotes the second fine configuration delay unit.

Optionally, the delay time parameter of the fine delay line 12 and the delay time parameter of the coarse delay line 11 satisfy a first preset formula;

the first preset formula includes:

wherein tFDU represents unit fine delay time of the fine delay line, tCDU represents unit coarse delay time of the coarse delay units, and N represents total number of configurable fine delay units in the fine delay line.

Wherein the value range of N can be selected to be 8-32.

Since the fine delay line 12 needs to be changed in accordance with the change of the unit coarse delay time, the fine delay line 12 should also be changed to be a configurable delay line structure, and the specific feasible structures of the third delay branch 121 and the fourth delay branch 122 can refer to the first delay branch 111 and the second delay branch 112.

In this embodiment, the fine delay unit is divided into a first fine configuration delay unit and a second fine configuration delay unit, the structure of the fine delay unit is different according to the different working frequency bands, when the working frequency band is a high frequency, the structure of the fine delay unit is a capacitor, and when the working frequency band is a low frequency, the structure of the fine delay unit may be the same as the structure of the coarse delay unit under the minimum delay configuration.

The output delay line provided by the embodiment of the present application is experimentally verified by taking 16 stages of fine delay units and 16 stages of coarse delay units as examples.

The simulation structure obtained by simulating the whole configurable output delay line under a typical PVT is shown in fig. 12 and 13, and fig. 12 and 13 are simulation results of the output delay line under the shortest delay state and the longest delay state, respectively, when the configuration selection signal S is the control signal of the first type. When the configuration selection signal S is a first type control signal, the output delay line operates in a high frequency band, the intrinsic delay of the coarse delay line 11 + the intrinsic delay of the fine delay line 12 is about 82ps, the unit coarse delay is about 38ps, and the unit fine delay is about 2.75 ps.

The simulation results show that the minimum delay time of the output delay line is 327ps, the maximum delay time is 2.98ns, and the result accords with logic.

Referring to fig. 14 and 15, fig. 14 and 15 are simulation results of the output delay line in the shortest delay state and the most frequently delayed state, respectively, when the configuration selection signal S is the second type control signal.

The intrinsic delay of the coarse delay line 11 + the intrinsic delay of the fine delay line 12 is about 338ps, the unit coarse delay time is about 626ps, and the unit fine delay time is about 43ps, when the configuration selection signal S is the second type control signal, the output delay line operates in a low frequency band, the minimum delay time of the output delay line is 1.35ns, and the maximum delay time is 44.2 ns. The simulation result shows that the longest delay time (2.98ns) when the configuration selection signal S is the first type control signal is longer than the longest delay time (1.35ns) when the configuration selection signal S is the second type control signal, which indicates that the two working frequency bands are overlapped with each other and the working range of the output delay line is continuous. In fig. 12 to 15, waveforms from top to bottom are CLKin (input clock signal), CLK90, CLK180, CKL270, and CLK360 (output four-phase clock signal, respectively), respectively.

When the configuration selection signal S is the second type control signal, the frequency locking range of the output delay line is about 23 MHz-700 MHz, and when the configuration selection signal S is the first type control signal, the frequency locking range of the output delay line is about 335 MHz-3 GHz.

Therefore, the output delay line provided by the embodiment of the application meets the requirement of the working frequency range of 33 MHz-800 MHz in the ONFI 4.2 international standard protocol on the premise of not adjusting other circuit structures of the delay phase-locked loop and the number of stages of the delay block 10 of the extended output delay line, and achieves the purpose of supporting all time modes defined in the ONFI 4.2 international standard protocol.

Correspondingly, the embodiment of the present application further provides a delay locked loop, including the output delay line according to any of the above embodiments.

To sum up, the embodiment of the present application provides an output delay line and a delay locked loop, wherein, the output delay line is composed of a plurality of delay blocks, each the delay block includes configurable coarse delay line and fine delay line, specifically, the coarse delay line includes multi-stage coarse delay unit, the fine delay line includes multi-stage fine delay unit, the adjustment of the respective delay time parameter of coarse delay unit and fine delay unit can be realized through the stage number of coarse configuration delay unit and fine configuration delay unit of configuration selection signal adjustment access loop, so that the delay time parameter of coarse delay line matches with the configuration selection signal, and the delay time parameter of fine delay line matches with the delay time parameter of coarse delay unit, the purpose of satisfying the delay time of the required delay locked loop under different frequency bands is realized, the working frequency range of 33 MHz-800 MHz is realized by segments, and all time modes defined by the ONFI 4.2 international protocol can be supported.

Features described in the embodiments in the present specification may be replaced with or combined with each other, each embodiment is described with a focus on differences from other embodiments, and the same and similar portions among the embodiments may be referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An output delay line for use in a delay locked loop, the output delay line comprising: a plurality of delay blocks, each of the delay blocks comprising a coarse delay line and a fine delay line connected in series, wherein,

2. The output delay line of claim 1, wherein the coarse delay unit comprises: the delay circuit comprises a first delay branch, a second delay branch and a first selector;

the second delay branch comprises a second switch;

3. The output delay line of claim 2, wherein the plurality of coarse configuration delay units are serially connected in sequence;

4. The output delay line of claim 3, wherein the coarse configuration delay unit comprises two inverters connected in series.

5. The output delay line of claim 3, wherein the coarse configuration delay cell comprises two inverters and two capacitors;

6. The output delay line of claim 2, wherein the coarse delay unit further comprises: a first logic structure, a second logic structure, a third logic structure, and a fourth logic structure; wherein the content of the first and second substances,

7. The output delay line of claim 2, wherein the fine delay unit comprises: a third delay branch, a fourth delay branch and a second selector;

8. The output delay line of claim 7, wherein the delay time parameter of the fine delay line and the delay time parameter of the coarse delay unit satisfy a first predetermined formula;

the first preset formula includes:

9. The output delay line of claim 8, wherein N is in the range of 8 to 32.

10. A delay locked loop comprising an output delay line as claimed in any one of claims 1 to 9.