CN103780251A - Control method for selecting frequency band and related clock data recovery device - Google Patents
Control method for selecting frequency band and related clock data recovery device Download PDFInfo
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- CN103780251A CN103780251A CN201310019747.7A CN201310019747A CN103780251A CN 103780251 A CN103780251 A CN 103780251A CN 201310019747 A CN201310019747 A CN 201310019747A CN 103780251 A CN103780251 A CN 103780251A
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Abstract
A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.
Description
Technical field
This case relates to a kind of control method for generation of clock and relevant clock data recovery device thereof, especially relates to a kind of control method and relevant clock data recovery device thereof that does not need accurate reference frequency can produce accurate clock.
Background technology
In electronic system, the clock signal between signal sending end and signal receiving end often exists clock jitter.Therefore, electronic system need to be used clock and data recovery (clock data recovery, CDR) circuit to calibrate clock jitter, to obtain correct transmission data in signal receiving end.Typically, clock data recovery device need, by using reference frequency accurately, just can accurately be calibrated clock jitter according to this.
For instance, please refer to Fig. 1, Fig. 1 is the schematic diagram of a known clock data recovery device 10.Clock data recovery device 10, by an input traffic DATAIN and a reference clock REF, produces recovered clock CLK and clock recovery data (Rerimed data) RDATA.As shown in Figure 1, clock data recovery device 10 comprises a phase detector PDET, a frequency detector FDET, a selected cell SEL, a state machine STA, a charge pump CP, a low-frequency filter LPF, a multiband voltage-controlled oscillator (VCO) VCO and a frequency elimination cells D IV.Phase detector PDET is used for detecting the phase difference distance between the data frequency of input traffic DATAIN and the recovered clock CLK of multiband voltage-controlled oscillator (VCO) VCO output, and exports according to this phase difference apart from signal S_PD and a phase-locked signal DLOCK.Phase detector PDET is separately by input traffic DATAIN and recovered clock CLK, and output clock recovers data RDATA.For instance, phase detector PDET can comprise a D flip-flop and a serial/parallel transducer (serial-to-parallel converter).Wherein, D flip-flop is used for by the frequency of recovered clock CLK calibration input traffic DATAIN, and calibration input traffic DATAIN later after the conversion of serial/parallel transducer, can obtain clock recovery data RDATA again.Frequency detector FDET is used for detecting the frequency distance between reference clock REF and a frequency elimination clock DIVCLK, and exports according to this frequency distance signal S_FD and a Frequency Locking signal FLOCK.Wherein, frequency elimination clock signal DIVCLK is produced after frequency elimination cells D IV frequency elimination by recovered clock CLK.Selected cell SEL is used for by a selection control signal CON, in output phase gap signal S_PD and frequency distance signal S_FD wherein one to charge pump CP.Charge pump CP is used for the signal of exporting by selected cell SEL, produces a suitable current signal CC tremendously low frequency filter LPF.Low-frequency filter LPF, by current signal CC, produces corresponding latch voltage VC.Multiband voltage-controlled oscillator (VCO) VCO is used for by latch voltage VC, produces recovered clock CLK.State machine STA is used for by phase-locked signal DLOCK and Frequency Locking signal FLOCK, and output is for controlling the selection control signal CON of selected cell SEL.
In simple terms, in the time that clock data recovery device 10 is started working, first clock data recovery device 10 makes the recovered clock CLK of multiband voltage-controlled oscillator (VCO) VCO output approach reference clock REF by reference to clock REF.Therefore, state machine STA selects control signal CON by adjustment, makes selected cell SEL output frequency gap signal S_FD.Next, in the time that recovered clock CLK approaches reference clock REF, frequency detector FDET can export suitable Frequency Locking signal FLOCK, so that state machine STA controls selected cell SEL output phase gap signal S_PD, thereby further locks by input traffic DATAIN.Thus, by two stage locking, clock data recovery device 10 can be avoided mistake lock (mis-lock) phenomenon by reference clock REF accurately, and then lock more accurately by input traffic DATAIN, to obtain correct clock recovery data RDATA and recovered clock CLK.
But clock data recovery device 10 needs precisely and the reference clock REF of low jitter, just can avoid phenomenon occurs to lock in the time further locking by input traffic DATAIN by mistake.On the other hand, in the time that clock data recovery device 10 comes into operation, in input signal IN, must comprise one section of training pattern (training pattern), clock data recovery device 10 begins to be locked to recovered clock CLK accurately, to capture correct clock recovery data RDATA.
Summary of the invention
Therefore, the present invention proposes a kind ofly not need accurate reference clock can produce the control method of accurate recovered clock and relevant clock data recovery device.
By one side, the present invention discloses a kind of control method, for supporting a clock data recovery device of multiple frequency ranges, be used for controlling this clock data recovery device and in the plurality of frequency range, select a working frequency range, so that this clock data recovery device generation one is used for producing the recovered clock of clock recovery data (retimed data), this control method comprises that reception has the serial datum stream of a data frequency; By the plurality of frequency range, corresponding to multiple frequency range group, wherein each frequency range group comprises at least one frequency range and corresponding to different frequency scope; By this data frequency and a latch voltage scope, in the plurality of frequency range group, select a frequency range group as a coarse adjustment frequency range group; And by this data frequency, this latch voltage scope and this coarse adjustment frequency range group, select a frequency range as this working frequency range, to produce this recovered clock.
By on the other hand, the present invention discloses a kind of clock data recovery device, comprise a phase detector, one of a data frequency that is used for flowing by serial datum and a recovered clock recovered frequency and produced a detecting phase signal, and by this serial data stream and this recovered clock, produce and recover data; One charge pump, is coupled to this phase detector, is used for producing a current signal by this detecting phase signal; One low pass filter, is coupled to this charge pump, is used for producing a latch voltage according to this current signal; One multi-band voltage-controlled oscillator, is coupled to this low pass filter, in order to by a Frequency Band Selection signal, operates in the working frequency range in multiple frequency ranges, and exports this recovered clock according to this latch voltage and this working frequency range; One voltage range generation unit, by a scope control signal, produces a latch voltage scope; One comparing unit, be coupled to this voltage range generation unit and this low pass filter, be used for by a ceiling voltage of this latch voltage and this latch voltage scope, export a high locking signal, and by a minimum voltage of this latch voltage and this latch voltage scope, output one low locking signal; An and control module, be coupled to this comparing unit, this charge pump, this voltage range generation unit and this multi-band voltage-controlled oscillator, be used for, by this latch voltage, this latch voltage scope, this high locking signal and this low locking signal, exporting this Frequency Band Selection signal and this scope control signal.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a known clock data recovery device.
Fig. 2 is the schematic diagram of the embodiment of the present invention one clock data recovery device.
Example schematic when Fig. 3 A, 3B are the clock data recovery device running shown in Fig. 2.
Fig. 4 is the schematic diagram of clock data recovery device one execution mode shown in Fig. 2.
Another example schematic when Fig. 5 is the clock data recovery device running shown in Fig. 2.
Fig. 6 is the schematic diagram of the embodiment of the present invention one control method.
Wherein, description of reference numerals is as follows:
10,20 clock data recovery devices
200 voltage range generation units
202 comparing units
204 control modules
400 digital-to-analogue conversion devices
402,404 comparators
60 control methods
600～624 steps
CFREQ recovers frequency
CP charge pump
CP_EN charge pump enable signal
CLK recovered clock
CON selects control signal
CON_R scope control signal CON_R
CTT_VBG coarse adjustment test frequency range group
CTT_VB coarse adjustment test frequency range
DATAIN input traffic
DFREQ data frequency
DIV frequency elimination unit
DIVCLK frequency elimination clock
DLOCK phase-locked signal
FDET frequency detector
FLOCK Frequency Locking signal
FTT_VB fine tuning test frequency range
LPF low-frequency filter
PDET phase detector
RDATA clock recovery data
REF reference clock
SEL selected cell
STA state machine
S_FD frequency distance signal
S_PD phase difference is apart from signal
VB_1～VB_n, VB_1～VB_15 frequency range
VB_1’～VB_12’
VB_SEL Frequency Band Selection signal
VB_W working frequency range
VBG_1～VBG_m, VBG_1～VBG_5 frequency range group
VC latch voltage
The high locking signal of VC_H
The low locking signal of VC_L
VCO multiband voltage-controlled oscillator (VCO)
VR, VR1, VR2 latch voltage scope
Embodiment
In following cited exemplary embodiment, clock data recovery device, by inputing to the latch voltage VC of multiband voltage-controlled oscillator (VCO) VCO, is adjusted multiband voltage-controlled oscillator (VCO) VCO automatically, so that multiband voltage-controlled oscillator (VCO) VCO is operated in most suitable frequency range.For more clearly understanding the present invention, below will coordinate accompanying drawing, elaborate with at least one exemplary embodiment.In addition, the connection term of mentioning in following examples, for example: couple or connection etc., be only with reference to attached drawings in order to illustrate, be not used for restriction in fact the annexation between two assemblies be directly to couple or indirectly couple.In other words, in certain embodiments, between two assemblies for directly coupling.In other embodiment, between two assemblies for indirectly coupling.
Please refer to Fig. 2, Fig. 2 is the schematic diagram of the embodiment of the present invention one clock data recovery device 20.Clock data recovery device 20 is used for flowing DATAIN by serial datum, output one recovered clock CLK and a clock recovery data RDATA.As shown in Figure 2, clock data recovery device 20 comprises a phase detector PDET, a charge pump CP, a low pass filter LPF, a multiband voltage-controlled oscillator (VCO) VCO, a voltage range generation unit 200, a comparing unit 202 and a control module 204.Phase detector PDET is used for producing a detecting phase signal S_PD by a data frequency DFREQ of serial data stream DATAIN and the recovery frequency CFREQ of recovered clock CLK.Phase detector PDET is separately by data flow DATAIN and recovered clock CLK, and output clock recovers data RDATA.For instance, phase detector PDET can comprise a D flip-flop and one serial/parallel converters (serial-to-parallel converter).Wherein, D flip-flop is used for by the frequency of recovered clock CLK calibration input traffic DATAIN, and calibration input traffic DATAIN later after the conversion of serial/parallel transducer, can obtain clock recovery data RDATA again.Charge pump CP is coupled to this phase detector PDET, is used for producing a current signal CC by detecting phase signal S_PD and a charge pump enable signal CP_EN.Low pass filter LPF is coupled to charge pump CP, is used for producing a latch voltage VC to multiband voltage-controlled oscillator (VCO) VCO according to current signal CC.Multiband voltage-controlled oscillator (VCO) VCO is coupled to low pass filter LPF, is used for, by a Frequency Band Selection signal VB_SEL, operating in the working frequency range VB_W in frequency range VB_1～VB_n, and exports recovered clock CLK according to latch voltage VC and working frequency range VB_W.Voltage range generation unit 200, by a scope control signal CON_R, produces a latch voltage scope VR.Comparing unit 202 is coupled to voltage range generation unit 200 and low pass filter LPF, be used for by a ceiling voltage of latch voltage VC and latch voltage scope VR, export a high locking signal VC_H, and by a minimum voltage of latch voltage VC and latch voltage scope VR, output one low locking signal VC_L.Control module 204 is coupled to charge pump CP, voltage range generation unit 200, comparing unit 202 and multi-band voltage-controlled oscillator VCO, be used for by latch voltage VC and latch voltage scope VR, output Frequency Band Selection signal VB_SEL, scope control signal CON_R and charge pump enable signal CP_EN.Thus, clock data recovery device 20 can pass through latch voltage VC, automatically chooses in frequency range VB_1～VB_n most suitable frequency range as working frequency range VB_W.In other words, clock data recovery device 20 does not need to use reference clock or training pattern, i.e. the recovered clock CLK of exportable high accurancy and precision and correct clock recovery data RDATA accurately.
Specifically, first frequency range VB_1～VB_n of multiband voltage-controlled oscillator (VCO) VCO is divided into the VBG_1～VBG_m of frequency range group.Wherein, each frequency range group all comprises at least one frequency range, and each frequency range group is corresponding to different frequency ranges.Next, control module 204 can be by adjusting Frequency Band Selection signal VB_SEL, and one of them tests the CTT_VBG of frequency range group as coarse adjustment to select at random the VBG_1～VBG_m of frequency range group.Now, multiband voltage-controlled oscillator (VCO) VCO also can select a frequency range in the coarse adjustment test CTT_VBG of frequency range group to test frequency range CTT_VB as coarse adjustment by Frequency Band Selection signal VB_SEL, and makes multiband voltage-controlled oscillator (VCO) VCO be operated in coarse adjustment test frequency range CTT_VB.Preferably, frequency range corresponding to coarse adjustment test frequency range CTT_VB is the median of frequency range corresponding to the contained frequency range of the coarse adjustment test CTT_VBG of frequency range group, but not subject to the limits.
Next, control module 204 is adjusted charge pump enable signal CP_EN makes clock data recovery device 20 start to lock, to produce the latch voltage VC corresponding to coarse adjustment test frequency range CTT_VB.Under this situation, comparing unit 202 starts, by latch voltage scope VR and latch voltage VC, to produce high locking signal VC_H and low locking signal VC_L, to indicate latch voltage VC whether to drop on latch voltage scope VR.For instance, in the time that latch voltage VC is greater than the maximum voltage of latch voltage scope VR, the high locking signal VC_H that comparing unit 202 is exported high logic level exceedes latch voltage scope VR with indication latch voltage VC.In the time that latch voltage VC is less than the minimum voltage of latch voltage scope VR, comparing unit 202 is exported the low locking signal VC_L of high logic level, to indicate latch voltage VC lower than latch voltage scope VR.In the time that latch voltage VC drops on latch voltage scope VR, the high locking signal VC_H that comparing unit 202 is exported and low locking signal VC_L are low logic level.By this, comparing unit 202 can judge whether latch voltage VC drops on latch voltage scope VR, and can indicate the magnitude relationship between latch voltage VC and latch voltage scope VR.It should be noted that comparing unit 202 need compare after latch voltage VC tends towards stability, to obtain correct high locking signal VC_H and low locking signal VC_L.
In the time that comparing unit 202 indicates latch voltage VC to drop in latch voltage scope VR, represent that the data frequency DFREQ of input traffic DATAIN drops on the frequency range of the coarse adjustment test CTT_VBG of frequency range group correspondence in latch voltage scope VR.Therefore, this coarse adjustment test of control module 204 outputs CTT_VBG of frequency range group is as the coarse adjustment frequency range CT_VBG of group, further to lock.In the time that comparing unit 202 indicates latch voltage VC not drop in latch voltage scope VR, control module 204 can select another frequency range group as the coarse adjustment test CTT_VBG of frequency range group by high locking signal VC_H and low locking signal VC_L, and again carries out above-mentioned steps until latch voltage VC drops in latch voltage scope VR.For instance, in the time that high locking signal VC_H indication latch voltage VC exceedes latch voltage scope VR, representative data frequency DFREQ is higher than the frequency range of the coarse adjustment test CTT_VBG of frequency range group correspondence in latch voltage scope VR.The frequency range group that control module 204 selects respective frequencies scope to be greater than the current coarse adjustment test CTT_VBG of frequency range group tests the CTT_VBG of frequency range group as next coarse adjustment.Or when low locking signal VC_H indicates latch voltage VC lower than latch voltage scope VR, representative data frequency DFREQ is lower than the frequency range of the coarse adjustment test CTT_VBG of frequency range group correspondence in latch voltage scope VR.The frequency range group that control module 204 can select respective frequencies scope to be less than the current coarse adjustment test CTT_VBG of frequency range group tests the CTT_VBG of frequency range group as next coarse adjustment.Thus, by above-mentioned steps, clock data recovery device 20 can be comparable to the frequency range frequency range group that input traffic DATAIN is corresponding by fast searching, reduces locking time.
After the output coarse adjustment frequency range CT_VBG of group, control module 204 can be by adjusting Frequency Band Selection signal VB_SEL, select a frequency range in the coarse adjustment frequency range CT_VBG of group to test frequency range FTT_VB as fine tuning, and make multiband voltage-controlled oscillator (VCO) VCO be operated in fine tuning test frequency range FTT_VB.Subsequently, control module 204 is adjusted charge pump enable signal CP_EN makes clock data recovery device 20 start to lock, to produce the latch voltage VC corresponding to fine tuning test frequency range FTT_VB.Whether similarly, comparing unit 202 starts, by latch voltage scope VR and latch voltage VC, to produce high locking signal VC_H and low locking signal VC_L, to indicate latch voltage VC to drop in latch voltage scope VR.If latch voltage VC does not drop in latch voltage scope VR, control module 204, by high locking signal VC_H and low locking signal VC_L, selects another frequency range as fine tuning test frequency range FTT_VB.For instance, in the time that high locking signal VC_H indication latch voltage VC exceedes latch voltage scope VR, representative data frequency DFREQ is higher than the frequency range of fine tuning test frequency range FTT_VB correspondence in latch voltage scope VR.The frequency range group that control module 204 selects respective frequencies scope to be greater than current fine tuning test frequency range FTT_VB tests frequency range FTT_VB as next fine tuning.Or when low locking signal VC_H indicates latch voltage VC lower than latch voltage scope VR, representative data frequency DFREQ is lower than the frequency range of fine tuning test frequency range FTT_VB correspondence in latch voltage scope VR.The frequency range group that control module 204 can select respective frequencies scope to be less than current fine tuning test frequency range FTT_VB tests the CTT_VBG of frequency range group as next coarse adjustment.Should be noted, the selectable frequency range of control module 204 is not limited to the included frequency range of the coarse adjustment frequency range CT_VBG of group.
On the other hand, in the time that comparing unit 202 indicates latch voltage VC to drop in latch voltage scope VR, control module 204 is by judging whether latch voltage scope VR is less than or equal to an error critical value TH, to export best working frequency range VB_W.In the time that control module 204 judges that latch voltage scope VR is greater than error critical value TH, control module 204 adjusting range control signal CON_R to be to dwindle latch voltage scope VR, and make comparing unit 202 magnitude relationship between latch voltage VC and latch voltage scope VR relatively again.In the time that latch voltage scope VR is less than or equal to an error critical value TH, FTT_VB is as working frequency range VB_W for this fine tuning test frequency range of control module 204 outputs.By repeating above-mentioned steps until latch voltage scope VR is less than or equal to error critical value TH, clock data recovery device 20 does not need to use reference clock or training pattern accurately, can make multiband voltage-controlled oscillator (VCO) VCO be operated in most suitable working frequency range VB_W.By this, the recovered clock CLK of clock data recovery device 20 exportable high accurancy and precision and correct clock recovery data RDATA.
It should be noted that in the above-described embodiments, clock data recovery device 20 uses exhaustive person ignorant of the law to look for (blind search) to select the coarse adjustment frequency range CT_VBG of group and fine tuning test frequency range FTT_VB, but is not limited to this.For instance, clock data recovery device 20 can use as searching methods such as dichotomy (binary search), linear searchs (linear search), carry out the process of the accelerated selection coarse adjustment frequency range CT_VBG of group and fine tuning test frequency range FTT_VB, and not subject to the limits.
In order more to clearly demonstrate the operation of clock data recovery device 20, please refer to Fig. 3 A, Fig. 3 A is the schematic diagram of the clock data recovery device 20 1 running examples shown in Fig. 2.As shown in Figure 3A, the multiband voltage-controlled oscillator (VCO) VCO of clock data recovery device 20 comprises frequency range VB_1～VB_15.Wherein, frequency range VB_1～VB_15 is divided into the VBG_1～VBG_5 of frequency range group.First, control module 204 first selects the VBG_2 of frequency range group as the coarse adjustment test CTT_VBG of frequency range group, and selects the VBG_2 of frequency range group Mid Frequency VB_5 as coarse adjustment test frequency range CTT_VB.Because the latch voltage VC corresponding to frequency range VB_5 exceedes latch voltage scope VR, the frequency range group that therefore control module 204 can select respective frequencies scope to be greater than the VBG_2 of frequency range group tests the CTT_VBG of frequency range group as next coarse adjustment.In this embodiment, control module 204 selects the VBG_3 of frequency range group as next coarse adjustment test CTT_VBG of frequency range group, and selects frequency range VB_8 as coarse adjustment test frequency range CTT_VB.Now, due in the time that multiband voltage-controlled oscillator (VCO) VCO is operated in frequency range VB_8, latch voltage VC drops in latch voltage scope VR, and therefore control module 204 is exported the VBG_3 of frequency range group as the coarse adjustment frequency range CT_VBG of group.
Next, please refer to Fig. 3 B, Fig. 3 B is the schematic diagram of clock data recovery device 20 another running examples shown in Fig. 2.After determining that the VBG_3 of frequency range group is as the coarse adjustment frequency range CT_VBG of group, control module 204 selects frequency range VB_7 as fine tuning test frequency range FTT_VB.Now, while being operated in frequency range VB_7 due to multiband voltage-controlled oscillator (VCO) VCO, latch voltage VC exceedes latch voltage scope VR, therefore, control module 204 is by adjusting Frequency Band Selection signal VB_SEL, and the frequency range VB_8 that selects respective frequencies scope to be greater than frequency range VB_7 tests frequency range FTT_VB as fine tuning.Now, in the time that multiband voltage-controlled oscillator (VCO) VCO is operated in frequency range VB_8, though latch voltage VC position is in latch voltage scope VR, but because latch voltage scope VR is greater than error critical value TH, therefore control module 204 can be dwindled latch voltage scope VR to latch voltage scope VR1 by adjusting range control signal CON_R.Then, while being operated in frequency range VB_8 due to multiband voltage-controlled oscillator (VCO) VCO, latch voltage VC exceedes latch voltage scope VR1, therefore, control module 204 is by adjusting Frequency Band Selection signal VB_SEL, and the frequency range VB_9 that selects respective frequencies scope to be greater than frequency range VB_8 tests frequency range FTT_VB as fine tuning.Similarly, control module 204 can be contracted to the latch voltage scope VR2 that equals error critical value TH by latch voltage scope VR1.Now, while being operated in frequency range VB_9 due to multiband voltage-controlled oscillator (VCO) VCO, latch voltage VC position in latch voltage scope VR2 and latch voltage scope VR2 equal error critical value TH, therefore, control module 204 is exported frequency range VB_9 as working frequency range VB_W.By this, the recovered clock CLK of clock data recovery device 20 exportable high accurancy and precision and correct clock recovery data RDATA.
Should be noted, whether the latch voltage that the main spirits of above-described embodiment is to control multiband voltage-controlled oscillator (VCO) by detecting within the scope of default latch voltage, first judges the band limits corresponding to input traffic., then by the band limits of obtaining then, dwindle gradually latch voltage scope and with band limits corresponding to obtaining near the latch voltage of frequency range compare, to obtain the frequency range that is most suited to input traffic.By this, the clock data recovery device of above-described embodiment does not need reference clock accurately, and clock data recovery device may be locked to the frequency range that is most suited to input traffic, and produces the recovered clock of high accurancy and precision and correct clock recovery data.By different application, those skilled in the art should implement suitable change and modification according to this.For instance, control module 204 can separately comprise a storage element, and it is used for storing the working frequency range VB_W that control module 204 is exported.In the time of the initial running of clock data recovery device, control module 204 can directly read the working frequency range VB_W being stored in storage element, and does not need to re-execute locking process.On the other hand, clock data recovery device 20 also can first utilize frequency error to be greater than the reference frequency of clock data recovery device 20 lockable scopes, auxiliary clock Data Recapture Unit 20 enters lockable scope, carrying out above step, obtains best working frequency range VB_W with fast fetching.
In addition, please refer to Fig. 4, Fig. 4 is the schematic diagram of clock data recovery device 20 1 execution modes shown in Fig. 2.Wherein, voltage range generation unit 200 is realized by a digital-to-analogue conversion device 400, and comparing unit 202 is to be realized by 402,404 of comparators.Digital-to-analogue conversion device 400 is used for by scope control signal CON_R, produces a maximum voltage VRP of latch voltage scope VR and a minimum voltage VRN of latch voltage scope VR.Comparator 402 is used for comparison latch voltage VC and positive range of voltages VRP, to produce high locking signal VC_H.Comparator 404 is used for comparison latch voltage VC and negative range of voltages VRN, to produce high locking signal VC_L.Thus, clock data recovery device 20 can correctly learn latch voltage VC whether position among latch voltage scope VR.It should be noted that in another embodiment, voltage range generation unit 200 also can be realized by an analogue-to-digital conversion device with the combination of comparing unit 202.The operation principles of analogue-to-digital conversion device should be well known to those skilled in the art, and for the sake of clarity, is not repeated herein.
On the other hand, by adjusting the frequency range of clock data recovery device, clock data recovery device can be obtained working frequency range more quickly.Please refer to Fig. 5, Fig. 5 is the schematic diagram of clock data recovery device 20 another running examples shown in Fig. 2.As shown in Figure 5, the multiband voltage-controlled oscillator (VCO) VCO of clock data recovery device 20 comprises frequency range VB_1～VB_15.Wherein, frequency range VB_1～VB_15 is divided into the VBG_1～VBG_5 of frequency range group.In the time of the initial running of clock data recovery device 20, can be first by adjusting charging current, the parameter of low-frequency filter LPF or the gain of multiband voltage-controlled oscillator (VCO) VCO in current pump CP, change the frequency range of clock data recovery device 20, to increase the each self-corresponding frequency range of frequency range VB_1～VB_15.After increasing the frequency range of clock data recovery device 20, frequency range VB_1～VB_15 becomes respectively frequency range VB_1 '～VB_15 '.As shown in Figure 5, the frequency range corresponding due to frequency range VB_1 '～VB_15 ' is large compared with frequency range VB_1～VB_15, and the frequency range that therefore frequency range VB_1 '～VB_12 ' (being the VBG_1～VBG_4 of frequency range group) is corresponding comprises that frequency range VB_1～VB_15(is the VBG_1～VBG_5 of frequency range group) corresponding frequency range.In other words, increasing after the each self-corresponding frequency range of frequency range VB_1～VB_15, clock data recovery device 20 can be tested frequency range or the frequency range group of lesser amt, can obtain the corresponding frequency range of data frequency DFREQ of input traffic DATAIN by fast fetching, thereby reduce the output services spent time of frequency range VB_W.
Further, the above clock data recovery device is obtained the behavior of working frequency range, can be summarized as a control method 60.Please refer to Fig. 6, Fig. 6 is the flow chart of the control method 60 of the embodiment of the present invention.Control method 60, for supporting a clock data recovery device of multiple frequency ranges, is used for controlling clock data recovery device and in multiple frequency ranges, selects a working frequency range, and control method 60 comprises:
Step 600: start.
Step 602: receive the serial datum stream with a data frequency.
Step 604: corresponding to multiple frequency range group, wherein each frequency range group comprises at least one frequency range and corresponding to different frequency scope by multiple frequency ranges.
Step 606: in multiple frequency range group, select one first frequency range group as a coarse adjustment test frequency range group.
Step 608: in coarse adjustment test frequency range group, select one first frequency range as a coarse adjustment test frequency range.
Step 610: by this test frequency range and this data frequency, produce a coarse adjustment latch voltage.
Step 612: judge whether this coarse adjustment latch voltage is present within the scope of this latch voltage.In the time that coarse adjustment latch voltage is present within the scope of latch voltage, output coarse adjustment is tested frequency range group as this coarse adjustment frequency range group, and performs step 614; Otherwise, by coarse adjustment latch voltage and latch voltage scope, in multiple frequency range group, select one second frequency range group as this coarse adjustment test frequency range group, and perform step 608.
Step 614: in coarse adjustment frequency range group, select one the 3rd frequency range as a fine tuning test frequency range.
Step 616: test frequency range and this data frequency by fine tuning, produce a fine tuning latch voltage.
Step 618: judge whether this fine tuning latch voltage is present within the scope of this latch voltage, to export this working frequency range, in the time that this fine tuning latch voltage is present within the scope of this latch voltage, execution step 620; Otherwise, by this latch voltage and this latch voltage scope, select one the 4th frequency range as this fine tuning test frequency range, and perform step 516.
Step 620: judge whether this latch voltage scope is less than or equal to an error critical value, in the time that this latch voltage scope is less than or equal to this error critical value, execution step 622 output fine tuning test frequency ranges are working frequency range; Otherwise, dwindle latch voltage scope, and perform step 618.
Step 622: exporting this fine tuning test frequency range is this working frequency range.
Step 624: finish.
By control method 60, clock data recovery device can not need reference clock accurately, can be operated in the frequency range corresponding to data frequency the best of serial data stream.Should be noted, in control method 60, select the second frequency range and select the method for the 4th frequency range to can be the method for exhaustion, dichotomy, linear search method scheduling algorithm by this latch voltage and this latch voltage scope by coarse adjustment latch voltage and latch voltage scope, and not subject to the limits.The detailed operation of control method 60 can, with reference to aforementioned, for the sake of clarity, be not repeated herein.
In sum, need to lock with reference clock accurately or training pattern compared to known technology, the disclosed control method of above-described embodiment and clock data recovery device can not need to use reference clock accurately, can produce recovered clock accurately and correct clock recovery data.By this, the manufacturing cost of construction clock data recovery device can effectively be reduced.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (42)
1. a control method, for supporting a clock data recovery device of multiple frequency ranges, be used for controlling this clock data recovery device and in the plurality of frequency range, select a working frequency range, so that this clock data recovery device generation one is used for producing the recovered clock of clock recovery data, this control method comprises:
Reception has the serial datum stream of a data frequency;
By the plurality of frequency range, corresponding to multiple frequency range group, wherein each frequency range group comprises at least one frequency range and corresponding to different frequency scope;
By this data frequency and a latch voltage scope, in the plurality of frequency range group, select a frequency range group as a coarse adjustment frequency range group; And
By this data frequency, this latch voltage scope and this coarse adjustment frequency range group, select a frequency range as this working frequency range, to produce this recovered clock.
2. control method as claimed in claim 1, is characterized in that by this data frequency and this latch voltage scope, in the plurality of frequency range group, selects this frequency range group to comprise as the step of this coarse adjustment frequency range group:
In the plurality of frequency range group, select one first frequency range group as a coarse adjustment test frequency range group;
In this coarse adjustment test frequency range group, select one first frequency range as a coarse adjustment test frequency range;
By this test frequency range and this data frequency, produce a coarse adjustment latch voltage; And
Judge whether this coarse adjustment latch voltage is present within the scope of this latch voltage, to export this coarse adjustment frequency range group.
3. control method as claimed in claim 2, is characterized in that the corresponding frequency range of this first frequency range is the median at least one frequency range corresponding at least one frequency range in this coarse adjustment test frequency range group.
4. control method as claimed in claim 2, is characterized in that by this coarse adjustment latch voltage and this latch voltage scope, judges that whether this coarse adjustment latch voltage is present within the scope of this latch voltage, comprises with the step of exporting this coarse adjustment frequency range group:
By a ceiling voltage of this coarse adjustment latch voltage and this latch voltage scope, produce a high locking signal;
By a minimum voltage of this coarse adjustment latch voltage and this latch voltage scope, produce a low locking signal; And
By this high locking signal and this low locking signal, judge whether this coarse adjustment latch voltage is present within the scope of this latch voltage, to export this coarse adjustment frequency range group.
5. control method as claimed in claim 2, is characterized in that judging whether this coarse adjustment latch voltage is present within the scope of this latch voltage, comprises with the step of exporting this coarse adjustment frequency range group:
In the time that this coarse adjustment latch voltage is present within the scope of this latch voltage, export this coarse adjustment test frequency range group as this coarse adjustment frequency range group.
6. control method as claimed in claim 2, is characterized in that judging whether this coarse adjustment latch voltage is present within the scope of this latch voltage, comprises with the step of exporting this coarse adjustment frequency range group:
In the time that this coarse adjustment latch voltage is not present within the scope of this latch voltage, by this coarse adjustment latch voltage and this latch voltage scope, in the plurality of frequency range group, select one second frequency range group as this coarse adjustment test frequency range group.
7. control method as claimed in claim 6, is characterized in that when this coarse adjustment latch voltage is during higher than this latch voltage scope, and frequency range corresponding to this second frequency range group is higher than this frequency range corresponding to the first frequency range group.
8. control method as claimed in claim 6, is characterized in that when this coarse adjustment latch voltage is during lower than this latch voltage scope, and frequency range corresponding to this second frequency range group is lower than this frequency range corresponding to the first frequency range group.
9. control method as claimed in claim 6, is characterized in that by this coarse adjustment latch voltage and this latch voltage scope, selects this second frequency range group to comprise as the step of this coarse adjustment test frequency range group in the plurality of frequency range group:
By this coarse adjustment latch voltage and this latch voltage scope, in the plurality of frequency range group, select this second frequency range group as this test frequency range group using dichotomy.
10. control method as claimed in claim 6, is characterized in that by this coarse adjustment latch voltage and this latch voltage scope, selects this second frequency range group to comprise as the step of this coarse adjustment test frequency range group in the plurality of frequency range group:
By this coarse adjustment latch voltage and this latch voltage scope, in the plurality of frequency range group, select this second frequency range group as this test frequency range group using linear search.
11. control methods as claimed in claim 6, is characterized in that by this coarse adjustment latch voltage and this latch voltage scope, select this second frequency range group to comprise as the step of this coarse adjustment test frequency range group in the plurality of frequency range group:
By this coarse adjustment latch voltage and this latch voltage scope, look in the plurality of frequency range group and select this second frequency range group as this test frequency range group using exhaustive person ignorant of the law.
12. control methods as claimed in claim 2, is characterized in that, by this data frequency, this latch voltage scope and this coarse adjustment frequency range group, selecting this frequency range as this working frequency range, comprise with the step that produces this recovered clock:
In this coarse adjustment frequency range group, select one first frequency range as a fine tuning test frequency range;
By this fine tuning test frequency range and this data frequency, produce a fine tuning latch voltage;
Judge whether this fine tuning latch voltage is present within the scope of this latch voltage, to export this working frequency range;
And
By this working frequency range, produce this recovered clock.
13. control methods as claimed in claim 12, is characterized in that judging whether this fine tuning latch voltage is present within the scope of this latch voltage, comprises with the step of exporting this working frequency range:
In the time that this fine tuning latch voltage is present within the scope of this latch voltage, judge whether this latch voltage scope is less than or equal to an error critical value, to export this working frequency range.
14. control methods as claimed in claim 13, is characterized in that judging whether this latch voltage scope equals this error critical value, comprises with the step of exporting this working frequency range:
In the time that this latch voltage scope is less than or equal to this error critical value, exporting this fine tuning test frequency range is this working frequency range.
15. control methods as claimed in claim 13, is characterized in that judging whether this latch voltage scope equals this error critical value, comprises with the step of exporting this working frequency range:
In the time that this latch voltage scope is greater than this error critical value, dwindle this latch voltage scope.
16. control methods as claimed in claim 12, is characterized in that judging whether this fine tuning latch voltage is present within the scope of this latch voltage, comprises with the step of exporting this working frequency range:
In the time that this fine tuning latch voltage is not present within the scope of this latch voltage, by this latch voltage and this latch voltage scope, select one second frequency range as this fine tuning test frequency range.
17. control methods as claimed in claim 16, is characterized in that when this fine tuning latch voltage is during higher than this latch voltage scope, and frequency range corresponding to this second frequency range is higher than frequency range corresponding to this first frequency range.
18. control methods as claimed in claim 16, is characterized in that when this fine tuning latch voltage is during lower than this latch voltage scope, and frequency range corresponding to this second frequency range is lower than frequency range corresponding to this first frequency range.
19. control methods as claimed in claim 2, is characterized in that by this data frequency and this latch voltage scope, in the plurality of frequency range group, select this frequency range group separately to comprise as the step of this coarse adjustment frequency range group:
Adjust serial data frequency range corresponding to each frequency range.
20. control methods as claimed in claim 19, is characterized in that the step by adjusting serial data frequency range corresponding to each frequency range comprises:
By changing in current value, the frequency range of a low pass filter and the yield value of a voltage controlled oscillator of charging current of a charge pump at least one, adjust serial data frequency range corresponding to each frequency range.
21. 1 kinds of clock data recovery devices, comprising:
One phase detector, one of a data frequency that is used for flowing by serial datum and a recovered clock recovered frequency and produced a detecting phase signal, and produces recovery data by this serial data stream and this recovered clock;
One charge pump, is coupled to this phase detector, is used for producing a current signal by this detecting phase signal;
One low pass filter, is coupled to this charge pump, is used for producing a latch voltage according to this current signal;
One multi-band voltage-controlled oscillator, is coupled to this low pass filter, in order to by a Frequency Band Selection signal, operates in the working frequency range in multiple frequency ranges, and exports this recovered clock according to this latch voltage and this working frequency range;
One voltage range generation unit, by a scope control signal, produces a latch voltage scope;
One comparing unit, be coupled to this voltage range generation unit and this low pass filter, be used for by a ceiling voltage of this latch voltage and this latch voltage scope, export a high locking signal, and by a minimum voltage of this latch voltage and this latch voltage scope, output one low locking signal; And
One control module, be coupled to this comparing unit, this charge pump, this voltage range generation unit and this multi-band voltage-controlled oscillator, be used for, by this latch voltage, this latch voltage scope, this high locking signal and this low locking signal, exporting this Frequency Band Selection signal and this scope control signal.
22. clock data recovery devices as claimed in claim 21, is characterized in that this voltage range generation unit is a digital to analog converter.
23. clock data recovery devices as claimed in claim 21, is characterized in that this voltage range generation unit and this comparing unit are combined as an analog-to-digital converter.
24. clock data recovery devices as claimed in claim 21, it is characterized in that this control module by the plurality of frequency range corresponding to the multiple frequency range of difference group, each frequency range group comprises at least one frequency range and corresponding to different frequency scope, and by this latch voltage, this high locking signal and this low locking signal, in the plurality of frequency range group, select a frequency range group as a coarse adjustment frequency range group, finally by this latch voltage, this high locking signal and this low locking signal, from this coarse adjustment frequency range group, select a frequency range as this working frequency range.
25. clock data recovery devices as claimed in claim 24, is characterized in that this control module is in the plurality of frequency range group, select one first frequency range group as a coarse adjustment test frequency range group; In this coarse adjustment test frequency range group, select one first frequency range as a coarse adjustment test frequency range; And judge corresponding to this latch voltage of this coarse adjustment test frequency range whether be present within the scope of this latch voltage by this high locking signal and this low locking signal, to export this coarse adjustment frequency range group.
26. clock data recovery devices as claimed in claim 25, is characterized in that the corresponding frequency range of this first frequency range is the median at least one frequency range corresponding at least one frequency range in this coarse adjustment test frequency range group.
27. clock data recovery devices as claimed in claim 25, while it is characterized in that within this latch voltage is present in this latch voltage, this control module is exported this coarse adjustment test frequency range group as this coarse adjustment frequency range group.
28. clock data recovery devices as claimed in claim 25, while it is characterized in that within this latch voltage is not present in this latch voltage, this control module is by this high locking signal and this low locking signal, in the plurality of frequency range group, selects one second frequency range group as this coarse adjustment test frequency range group.
29. clock data recovery devices as claimed in claim 28, is characterized in that in the time that this high locking signal is indicated this latch voltage higher than this latch voltage scope, and frequency range corresponding to this second frequency range group is higher than this frequency range corresponding to the first frequency range group.
30. clock data recovery devices as claimed in claim 28, is characterized in that in the time that this low locking signal is indicated this latch voltage lower than this latch voltage scope, and frequency range corresponding to this second frequency range group is lower than this frequency range corresponding to the first frequency range group.
31. clock data recovery devices as claimed in claim 28, is characterized in that this control module is by this high locking signal and this low locking signal, select this second frequency range group as this coarse adjustment test frequency range group using dichotomy in the plurality of frequency range group.
32. clock data recovery devices as claimed in claim 28, it is characterized in that this control module is by this high locking signal and this low locking signal, in the plurality of frequency range group, select this second frequency range group as this coarse adjustment test frequency range group using linear search.
33. clock data recovery devices as claimed in claim 28, it is characterized in that this control module is by this high locking signal and this low locking signal, look in the plurality of frequency range group and select this second frequency range group as this coarse adjustment test frequency range group using exhaustive person ignorant of the law.
34. clock data recovery devices as claimed in claim 24, is characterized in that this control module is in this coarse adjustment frequency range group, select one first frequency range as a fine tuning test frequency range; And judge by this high locking signal and this low locking signal whether this latch voltage producing by this fine tuning test frequency range and this data frequency is present within the scope of this latch voltage, to export this working frequency range.
35. clock data recovery devices as claimed in claim 34, while it is characterized in that within this latch voltage is present in this latch voltage, this control module judges by this scope control signal whether this latch voltage scope is less than or equal to an error critical value, to export this working frequency range.
36. clock data recovery devices as claimed in claim 35, is characterized in that in the time that this latch voltage scope is less than or equal to this error critical value, and it is this working frequency range that this control module is exported this fine tuning test frequency range.
37. clock data recovery devices as claimed in claim 35, is characterized in that in the time that this latch voltage scope is greater than this error critical value, and this control module, by adjusting this scope control signal, is dwindled this latch voltage scope.
38. clock data recovery devices as claimed in claim 34, while it is characterized in that within this latch voltage is not present in this latch voltage, this control module, by this high locking signal and this low locking signal, selects one second frequency range as this fine tuning test frequency range.
39. clock data recovery devices as claimed in claim 38, is characterized in that in the time that this high locking signal is indicated this latch voltage higher than this latch voltage scope, and frequency range corresponding to this second frequency range is higher than frequency range corresponding to this first frequency range.
40. clock data recovery devices as claimed in claim 38, is characterized in that in the time that this low locking signal is indicated this latch voltage lower than this latch voltage scope, and frequency range corresponding to this second frequency range is lower than frequency range corresponding to this first frequency range.
41. clock data recovery devices as claimed in claim 20, is characterized in that the another output of this control module one frequency range control signal, to adjust frequency range corresponding to each frequency range.
42. clock data recovery devices as claimed in claim 41, it is characterized in that the another output of this control module one frequency range controls signal in this charge pump, this low pass filter and this multi-band voltage-controlled oscillator at least one, to adjust frequency range corresponding to each frequency range.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261717612P | 2012-10-23 | 2012-10-23 | |
| US61/717,612 | 2012-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103780251A true CN103780251A (en) | 2014-05-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310019747.7A Pending CN103780251A (en) | 2012-10-23 | 2013-01-18 | Control method for selecting frequency band and related clock data recovery device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103780251A (en) |
| TW (1) | TW201417550A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI608721B (en) * | 2015-12-29 | 2017-12-11 | 安南帕斯公司 | Bidirectional communication method and bidirectional communication apparatus using the same |
| CN108880534A (en) * | 2018-06-11 | 2018-11-23 | 清华大学 | The clock and data recovery lock detecting circuit of bandwidth varying is adapted in a kind of high-speed serial communication |
| CN109391262A (en) * | 2017-08-03 | 2019-02-26 | 联咏科技股份有限公司 | Timing recovery device and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04322532A (en) * | 1991-04-22 | 1992-11-12 | Matsushita Electric Ind Co Ltd | Clock recovery circuit |
| US20050174185A1 (en) * | 2004-02-10 | 2005-08-11 | Steinbach Guntor W. | Centering a multi-band voltage controlled oscillator |
| US7164322B1 (en) * | 2005-07-21 | 2007-01-16 | Agilent Technologies, Inc. | Establishing a tuning signal window for use in centering a multi-band voltage controlled oscillator |
| US20070173219A1 (en) * | 2006-01-24 | 2007-07-26 | Samsung Electronics Co., Ltd. | Phase locked loop and method thereof |
| US20070183552A1 (en) * | 2006-02-03 | 2007-08-09 | Sanders Anthony F | Clock and data recovery circuit including first and second stages |
| CN101394181A (en) * | 2008-09-24 | 2009-03-25 | 硅谷数模半导体（北京）有限公司 | Time clock and data recovery circuit and integrated chip having the circuit |
-
2013
- 2013-01-07 TW TW102100434A patent/TW201417550A/en unknown
- 2013-01-18 CN CN201310019747.7A patent/CN103780251A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04322532A (en) * | 1991-04-22 | 1992-11-12 | Matsushita Electric Ind Co Ltd | Clock recovery circuit |
| US20050174185A1 (en) * | 2004-02-10 | 2005-08-11 | Steinbach Guntor W. | Centering a multi-band voltage controlled oscillator |
| US7164322B1 (en) * | 2005-07-21 | 2007-01-16 | Agilent Technologies, Inc. | Establishing a tuning signal window for use in centering a multi-band voltage controlled oscillator |
| US20070173219A1 (en) * | 2006-01-24 | 2007-07-26 | Samsung Electronics Co., Ltd. | Phase locked loop and method thereof |
| US20070183552A1 (en) * | 2006-02-03 | 2007-08-09 | Sanders Anthony F | Clock and data recovery circuit including first and second stages |
| CN101394181A (en) * | 2008-09-24 | 2009-03-25 | 硅谷数模半导体（北京）有限公司 | Time clock and data recovery circuit and integrated chip having the circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI608721B (en) * | 2015-12-29 | 2017-12-11 | 安南帕斯公司 | Bidirectional communication method and bidirectional communication apparatus using the same |
| CN109391262A (en) * | 2017-08-03 | 2019-02-26 | 联咏科技股份有限公司 | Timing recovery device and method |
| CN109391262B (en) * | 2017-08-03 | 2022-09-13 | 联咏科技股份有限公司 | Clock recovery device and method |
| CN108880534A (en) * | 2018-06-11 | 2018-11-23 | 清华大学 | The clock and data recovery lock detecting circuit of bandwidth varying is adapted in a kind of high-speed serial communication |
| CN108880534B (en) * | 2018-06-11 | 2021-05-04 | 清华大学 | Clock data recovery locking detection circuit adapting to variable bandwidth in serial communication |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201417550A (en) | 2014-05-01 |
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Application publication date: 20140507 |