CN103780247A - Circuit for controlling output stage reactive current to generate offset voltage - Google Patents

Abstract

The invention discloses a circuit for controlling an output stage reactive current to generate an offset voltage. A rail-to-rail output stage is provided. The output stage can offset the non-linear component in the transconductance of a transistor for the output stage so that the reactive current in the output stage is allowed to be controlled by an external current source and an apparatus specification ratio, and the reactive current in the output stage can be independent from a manufacturing process, temperature and a power supply voltage and be maintained. The output stage receives an input signal and an offset voltage from an external power supply, and correspondingly a promotion current for supplying a current to a load and a traction current for leading the current out from the load are generated. When the promotion current matches the traction current, the output stage can be called "reactive". The offset voltage controls the reactive current. Through simulating a voltage and a current which are generated by the output stage employing a similar element, an offset voltage generation circuit can provide an offset voltage so that a reactive point can be independent from a manufacturing process, temperature and a power supply voltage and be maintained.

Description

A kind of circuit that produces bias voltage to controlling output stage reactive current

Technical field:

The circuit of track to track output stage and the method for providing is provided.More particularly, the present invention relates to circuit and the method for track to track output stage, this output stage can provide high linearity in the situation that not using feedback, in its mutual conductance, provide high linearity, can consider the reactive current of being controlled by designer, and can provide those to be controlled by designer, the reactive current that not affected by manufacturing process, temperature and supply voltage.

Background technology:

Track to track output stage is widely known in the prior art.Typical track to track output stage is combined the common source of two polarity complementations (or common emitter) transistor, transistorized drain electrode (or collector electrode) links together, form an output node that is connected to load, transistorized source electrode (or emitter) is connected on a forward and reverse electrical source voltage, and transistorized grid (or base stage) is connected on two driving signals that replace from external input signal.These output stages are very useful, and the drift ability of their maximization circuit output signal voltage, makes it to approach the limit of power supply, and therefore provide maximum signal to noise ratio to given noise level.

But many known circuit that track to track output stage is provided and method have been shown the non-linear transfer characteristic that is input to output.These are non-linear is input to output characteristic and conventionally can causes the distortion of signal, especially can revise under the high frequency situations of output stage nonlinearity by negative feedback in limited loop gain.Therefore, do not use feedback just in these output stages, to provide high linearity extremely to need.

In track to track output stage, conventionally also need to maintain one known, flow through the each transistorized reactive current of output stage.Reactive current is when output stage is neither to the load Injection Current that is connected to output node, during also not from this load Absorption Current, and the electric current flowing through in transistor.By maintaining the reactive current in output stage transistor, the intermodulation distortion in output stage just can remain on minimum value.But because be applied to the variation of manufacturing process, temperature and the supply voltage of the element of output stage, this reactive current is very rambunctious.

Summary of the invention:

Described in above, an object of the present invention is to provide the track to track output stage that reaches high linearity.

Another object of the present invention is to provide the track to track output stage that reaches high linearity in mutual conductance.

Another object of the present invention is to provide the track to track output stage of the reactive current of considering that designer controls.

Another object of the present invention is to provide the track to track output stage that does not use feedback just to reach high linearity.

Another object of the present invention is to provide the track to track output stage that allows reactive current to be independent of manufacturing process, temperature and supply voltage.

Technical solution of the present invention:

According to the present invention, can provide circuit and the method for the track to track output stage that reaches these or other object.More particularly, the track to track output stage that circuit of the present invention and method provide has been eliminated unintentional nonlinearity degree in output stage transistor mutual conductance, allow reactive current in output stage to be controlled by current source and device specification ratio, and make the reactive current in output stage can be independent of manufacturing process, temperature and supply voltage and be maintained.

In general,, on functional level, form output stage according to the present invention and comprise that a pair transistor supplements branch road, a current mirroring circuit and an output driving circuit.These circuit are all arranged, and like this, an input signal is supplied with pair transistor and supplemented branch road and output driving circuit.Also having a bias voltage to be connected in pair transistor supplements on branch road.Pair transistor supplements branch road and output driving circuit is also likely connected on voltage source.Pair transistor supplementary circuitry drive current mirror circuit.Current mirroring circuit is also connected on another voltage source.Current mirroring circuit and output driving circuit share a terminal being connected in load.This load is also connected on earth terminal, and what the electromotive force that this earth terminal has was conventionally the voltage that provided by two voltage sources is poor.

In operation, the first-selected output stage forming according to the present invention receives an input signal from external power source, receives a bias voltage from bias generator, as follows described in this process.Output driver can produce one and promote electric current supply load, responds above-mentioned input signal.Pair transistor supplements branch road can supply with current mirror by branch current, responds the voltage difference being produced by above-mentioned input signal and bias voltage.Match with this branch current, after current mirror, from load, pull out traction current.When the promotion electric current by output driver supply load with from load, draw while matching into the traction current of current mirror because mobile net current is zero in load, output stage is just called as " idle ".Load circuit is commonly called mutual conductance to applied signal voltage corresponding.

Promote electric current when output driver at least provides some, current mirror at least draws some traction currents, and output stage of the present invention will provide the mutual conductance of a substantial linear.This linear transconductance is received by output stage, and output stage matches with the non-linear component that promotes path mutual conductance, and has certain elimination, matches with the non-linear component of traction path mutual conductance.When providing one, enough strong voltage is as input signal, and one that promotes in electric current or traction current will stop flowing.Once one in both stops flowing, output stage will stop eliminating the non-linear component of output signal, the substitute is and enters the improved AB generic operation of effect.

Output stage of the present invention also may comprise bias voltage generating circuit, and producing with this can be as the voltage of output stage biased voltage.The transistor voltage electric current that this bias voltage generating circuit produces while being operated in by simulation at idle by output stage, produces needed bias voltage.Therefore, the reactive current in output stage just can arrange according to device specification ratio and reference current source.Bias voltage generating circuit is that track to track output stage produces bias voltage, and like this, required reactive current will produce in output stage, and is independent of manufacturing process, temperature and the supply voltage of synthetic circuit.

Contrast patent documentation: CN201430578U bias voltage circuit and electronic equipment 200920146151.2

Accompanying drawing explanation:

Of the present invention above-mentioned with and other objects and advantages be next described later in detail, and in conjunction with relevant indicators, wherein refer to the components and parts of a full piece of writing with reference to characteristic, wherein:

Figure 1 shows that the schematic diagram of the known structure of pair of output transistors in track to track output stage;

Figure 2 shows that according to the schematic diagram of the illustrative example of a track to track output stage of the present invention;

Figure 3 shows that input signal V in key diagram 2 _iNwith promotion electric current I _p, traction current I _nwith output current I _oUTbetween the curve chart of voltage-current relationship;

Figure 4 shows that according to the schematic diagram of the second illustrative example of track to track output stage of the present invention, the input signal of this output stage drives a nmos fet (FET);

Figure 5 shows that, according to the schematic diagram of the 3rd illustrative example of track to track output stage of the present invention, this output stage is combined bipolar transistor (BJT);

Figure 6 shows that one provides required bias voltage (V according to of the present invention _bIAS) the schematic diagram of illustrative example of biasing circuit.

Embodiment:

According to the present invention, provide the circuit of track to track output stage and method apparent.Track to track output stage of the present invention can, by mating and eliminate the nonlinearity of large-signal mutual conductance intrinsic in output stage transistor, in the situation that not using feedback, obtain high linearity.The design control of reactive current in these track to track output stages, is promoted by obtain reactive current from device specification ratio and reference current.

For notional convenience, the current-voltage equation of saturated FET here represents with the threshold voltage of agreement, wherein threshold voltage parameter (" V _t") FET of N channel enhancement and P-channel enhancement type is had to positive role.In addition, not being represented as the voltage between pair of terminal, is with reference to the unnecessary earth terminal marking.

Fig. 1 has shown the structure 20 of pair of output transistors in a known track to track output stage.As shown in the figure, structure 20 comprises PMOS FET22 and NMOS FET24, and both drain electrodes 26 and 28 connect together, and is jointly connected in load 30, and their source electrode 32 and 34 is connected on respectively V _dDand V _sS(negative rail and positive track) is upper, and their grid 40 and 42 is connected to P and drives input 44 and N to drive in input 46.Load 30 ground connection, its electromotive force is conventionally between V _dDand V _sS.For the transistor of Drive Structure 20, in load 30, can produce an electric current, driving voltage must be applicable to input 44 and 46.When driving voltage is added on input 44, the source electrode of FET22 is to grid voltage (V _sG) exceed its PMOS threshold voltage (V _tP), drain electrode 26 just has outflow of bus current.This electric current by the source electrode of FET22 to grid voltage control.When driving voltage is added on input 46, the grid of FET24 is to source voltage (V _gS) exceed its NMOS threshold voltage (V _tN), drain electrode 28 just has electric current and flows into.This electric current by the source electrode of FET24 to grid voltage control.

In load 30, be to flow out drain electrode 26 and flow into drain electrode 28 difference between currents by FET22 and 24 total currents that produce.Therefore, exceed when flowing out the electric current of drain electrode 26 electric current that flows out drain electrode 28, load 30 just has outflow of bus current and flows to ground 31.Be less than when flowing out the electric current of drain electrode 26 electric current that flows into drain electrode 28, in load 30, will flow through the electric current from ground 31.Finally, when flowing out drain electrode 26 electric current and equal to flow out the electric current of drain electrode 28, output stage is just considered to be in its idle point, does not have electric current to flow through load 30.At idle some place, the electric current of the electric current of outflow drain electrode 26 and inflow drain electrode 28 is known as the reactive current (I of FET22 and 24 _q).

Fig. 2 has shown according to of the present invention, and high linearity and designer are provided the electric current of controlled reactive current.As shown in the figure, output stage 60 comprises a PMOS FET62 and a NMOS FET64, and their drain electrode links together, and is attempted by load 66, and their source electrode is connected on respectively V _dDand V _sSon.NMOS FET72 also comprises an output stage, and has formed a current mirror 74 with NMOS FET64, and NMOS FET76 has formed a pair transistor and supplemented branch road 80 together with NMOS FET78.The grid of FET64 is connected in the grid of FET72 and the drain electrode of drain electrode and FET78.The source electrode of FET72 is connected on V _sSon.The source electrode of FET78 and body end (in order to eliminate body effect) are connected on the source electrode of FET76.The drain electrode of FET76 is connected on V _dDon.The grid of PMOS FET62 and NMOS FET76 is by V _iNdrive, the grid of PMOS FET78 is connected to V _bIASon.

Current mirror 74 is to approach its input current I for return to one at its end ₁m times of electric current I _n, NMOS FET64 is made up of M identical NMOS FET72 parallel connection well, and is placed on the place very close with FET72, can make like this temperature contrast minimize.

For the purpose of illustrating, Fig. 2 and Fig. 4 afterwards, 5,6 have shown the example of the integrated circuit of making based on N trap COMS manufacturing process.Therefore, in these figure, the P type substrate of shown integrated circuit in the dark with V _sSconnect, connect in the PMOS transistor clearly not showing at trap (" substrate "), substrate is just connected to V _dDon.In Fig. 2, the body end of FET78 is connected to source terminal, has eliminated the impact of substrate-source voltage when FET78 reaches threshold voltage.All circuit described herein also can use P well or other CMOS technique in application, or according to of the present invention, have the N well technique connecting from PMOS substrates different in figure.

Although circuit 60 has used PMOS and NMOS FET62,64,72,76 and 78, people can find these elements can be with the FET of opposed polarity, there is the replacements such as identical or the BJT of opposed polarity.Equally, although not explanation, the drain current of FET76 can pass through at V _dDand the method for inserting resistance and so between FET62 source electrode and FET76 drain junction, is resumed and is incorporated to I _oUT.

The course of work of output stage 60 is as follows.Load 66 is by V _iNand V _bIASgeneration current I under the control of input is provided _oUT.I _oUTfor promoting electric current I _p(being provided by FET62 drain electrode) and traction current I _n(being provided by FET64 drain electrode) poor.Just as the electric current that in Fig. 1, FET22 drain electrode is flowed out, electric current I _pby V _iNdirectly control, and be V _dDand V _iNthe function of the difference of voltage.

Unlike the electric current that in Fig. 1, FET24 drain electrode flows into, flow into the electric current I of FET64 drain electrode _nnot directly actuated by single, special input.On the contrary, electric current I _nsignal V _iNand V _bIASthe function of sum.According to V _iNand V _bIASthe voltage at place, electric current I ₁flow through branch road 80.In following detailed description, the action of branch road 80 is similar to a NMOS FET, and its threshold voltage is by V _bIAScontrol, transconductance factor is the combination of FET76 and 78.Electric current I ₁the also FET72 of current flowing mirror 74.According to the current ratio of current mirror 74, electric current I _nto flow through the electric current I of FET72 ₁speed doubly of M flow into the drain electrode of FET64.

Fig. 3 has shown performance high linearity of the present invention and the reactive current that designer is controlled.Fig. 3 has shown as V _iN(Fig. 2) locate the electric current I of the function of input signal _p, I _nand I _oUT.As can be seen from Figure 3, I _pand I _nin input voltage range, show as non-linear.Because each FET is operated in saturation condition, electric current I in the time opening in Fig. 2 _pand I _njust there is square law relationship.For NMOS FET, for example FET64 in Fig. 2, this square law relationship is arithmetically being approximately:

(1), I wherein _nfor the drain current of the NMOS FET that defines in Fig. 2, K _nfor transconductance factor, V _gSNfor grid-source voltage, V _tNfor threshold voltage.For PMOS FET.The for example FET62 in Fig. 2, the threshold voltage of the agreement of describing before using, this square law relationship is arithmetically being approximately:

(2), I wherein _pfor the drain current of the PMOS FET that defines in Fig. 2, K _pfor transconductance factor, V _sGPfor source electrode-grid voltage, V _tPfor threshold voltage.

In order to improve the accuracy of the equation relevant with Fig. 2 (1) and (2), clearly, for PMOS FET62, I _pcan also use the Representation Equation below: I _p=K _p(V _dD-V _iN-V _tP) ², or equation (3) can be by following expression (3): $I_P=K_P{V}_{\mathrm{DD}}^2-2K_P{V}_{\mathrm{DD}}{V}_{\mathrm{IN}}-2K_P{V}_{\mathrm{DD}}{V}_{\mathrm{TP}}+K_P{V}_{\mathrm{IN}}^2+2K_P{V}_{\mathrm{IN}}{V}_{\mathrm{TP}}+K_P{V}_{\mathrm{TP}}^2---\left(4\right).$

Same, use V _iNform represent electric current I _n, the characteristic of the topological structure of output stage 60 and branch road 80 and current mirror 74 just need to be taken into account.The first, observe the topological structure of output stage 60, clearly, the grid-source voltage V of FET76 _gS76add source electrode-grid voltage V of FET78 _sG78equal applied signal voltage V _iNdeduct bias voltage V _bIAS.This relation can represent with equation below: V _gS76+ V _sG78=V _iN-V _bIAS(5).

In addition, because flow into the electric current I of FET76 drain electrode _d76with the electric current I that flows out FET78 drain electrode _d78identical, I ₁can be represented by relation below: I ₁=I _d76=I _d78(6).

Under square law relationship, the electric current in FET76 can be similar to equation below: I _d76=K ₇₆(V _gS76-V _t76) ²(7).Wherein K ₇₆for the transconductance factor of FET76, V _gS76grid-source voltage, V _t76it is threshold voltage.Equation (7) can also be represented as: V _gS76=V _t76+ (I _d76/ K ₇₆) ^1/2(8).

Similarly, under square law relationship, the electric current in FET78 can be similar to equation below: I _d78=K ₇₈(V _sG78-V _t78) ²(9).Wherein K ₇₈for the transconductance factor of FET78, V _sG78source electrode-grid voltage, V _t78it is threshold voltage.Equation (9) can also be represented as: V _sG78=V _t78ten (I _d78/ K ₇₈) ^1/2(10).

Separate I in conjunction with equation (5), (6), (8) and (10) ₁, clearly, I ₁can represent with equation below: I ₁=K _c(V _iN-V _bIAS-V _t76-V _t78) ²(11), wherein, K _cthe transconductance factor that represents branch road 80, is defined by equation below: K _c=1/ (1/K ₇₆ ^1/2+ 1/K ₇₈ ^1/2) ²(12).

Because I _ncurrent ratio factor M by electric current in FET72 and current mirror 74 determines in proportion, and because the electric current in FET72 equals the electric current I in branch road 80 ₁so, electric current I _ncan be by the Representation Equation below: I _n=MI ₁=MK _c(V _iN-V _bIAS-V _t76-V _t78) ², or be expressed as (13): $\begin{array}{c}{I}_N={\mathrm{MK}}_C{V}_{\mathrm{IN}}^2-2{\mathrm{MK}}_C{V}_{\mathrm{IN}}{V}_{\mathrm{BIAS}}-2{\mathrm{MK}}_C{V}_{\mathrm{IN}}{V}_{T76}-2{\mathrm{MK}}_C{V}_{\mathrm{IN}}{\mathrm{<figure-callout\; id="78"\; label="V\; T"\; filenames="HDA0000422662690000021.png"\; state="\{\{state\}\}">V</figure-callout>}}_T+{\mathrm{MK}}_C{V}_{\mathrm{BIAS}}^2+\\ 2{\mathrm{MK}}_C{V}_{\mathrm{BIAS}}{V}_{\mathrm{<figure-callout\; id="76"\; label="T"\; filenames="HDA0000422662690000021.png"\; state="\{\{state\}\}">T</figure-callout>}76}+2{\mathrm{MK}}_C{V}_{\mathrm{BIAS}}{V}_{\mathrm{<figure-callout\; id="78"\; label="T"\; filenames="HDA0000422662690000021.png"\; state="\{\{state\}\}">T</figure-callout>}78}+{\mathrm{MK}}_{\mathrm{<figure-callout\; id="76"\; label="C\; V\; T"\; filenames="HDA0000422662690000021.png"\; state="\{\{state\}\}">C</figure-callout>}}{V}_T^{}{76}_2^{}+2{\mathrm{MK}}_C{V}_{T76}{\mathrm{<figure-callout\; id="78"\; label="V\; T"\; filenames="HDA0000422662690000021.png"\; state="\{\{state\}\}">V</figure-callout>}}_T+{\mathrm{MK}}_C{V}_{\mathrm{<figure-callout\; id="78"\; label="T"\; filenames="HDA0000422662690000021.png"\; state="\{\{state\}\}">T</figure-callout>}78}^2\end{array}---\left(14\right).$

Mention equation (4) above, clearly,

i _pin unique non-linear composition because V _dDand V _tPbe independent of V _iN.Similarly, clearly,

i _nin unique non-linear composition because V _bIAS, V _t76and V _t78be independent of V _iN.

For from V _iNto V _oUTmiddle acquisition high linearity, eliminates I _pand I _nin non-linear composition just very important.As described above, I _oUTjust I _pand I _npoor, by the Representation Equation be: I _oUT=I _p-I _n(15).

Therefore, eliminate I _pand I _nin non-linear composition can be by mating and eliminating I _pand I _ntwo non-linear compositions complete.In order to reach this object, just must meet equation below:

(16), that is: K _p=MK _c(17).

Therefore be, K by choosing mutual conductance _pfET62, mutual conductance is respectively K ₇₆and K ₇₈fET76 and 78 combination, like this, a combination mutual conductance K _cand the current mirror 74 being made up of FET64 and 72 just has current ratio M, like this, equation (17) is just met, output current I _oUTwill be V _iNlinear function.

Although V _iN-I _oUTprimary nonlinearity in relation can be eliminated by constraint equation (17) by output stage 60, but is to provide reactive current I _q(work as I _oUTbe the electric current of 1 o'clock inflow device 62 and 64) designability still very important.

In Fig. 2, V _iN-I _oUTconnected by two discrete path: the upper pathway (I that flows through PMOS device 62 _p) and flow through the lower path (I of other devices _n).As shown in Figure 3, discrete non-linear large-signal V _iN-I _oUTthis two paths of curve controlled, although the non-linear partial of these curves is at I _oUTin eliminated.Article two, curve intersection is in point 94, I herein _pequal I _n, current value is I _q, be reactive current.I _pand I _nthe intersection point of curve is positioned at V _iNparticular value place, be called as " V here _iNQ".

Voltage V in Fig. 2 _bIAScan be used for arranging reactive current value I _q.This is because easily known V by Fig. 2 circuit and equation (13) _bIASoffset V _iNat V _non impact.That is to say, work as V _bIASpositively biased or when reverse-biased, V _iNjust need to obtain an I _nwith onesize positively biased respectively or value reverse-biased and that change.In Fig. 3, the impact of this part makes I _ncurve moves to left respectively or moves to right.V _bIASmake I _ncurve movement and do not make I _pcurve movement, is expressed as equation (3) on mathematics.Therefore, change V _bIAScan change intersection point electric current I _qand corresponding voltage V _iNQ.

The Input output Relationship of analyzing output stage 60 has represented V very clearly _iNQand I _qwith V _bIASthe independence changing, V _bIASvalue caused a required I _qvalue, corresponding V _iNQvalue, and I _oUTand V _iNsimple relation.By equation (3) and (13) and V _tC=V _t76+ V _t78, I _oUTcan be by the Representation Equation below: I _oUT=I _p-I _n=K _p(V _dD-V _iN-V _tP) ²-MK _c(V _iN-V _bIAS-V _tC) ²(18).

Use according to the linear conditions before equation (17) and eliminate factor MK _c, the form after rearrangement is: I _oUT=K _p[(V _dD-V _tP) ²-(V _bIAS+ V _tC) ²-2V _iN(V _dD-V _tP-V _bIAS-V _tC)] (19).

This I _oUTat particular value V _iNplace is zero, is called V _iNQ.According to condition I _oUT=0 solves: V _iNQ=(V _dD-V _tP+ V _bIAS+ V _tC)/2(20), reactive current I _qat V _iN=V _iNQtime equal I _p(or I _n) value, can be expressed as: I _q[K _p(V _dD-V _tP-V _bIAS-V _tC) ²]/4(21).

Last a kind of form can by arrangement meet obtain to reactive current I _qrequired V _bIASvalue: V _bIAS=V _dD-V _tP-V _tC-2 (I _q/ K _p) ^1/2(22).Such voltage can use similar transistorized V _bIASin generative circuit, obtain, as shown below, this V _bIASthe output of circuit for generating can drive many output stages 60 simultaneously.

When application has the V of this value _bIAStime, input reactive voltage V _iNQbe just: V _iNQ=V _dD+ V _tP-(I _q/ K _p) ^1/2(23).

As V suitable in equation (22) and that meet the linear conditions of equation (17) _bIASbe applied in output stage 60, the Input output Relationship of equation (19) can be reduced to (result before using): I _oUT=-4 (K _pi _q) ^1/2(V _iN-V _iNQ) (24).

As long as the FET in output stage 60 is in normal strong oppositely saturation condition, especially conduction state, equation (24) is exactly effective.Had constraint above, equation (24) is exactly a general large-signal model, but is not the common inearized model based on negligible signal drift.This is main advantage of the present invention.The linear conditions K of equation (17) _p=MK _cbe easy to meet, because its specification with four different factors: FET76 (becomes the K in equation (12) ₇₆, and the K obtaining thus _c); The specification of FET78 (becomes the K in equation (12) ₇₈, and the K obtaining thus _c); The FET72 obtaining than M via image current and 64 specification ratio; Via factor K _pthe specification of the FET62 obtaining.

Eliminate electric current I in order to make output stage 60 by said process _pand I _nin non-linear composition, FET62 and 64 all must conduction, therefore, output stage 60 must be in A level work pattern.Once a cut-off in FET62 or 64, the Nonlinear elimination characteristic of output stage 60 just no longer works, and therefore, output stage 60 departs from A level work pattern, enters AB level work pattern, and effect also gets a promotion.

An optional example of output stage 60 is illustrated by the output stage 100 in Fig. 4.In output stage 100, V _iNdrive the PMOS FET that in a NMOS FET102 rather than Fig. 2, output stage 60 is used.

Just as output stage 60, output stage 100 comprises NMOS FET102 and PMOS FET104, and its drain electrode connects together and is connected in load 106, and source electrode is connected to V _sSand V _dDon.Load 106 is also connected on ground 107, and its electromotive force is conventionally between V _dDand V _sS.Electric current I in load 106 _oUTfor flowing out the I of FET104 drain electrode _pwith the I that flows into FET102 drain electrode _n poor.Output stage 100 also comprises PMOS FET112, forms 1:M current mirror 114 with PMOS DET104, and PMOS FET116 and NMOS FET118 jointly form pair transistor and supplement branch road 120.As shown in FIG., the grid of FET104 is connected in the grid of FET112 and the drain electrode of drain electrode and FET118.The source electrode of FET112 is connected to V _dDon.The source electrode of FET188 is connected on the source electrode of FET116, is also connected on the body end of FET116 (in order to eliminate body effect).The drain electrode of FET116 is connected to V _sSon.The grid of NMOS FET102 and PMOS FET116 is by V _iNdrive, the grid of NOMS FET118 is connected to V _bIASon.

Although circuit 100 comprises PMOS and NOMS FET102,104,112,116,118, people can find these devices can be by the FET of opposed polarity, have identical or the BJT of opposed polarity replaces.Equally, although not explanation, the drain current of FET116 can pass through at V _sSand the method for inserting resistance and so between FET102 source electrode and FET116 drain junction, is resumed and is incorporated to I _oUT.

Output stage 100 is that a N-P of output stage 60 in Fig. 2 supplements or inverted change example.The work of circuit 60 and 100 is all fours, has used the PMOS that replaces NMOS device, and vice versa.The analysis classes that output stage 100 is worked is similar to output stage 60, has following main conclusions.For notional convenience, as shown in Figure 2, saturated FET current-voltage equation is here explained, like this, threshold voltage the parameter (" V of NMOS and PMOS in FET _t") device of amplification mode is had to positive role.Parameter K _nand V _tNrepresent the characteristic of output driving N MOS FET102.Pair transistor supplements branch road 120, just as similar branch road 80 in Fig. 2, has complex parameter V _tCand K _c, definition is: V _tC=V _t118+ VT ₁₁₆(25), K _c=1/ (1/K ₁₁₈ ^1/2+ 1/K ₁₁₆ ^1/2) ²(26).

In the time that condition is below satisfied, electric current I _pand I _nin be V _iNthe composition of nonlinear function is at I _oUTin offset: K _n=MK _c(27).

In the time that this condition meets, at I _pand I _nthe required V of reactive current obtaining is expected in middle acquisition _bIASvalue: V _bIAS=V _sS+ V _tN+ V _tC+ 2 (I _q/ K _n) ^1/2(28).

As this V _bIASvalue when being employed, V _iNcorresponding idle value is just V _iNQ, wherein: V _iNQ=V _sS+ V _tN+ (I _q/ K _n) ^1/2(29), the input and output of entirety are expressed as: I _oUT=-4 (K _pi _q) ^1/2(V _iN-V _iNQ) (30).

Fig. 5 has shown the output stage 150 being made up of bipolar transistor (BJT) according to the present invention.Function, output stage 150 works together and is similar to the output stage 100 in Fig. 4.Although output stage 150 comprises BJT166,170,176 and 168, and FET190,192 and 194, some of output stage 150 or all BJT can be replaced by identical or the FET of opposed polarity in application process, and some or whole FET can be replaced by identical or the BJT of opposed polarity.In addition, although Fig. 5 has illustrated that one by the output stage that works together and form with output stage 100 similar BJT, the output stage that other are made up of BJT, for example by one by the output stage that works together and form with the similar BJT of output stage 60, also can be applied in reality and go according to the present invention.

As shown in Figure 5, output stage 150 comprises that a pair transistor supplements branch road 182, current mirror 158, output driving circuit 156 and a PNP BJT176 for anti-saturation clamper.Branch road 182 comprises a PMOS FET190, a resistance 188 and a NPN BJT186.The grid of FET190 is connected to V _iNupper, the drain electrode of FET190 is connected to V _sSon.One end of resistance 188 is connected on the source electrode of FET190, and is connected on the body end of FET190 (in order to eliminate body effect), and the other end of resistance 188 is connected to the emitter of NPN BJT186.That be connected to BJT186 base stage is V _bIAS.Current mirror 158 comprises PMOS FET192 and PMOS FET194.The grid of the grid of FET192 and drain electrode and FET194 is connected to the collector electrode of BJT186.FET192 and 194 source electrode are connected to V _dDon.The drain electrode of FET194 is connected to one end of load 154.The other end of load 154 is connected on ground 153, and its electromotive force is conventionally between V _dDand V _sSbetween.

Output driving circuit comprises NPN BJT170, resistance 172, and NPN BJT166 and current source 168, current source can be replaced or be omitted completely by a resistance.The collector electrode of BJT170 is connected to one end of load 154 and the drain electrode of FET194, and the emitter of BJT170 is connected to one end of resistance 172.The other end of resistance 172 is connected to V _sSon.The base stage of BJT170 is connected on the emitter and current source 168 of BJT166.Current source 168 is also connected to V _sSon.The collector electrode of BJT166 is connected to V _dDupper, the base stage of BJT166 is connected to V _iNon the emitter of PNP BJT176.The base stage of PNP BJT176 is connected on the collector electrode of BJT170, and the collector electrode of PNP BJT176 is connected to V _sSon.

Although the circuit in Fig. 5 150 comprises resistance 172 and 188, one of them can omit, or both can omit, or is replaced by the connection between the circuit node at their terminal places.

Just as Fig. 2 is the same with 100 with the output stage 60 in Fig. 4, output stage 150 produces and promotes electric current I _pwith traction current I _ncarry out the electric current in control load 154.I _pproduce and respond respectively V _bIASbias voltage and V that place provides _iNthe input signal that place provides, I _cflow through BJT186, the FET190 of resistance 188 and branch road 182.Just as the branch road 120 in branch road 80 and Fig. 4 in Fig. 2, the equivalent threshold voltage of branch road 182 is variable, and is subject to V _bIASthe control of the bias voltage at place.In order to respond I _c current mirror 158 makes I _paccording to factor M and I _cflow out pro rata the drain electrode of PMOS FET194, flow into load 154 and/or output driving circuit 156.

I _nproduced by output driving circuit 156, respond V _iNthe input signal that place provides.Circuit 156 is good common collectors known in technology, common emitter pair.In order to stop the saturated of transistor 170, in the time that the voltage drop of transistor 170 collector electrodes place arrives lower than threshold voltage, output stage 150 provides PNP BJT 176 to reduce the electric current of inflow transistor 166.

Fig. 6 has illustrated as one or more output stage 60(Fig. 2) V _bIASplace produces the circuit 200 of required bias voltage.The voltage and current that circuit 200 produces while being operated in idle point 94 by simulation by output stage 60 produces required bias voltage.More particularly, the voltage being produced by the many elements of circuit 200 is the same with the voltage that respective element in output stage 60 produces.For example, FET218,210,208,216 and 214 grid-source voltages that produce, can be also in most of the cases drain electrode-source voltage, equates respectively with FET62,64,72,76 and 78 voltages that produce in output stage 60.

The raw electric current of these element fecund in circuit 200 can equate with the electric current in respective element in output stage or be proportional.For example, for stabilized power supply, the electric current in circuit 200 can be scaled according to the electric current in output stage 60.In order to obtain identical working end voltage, the transistor specifications in circuit 200, mutual conductance (" K ") factor must change according to their electric current.The voltage and current producing under similar condition of work by analog output stage 60, circuit 200 produces a V _bIASvoltage, makes to produce in output stage 60 reactive current that is independent of integrated circuit fabrication process variation, temperature and supply voltage, and is only independent of current source and device specification ratio in circuit 200.Analog circuit 60 in this way, in circuit 200, device is tending towards eliminating with respect to circuit 60 to technique, temperature and supply voltage dependence.

Required V in circuit 200 _bIASthe generation of voltage is controlled by current source 202 and 204.Current source 202 and 204 can use any known circuit or method in application.Reactive current I that can be required with output stage 60 by the circuit of current source 202 and 204 generations _qequal or proportional.By one in two overlapping negative feedback loops of each drives of current source 202 and 204 generations.FET214 is set up in these feedback loop work, and 216 and 218 grid place voltages cause that the total current being produced by current source 202 and 204 flows through FET 210,212 and 218.

Can find a negative feedback loop at node 240 places, lead to the grid of FET216, supplement branch road 232 by pair transistor, current mirror 206, cascade FET212, finally gets back to node 240.This feedback loop comprises the electric current I of current source 202 exact values ₂, revise the deviation away from current source 202 exact values in 212 by the voltage and current of adjusting in loop.More particularly, if the electric current of FET210 and 212 conductings is not the exact value of current source 202, the direct current that flows into so node 240 just can not equal to flow out the direct current of node 240, just do not meet Kirchhoff's law, the voltage at node 240 places will start to raise or reduce, and transistor capacitance will charge or discharge.The rising of node 240 place's voltages or reduction will cause recovery Effects, revise the value completely of the electric current trend current source 202 in FET 210 and 212.

For example, if the drain current in FET 210 and 212 drops to the exact value lower than current source 202, the voltage that node 240 goes out so will show the trend of rising.Such voltage raises and will cause the rising of FET216 and 218 grid voltages, due to the acting in opposition of FET218, will cause the reduction of FET214 grid voltage.Since the rising of FET214 and 216 grid voltage across poles, the I in branch road 232 ₃will be similar to the I in Fig. 2 branch road 80 ₁increase.Electric current in branch road 232 increases the increase of the electric current in electric current and the FET212 that will cause FET210 in current mirror 206, therefore, just makes I ₂return to the exact value of current source 202.

Another feedback loop can find at the grid of FET214, and by branch road 232, current mirror 206, and cascade FET212, lead to the grid of FET218, by FET218, finally gets back to V _bIAS.Similar with the first feedback loop, this feedback loop flows through FET218 by work to maintain, and has the electric current I of current source 204 exact values ₄.If the electric current that FET218 flows through is not the exact value of current source 204, the direct current that flows into so node 242 is just not equal to the direct current that flows out node 242, just do not meet Kirchhoff's law, the voltage at node 242 places will start to raise or reduce, and transistor capacitance will start charge or discharge.Rising or the reduction of node 242 place's voltages can cause recovery Effects, revise the exact value of the electric current trend current source 204 in FET218.

For example,, if flow through the I of FET218 ₄drop to the exact value lower than current source 204, the voltage at node 242 places will show reduction trend so.In node 242 places and branch road 232, the reduction of FET214 grid voltage will cause electric current I in branch road 232 ₃increase.In order to respond I ₃increase, current mirror 206 can cause I ₂increase in proportion.As described above, electric current so increases the reduction that will cause node 240 places and FET218 grid voltage.The reduction of FET218 grid voltage will cause recovery Effects, makes the electric current I in FET218 ₄be increased to the exact value of current source 204.

As described above, because FET218,216,214,208 and 210 is selected to performance and FET62,76,78 in output stage, 72 and 64 roughly equal voltage and roughly equal or proportional electric current respectively, the voltage being produced by these feedback loops is exactly output stage 60 generation while being operated in idle point 94.The more important thing is, owing to flowing through the I of FET218 ₄with the I in FET62 _qcoupling or proportional, so clearly, the grid voltage of FET218 just equals V in output stage 60 _iNidle value V _iNQ.Same, owing to flowing through the I of FET210 ₂with the I in FET64 _qcoupling or proportional, so clearly, flows through the I of branch road 232 ₃with the electric current I in the FET76,78 and 72 of output stage 60 _qcoupling or proportional.Because the behavior of branch road 232 is similar to branch road 80, again because the grid of FET216 has and the idle input voltage V of output stage 60 _iNQequal voltage, also because flow through the electric current I of branch road 232 ₃match idle some time with current work in branch road 80, so, the grid voltage of FET214 and V _bIASneeded V while being just operated at idle with output stage 60 _bIASmatch.

As shown in Figure 6, circuit 200 provides cascade FET212 and electric capacity 220.Under the control of reference voltage 226 that is connected to its grid, it is constant that cascade FET212 allows drain electrode-source voltage of FET210 to stablize, like this, and the V of FET210 _dSjust with FET64(Fig. 2) match at idle point.Electric capacity 220 is by the V that prevented vibrational stabilization _bIASfeedback loop in generator.Electric capacity 220 is connected to V _bIASand between ground 230.Although be not compulsory, electric capacity 220 is placed on to V _bIASplace also satisfies the demand, and also satisfies the demand because the dominant pole of pressurizer is placed on to output.After electric capacity 220, be just not only used for stablizing feedback loop, prevent vibration, can also under most of frequencies, guarantee low output impedance, and can absorb V _bIAStransient current.

V in Fig. 6 _bIASin the design of generator 200, used transistor, its condition of work has been simulated the transistor of output stage 60 in Fig. 2.Other output-stage circuits that are out of shape as circuit 60, for example, those circuit in Fig. 4, Fig. 5 and other distortion not illustrating, need a corresponding V _bIASgenerator.Different in the situation that, one is similar to the V of circuit 200 _bIASgenerator can be constructed according to the above-mentioned principle of circuit 200 and with the relation of output stage 60.

The principle according to the present invention, people can find, and it can also be applied to other circuit, and for purposes of illustration, the present invention is unrestricted, limited by claim of the present invention.

Claims (9)

1. one kind produces the circuit of bias voltage to controlling output stage reactive current, it is characterized in that: the circuit that produces bias voltage for thering is the output stage of an idle point, when input signal equals direct voltage, when biasing input equals above-mentioned bias voltage, will produce a reactive current at idle point, this circuit comprises: first current source, provides first electric current proportional to above-mentioned reactive current; A transistor, on it, at least comprise a part for above-mentioned the first electric current by the amount of the first electric current, control the amount that above-mentioned the first electric current passes through and respond output voltage, when above-mentioned output voltage equals above-mentioned direct voltage, the amount of above-mentioned the first electric current that transistor passes through just equals above-mentioned the first electric current; A current mirror, the amount of the second electric current passing through on current mirror output at least comprises a part for the second electric current, controls the amount that above-mentioned the second electric current passes through and responds branch current; Second current source, produces above-mentioned the second electric current, proportional with above-mentioned reactive current, and the change that causes input voltage responds the amount of above-mentioned the second electric current that above-mentioned current mirror passes through; A supplementary branch road, its first input end is by above-mentioned input voltage control, the second input responds above-mentioned transistor and whether equals above-mentioned the first electric current by the amount of above-mentioned the first electric current, output produces above-mentioned branch current, first input end and second input of the above-mentioned branch road of its amount response, like this, when above-mentioned branch road produces above-mentioned branch current, cause that above-mentioned current mirror equals above-mentioned the second electric current by the amount of above-mentioned the second electric current, and above-mentioned input voltage is while equaling above-mentioned direct voltage, above-mentioned bias voltage will appear at above-mentioned the second input; Produce the method for bias voltage for thering is the output stage of an idle point, when input signal equals direct voltage, when biasing input equals above-mentioned bias voltage, will produce a reactive current at idle point, the method comprises: produce first electric current, and proportional with the reactive current of above-mentioned use the first current source; In a transistor, at least comprise a part for above-mentioned the first electric current by the amount of the first electric current, control the amount that above-mentioned the first electric current passes through and respond output voltage, when above-mentioned output voltage equals above-mentioned direct voltage, the amount of above-mentioned the first electric current that transistor passes through just equals above-mentioned the first electric current; In a current mirror, the amount of the second electric current passing through on current mirror output at least comprises a part for the second electric current, controls the amount that above-mentioned the second electric current passes through and responds branch current; In second current source, produce above-mentioned the second electric current, proportional with above-mentioned reactive current, and the change that causes input voltage responds the amount of above-mentioned the second electric current that above-mentioned current mirror passes through; In a supplementary branch road, its first input end is by above-mentioned input voltage control, the second input responds above-mentioned transistor and whether equals above-mentioned the first electric current by the amount of above-mentioned the first electric current, output produces above-mentioned branch current, first input end and second input of the above-mentioned branch road of its amount response, like this, when above-mentioned branch road produces above-mentioned branch current, cause that above-mentioned current mirror equals above-mentioned the second electric current by the amount of above-mentioned the second electric current, and above-mentioned input voltage is while equaling above-mentioned direct voltage, above-mentioned bias voltage will appear at above-mentioned the second input.

2. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 1, it is characterized in that: the circuit that produces bias voltage for having the output stage of an idle point further comprises above-mentioned output stage, above-mentioned output stage produces an output signal, make to have added in load a load current, respond the above-mentioned input signal receiving at signal input part, this circuit comprises: an output driver by above-mentioned input signal control, at least load current in the above-mentioned load of control section; One is supplemented branch road by second of above-mentioned input signal and bias voltage control, produces second branch current; Second current mirror by above-mentioned the second branch current control, at least load current in the above-mentioned load of control section; Wherein, above-mentioned output driver is a PMOS FET, and it has the grid of an above-mentioned signal of response input and one and drive the drain electrode of load current in above-mentioned load; Above-mentioned output driver is a NMOS FET, and it has the grid of an above-mentioned signal of response input and one and drive the drain electrode of load current in above-mentioned load; Above-mentioned driver comprises: a NPN transistor, and its base stage responds to above-mentioned signal input, and collector electrode drives the load current in above-mentioned load; First NPN transistor, its base stage responds to above-mentioned signal input, second NPN transistor, its base stage responds to the emitter of above-mentioned the first NPN transistor, and collector electrode drives the load current in above-mentioned load; Above-mentioned output stage further comprises: a PNP transistor, and its base stage responds to the voltage that is positioned at above-mentioned NPN transistor collector electrode, and emitter causes that above-mentioned NPN transistor base stage reduces the response to above-mentioned input signal; Above-mentioned output stage further comprises: a PNP transistor, and its base stage responds to the collector electrode that is positioned at above-mentioned NPN transistor, and emitter causes that above-mentioned NPN transistor base stage reduces the response to above-mentioned input signal.

3. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 1, it is characterized in that: the circuit that produces bias voltage for having the output stage of an idle point further comprises above-mentioned output stage, above-mentioned output stage produces an output signal and makes to have added in load a load current, respond the above-mentioned input signal receiving at signal input part, this circuit comprises: an output driver by above-mentioned input signal control, at least load current in the above-mentioned load of control section; One is supplemented branch road by second of above-mentioned input signal and bias voltage control, produces second branch current; Second current mirror by above-mentioned the second branch current control, at least load current in the above-mentioned load of control section; Wherein, above-mentioned branch road comprises: one has the NMOS FET of a grid and a source electrode, its grid responds to above-mentioned signal input, one has the PMOS FET of a grid, a drain electrode and a source electrode, its grid responds to above-mentioned bias voltage, drain electrode allows above-mentioned branch current pass through, and flows to above-mentioned current mirror, and source electrode responds to the source electrode of above-mentioned NMOS FET; One has the PMOS FET of a grid and a source electrode, its grid responds to above-mentioned signal input, one has the NMOS FET of a grid, a drain electrode and a source electrode, its grid responds to above-mentioned bias voltage, drain electrode allows above-mentioned branch current pass through, and flowing to above-mentioned current mirror, source electrode responds to the source electrode of above-mentioned PMOS FET; One has the PMOS FET of a grid and a source electrode, its grid responds to above-mentioned signal input, one has the NPN transistor of an emitter, a base stage and a collector electrode, its emitter responds to the source electrode of above-mentioned PMOS EFT, base stage responds to above-mentioned bias voltage, collector electrode allows above-mentioned branch current pass through, and flows to above-mentioned current mirror.

4. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 1, it is characterized in that: the circuit that produces bias voltage for having the output stage of an idle point further comprises above-mentioned output stage, above-mentioned output stage produces an output signal and makes to have added in load a load current, respond the above-mentioned input signal receiving at signal input part, this circuit comprises: an output driver by above-mentioned input signal control, at least load current in the above-mentioned load of control section; One is supplemented branch road by second of above-mentioned input signal and bias voltage control, produces second branch current; Second current mirror by above-mentioned the second branch current control, at least load current in the above-mentioned load of control section; Wherein, above-mentioned current mirror comprises: one has a NMOS FET of a drain electrode and a grid, its grid responds to the output of above-mentioned branch road, one has the 2nd NOMS FET of a drain electrode and a grid, load current in the above-mentioned load of its drain drives, grid responds to the drain and gate of an above-mentioned NMOS FET; One has a PMOS FET of a drain electrode and a grid, its grid responds to the output of above-mentioned branch road, one has the 2nd POMS FET of a drain electrode and a grid, load current in the above-mentioned load of its drain drives, grid responds to the drain and gate of an above-mentioned PMOS FET.

5. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 1, it is characterized in that: the circuit that produces bias voltage for having the output stage of an idle point further comprises an electric capacity, stablizes above-mentioned electric current by the generation that prevents vibration; The circuit that produces bias voltage for having the output stage of an idle point further comprises a cascode transistors, and the voltage that is positioned at above-mentioned current mirror output is stablized.

6. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 2, it is characterized in that: said method further produces an output signal, make to have added in load a load current, respond an input signal receiving at signal input part, said method further comprises: use an output driver, at least the load current in the above-mentioned load of control section, responds above-mentioned input signal; In second supplements branch road, produce second branch current, respond above-mentioned input signal and above-mentioned bias voltage; Use the second current mirror, at least load current in the above-mentioned load of control section, responds above-mentioned the second branch current that results from above-mentioned the second branch road; Wherein, above-mentioned output driver is a PMOS FET with a grid and a drain electrode, and its grid responds to above-mentioned signal input, the load current in the above-mentioned load of drain drives; Above-mentioned output driver is a NMOS FET with a grid and a drain electrode, and its grid responds to above-mentioned signal input, the load current in the above-mentioned load of drain drives; A NPN transistor, its base stage responds to above-mentioned signal input, and collector electrode drives the load current in above-mentioned load; First NPN transistor, its base stage responds to above-mentioned signal input, second NPN transistor, its base stage responds to the emitter of above-mentioned the first NPN transistor, and collector electrode drives the load current in above-mentioned load; Above-mentioned output driver further comprises a PNP BJT, and its base stage responds to the voltage that is positioned at above-mentioned NPN transistor collector electrode, and emitter causes that above-mentioned NPN transistor base stage reduces the response to above-mentioned input signal; Above-mentioned output driver further comprises a PNP BJT, and its base stage responds to the voltage that is positioned at above-mentioned the second NPN transistor collector electrode, and emitter causes that above-mentioned the first NPN transistor base stage reduces the response to above-mentioned input signal.

7. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 2, it is characterized in that: said method further produces an output signal, make to have added in load a load current, respond an input signal receiving at signal input part, said method further comprises: use an output driver, at least the load current in the above-mentioned load of control section, responds above-mentioned input signal; In second supplements branch road, produce second branch current, respond above-mentioned input signal and above-mentioned bias voltage; Use the second current mirror, at least load current in the above-mentioned load of control section, responds above-mentioned the second branch current that results from above-mentioned the second branch road; Wherein, above-mentioned the second branch road comprises: a NMOS FET, its grid responds to above-mentioned signal input, one has the PMOS FET of a grid, a drain electrode and a source electrode, its grid responds to above-mentioned bias voltage, drain electrode allows above-mentioned branch current pass through, and flows to above-mentioned current mirror, and source electrode responds to the source electrode of above-mentioned NMOS FET; A PMOS FET, its grid responds to above-mentioned signal input, one has the NMOS FET of a grid, a drain electrode and a source electrode, its grid responds to above-mentioned bias voltage, drain electrode allows above-mentioned branch current pass through, and flowing to above-mentioned current mirror, source electrode responds to the source terminal of above-mentioned NMOS FET; A PMOS FET, its grid responds to above-mentioned signal input, one has the NPN transistor of an emitter, a base stage and a collector electrode, its emitter responds to the source electrode of above-mentioned PMOS EFT, base stage responds to above-mentioned bias voltage, collector electrode allows above-mentioned branch current pass through, and flows to above-mentioned current mirror.

8. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 2, it is characterized in that: said method further produces an output signal, make to have added in load a load current, respond an input signal receiving at signal input part, said method further comprises: use an output driver, at least the load current in the above-mentioned load of control section, responds above-mentioned input signal; In second supplements branch road, produce second branch current, respond above-mentioned input signal and above-mentioned bias voltage; Use the second current mirror, at least load current in the above-mentioned load of control section, responds above-mentioned the second branch current that results from above-mentioned the second branch road; Wherein, above-mentioned the second current mirror comprises: a NMOS FET, its grid responds to the output of above-mentioned branch road, one has the 2nd NOMS FET of a drain electrode and a grid, load current in the above-mentioned load of its drain drives, grid responds to the drain and gate of an above-mentioned NMOS FET; One has a PMOS FET of a drain electrode and a grid, its grid responds to the output of above-mentioned branch road, one has the 2nd POMS FET of a drain electrode and a grid, load current in the above-mentioned load of its drain drives, grid responds to the drain and gate of an above-mentioned PMOS FET.

9. a kind of circuit that produces bias voltage to controlling output stage reactive current according to claim 2, it is characterized in that: the method that produces bias voltage for having the output stage of an idle point further comprises an electric capacity of use, stablizes above-mentioned electric current by the generation that prevents vibration; The method that produces bias voltage for having the output stage of an idle point further comprises a cascode transistors of use, and the voltage that is positioned at above-mentioned current mirror output is stablized.

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