CN103779213A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103779213A CN103779213A CN201210397928.9A CN201210397928A CN103779213A CN 103779213 A CN103779213 A CN 103779213A CN 201210397928 A CN201210397928 A CN 201210397928A CN 103779213 A CN103779213 A CN 103779213A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 140
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 25
- 238000005516 engineering process Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 52
- 238000001039 wet etching Methods 0.000 claims description 18
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 19
- 230000008021 deposition Effects 0.000 abstract description 2
- 230000006835 compression Effects 0.000 description 19
- 238000007906 compression Methods 0.000 description 19
- 238000013459 approach Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of a semiconductor. The manufacturing method of a semiconductor device, provided by the embodiments of the invention, realizes a germanium silicon layer formation technology through two steps, i.e., first of all, forming a first germanium silicon layer, and then forming a second germanium silicon layer in the first germanium silicon layer, so that the problem of non-ideal germanium silicon stack caused by forming the germanium silicon layer through a one-step deposition technology is overcome, the germanium silicon layer is closer to a PMOS channel area, the crushing stress enhancement effects of the germanium silicon layer are guaranteed, the PMOS performance is enhanced, and the performance of the whole semiconductor device is improved accordingly. In the semiconductor device provided by the embodiments of the invention, a germanium silicon layer comprises two parts, i.e., a first germanium silicon layer disposed at an outer side and a second germanium silicon layer disposed inside the first germanium silicon layer, so that the problem of non-ideal germanium silicon stack in the prior art is overcome, the germanium silicon layer is closer to a PMOS channel area, the crushing stress enhancement effects of the germanium silicon layer are guaranteed, the PMOS performance is enhanced, and the performance of the whole semiconductor device is improved accordingly.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and manufacture method thereof.
Background technology
In technical field of semiconductors, along with developing rapidly of nanofabrication technique, transistorized characteristic size has entered nanoscale.This mode of performance that improves the silicon CMOS device of current main-stream by the method for scaled down, is subject to the restriction of increasing physics and technique.In order to improve NMOS and the transistorized performance of PMOS in cmos device, stress technique (stress engineering) more and more receives the concern of industry.
The mobility of the charge carrier in stress influence semiconductor.Generally speaking, in silicon, the mobility of electronics increases along with the increase of the tension stress along electron transfer direction, and reduces along with the increase of compression.On the contrary, in silicon, the mobility in the hole of positively charged increases along with the increase of the compression of hole moving direction, and reduces along with the increase of tension stress.Therefore, can improve respectively the hole mobility of PMOS and the electron mobility of NMOS by introduce suitable compression and tension stress in raceway groove.
In the prior art, generally leak and introduce raceway groove compression (being germanium silicon technology) by epitaxial Germanium silicon (SiGe) source, utilize the lattice constant mismatch control strain size of source leakage and raceway groove, and then improve hole mobility, improve the performance of PMOS.For the semiconductor device of application germanium silicon technology, the quality direct relation of germanium silicon stack folded (stack) the size of the compression of the channel region that is applied to PMOS, and then directly has influence on the device performance of PMOS.
In the prior art, in the processing procedure of the semiconductor device of application germanium silicon technology, generally form as follows germanium silicon layer: first, in the Semiconductor substrate of the grid both sides of PMOS, etch groove (as U-shaped or Sigma type etc.); Then, in groove the disposable deposition that completes germanium silicon to form germanium silicon layer (generally adopting epitaxial growth method)., prior art completes the formation of whole germanium silicon layer by primary depositing technique.Due to germanium silicon growth rate in different directions (speed that finger-type becomes) inconsistent in groove, therefore, the germanium silicon layer that the technical scheme of aforementioned formation germanium silicon layer of the prior art forms is unsatisfactory (the folded quality of germanium silicon stack is undesirable) often, such as, the germanium silicon layer forming is generally distant from the channel region of PMOS, cause germanium silicon layer to be affected to the humidification of compression, and then cause the performance of PMOS undesirable, thereby cause the performance of whole semiconductor device undesirable.
Along with more and more higher to the performance requirement of semiconductor device in industry application, the problems referred to above that germanium silicon technology of the prior art exists also more and more highlight.Therefore, need to propose a kind of new semiconductor device and manufacture method thereof, meet the requirement of PMOS to compression, improve the performance of semiconductor device.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of semiconductor device and manufacture method thereof.
On the one hand, the invention provides a kind of manufacture method of semiconductor device, the method comprises the steps:
Step S101: the Semiconductor substrate that the grid structure that is formed with PMOS is provided;
Step S102: the both sides at the grid structure of described PMOS form grid the first side wall;
Step S103: take described grid the first side wall as mask, described Semiconductor substrate is carried out to etching, form the first groove in the both sides of the grid structure of described PMOS;
Step S104: form the first germanium silicon layer in described the first groove;
Step S105: the both sides at described grid the first side wall form grid the second sidewall;
Step S106: take described grid the second sidewall as mask, described the first germanium silicon layer is carried out to etching, form the second groove in described the first germanium silicon layer;
Step S107: form the second germanium silicon layer in described the second groove.
Wherein, described step S103 comprises:
Take described grid the first side wall as mask carries out dry etching to described Semiconductor substrate, form the first preliminary groove;
Take described grid the first side wall as mask, described Semiconductor substrate is carried out to wet etching, change the shape of described the first preliminary groove by described wet etching, form the first groove.
Wherein, in described step S104, the method for described formation the first germanium silicon layer is epitaxial growth technology.
Further, described epitaxial growth technology is the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical vapour deposition, rapid heat chemical vapour deposition and molecular beam epitaxy.
Wherein, described step S106 comprises:
Take described grid the second sidewall as mask carries out dry etching to described Semiconductor substrate, form the second preliminary groove;
Take described grid the second sidewall as mask, described Semiconductor substrate is carried out to wet etching, change the shape of described the second preliminary groove by described wet etching, form the second groove.
Wherein, in described step S107, the method for described formation the second germanium silicon layer is epitaxial growth technology.
Further, described epitaxial growth technology is the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical vapour deposition, rapid heat chemical vapour deposition and molecular beam epitaxy.
Wherein, the Sigma type that is shaped as of described the first groove, and/or, the Sigma type that is shaped as of described the second groove.
Wherein, the degree of depth of described the first groove is 60 ~ 80nm, and/or the degree of depth of described the second groove is 40 ~ 70nm.
Wherein, in described the first germanium silicon layer, the concentration of germanium is 5% ~ 20%, and/or in described the second germanium silicon layer, the concentration of germanium is 15% ~ 60%.
Further, between described step S104 and step S105, also comprise: the step of described PMOS being carried out to LDD processing.
On the other hand, the invention provides a kind of semiconductor device, described semiconductor device comprises Semiconductor substrate and the PMOS being located thereon, wherein, in the Semiconductor substrate of the grid structure both sides of described PMOS, be formed with the first groove, in described the first groove, be formed with the first germanium silicon layer; In described the first germanium silicon layer, be formed with the second groove, in described the second groove, be formed with the second germanium silicon layer.
Further, the Sigma type that is shaped as of described the first groove, and/or, the Sigma type that is shaped as of described the second groove.
Wherein, the degree of depth of described the first groove is 60 ~ 80nm type, and/or the degree of depth of described the second groove is 40 ~ 70nm.
Wherein, in described the first germanium silicon layer, the concentration of germanium is 5% ~ 20%, and/or in described the second germanium silicon layer, the concentration of germanium is 15% ~ 60%.
Wherein, described semiconductor device also comprises the grid the first side wall of the grid structure both sides that are positioned at described PMOS, the position that the outside of described grid the first side wall and the surface of described Semiconductor substrate have a common boundary, overlaps with the position that the surface of described Semiconductor substrate has a common boundary with described the first groove.
Further, described semiconductor device also comprises grid the second sidewall that is positioned at described grid the first side wall outside, the position that the outside of described grid the second sidewall and the surface of described Semiconductor substrate have a common boundary, overlaps with the position that the surface of described Semiconductor substrate has a common boundary with described the second groove.
Wherein, described semiconductor device also comprises the Semiconductor substrate Shang LDD district of the grid structure both sides that are positioned at described PMOS.
The manufacture method of the semiconductor device that the embodiment of the present invention provides, by being divided into twice, the formation technique of germanium silicon layer realizes, first form the first germanium silicon layer, then in the first germanium silicon layer, form the second germanium silicon layer, having overcome in prior art causes germanium silicon stack to fold the undesirable problem of quality by primary depositing technique formation germanium silicon layer, make germanium silicon layer more approach the channel region of PMOS, the compression that has guaranteed germanium silicon layer strengthens effect, improve the performance of PMOS, and then improved the performance of whole semiconductor device.The semiconductor device that the embodiment of the present invention provides, germanium silicon layer comprises the first germanium silicon layer that is positioned at outside and the second germanium silicon layer two parts that are positioned at the first germanium silicon layer inside, the special construction of this germanium silicon layer has overcome the folded undesirable problem of germanium silicon stack in prior art, make germanium silicon layer more approach the channel region of PMOS, therefore the compression that has guaranteed germanium silicon layer strengthens effect, improve the performance of PMOS, and then improved the performance of whole semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The profile of the structure of formation after each step of the manufacture method of a kind of semiconductor device that Figure 1A-Fig. 1 E is the embodiment of the present invention completes;
The profile of the typical structure of a kind of semiconductor device that wherein, Fig. 1 E is the embodiment of the present invention.
Fig. 2 is the flow chart of the manufacture method of a kind of semiconductor device of embodiment of the present invention proposition.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device.For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations.Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.In the time that this uses, " one " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", in the time using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.In the time that this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
Here with reference to the cross-sectional view of the schematic diagram as desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, can expect due to for example manufacturing technology and/or tolerance cause from shown in the variation of shape.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to for example manufacturing the form variations causing.For example, the Qi edge, injection region that is shown as rectangle has round or bending features and/or implantation concentration gradient conventionally, rather than binary from injection region to non-injection regions changes.Equally, when the disposal area forming by injection can cause this disposal area and injection to be carried out some injections in the district between the surface of process.Therefore, the district showing in figure is in fact schematically, their shape be not intended display device district true form and be not intended to limit scope of the present invention.
Unless otherwise defined, all terms (comprising technology and scientific terminology) have the identical implication of conventionally understanding with the those of ordinary skill in field of the present invention as used herein.Also will understand, in dictionary such as common use, defined term should be understood to have the implication consistent with they implications in the environment of association area and/or these specifications, and can not explaining in desirable or excessively formal meaning, unless definition so expressly here.
In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, so that semiconductor device and manufacture method thereof that explaination the present invention proposes.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Embodiment 1
The embodiment of the present invention provides a kind of manufacture method of semiconductor device.The detailed step of an illustrative methods of the manufacture method of the semiconductor device that the present invention proposes is described with reference to Figure 1A-1E and Fig. 2 below.The profile of the structure of formation after each step of the manufacture method of a kind of semiconductor device that wherein, Figure 1A-Fig. 1 E is the embodiment of the present invention completes; Fig. 2 is the flow chart of the manufacture method of a kind of semiconductor device of embodiment of the present invention proposition.
The manufacture method of the semiconductor device that the embodiment of the present invention provides, specifically comprises the steps:
Step 1, provide semi-conductive substrate 100, in described Semiconductor substrate, be formed with the grid structure 101 of PMOS, as shown in Figure 1A.
Wherein, the grid structure 101 of this PMOS can be common grid, can be also metal gates, can also, for being used to form the dummy grid of metal gates, be not construed as limiting herein.
In the embodiment of the present invention, each schematic diagram (Figure 1A to Fig. 1 E) only shows a part for semiconductor device, and this part comprises two PMOS; In the semiconductor device of the embodiment of the present invention, can also comprise the device such as NMOS, STI, because of irrelevant with the inventive point of the embodiment of the present invention, therefore be not construed as limiting and set forth.
As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to form.In described Semiconductor substrate, be formed with isolation structure, described isolation structure be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, Semiconductor substrate is divided into nmos area and PMOS district by described isolation structure.In described Semiconductor substrate, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure, by those skilled in the art are had the knack of, is described no longer in detail at this.
The both sides of the grid structure 101 of step 2, PMOS in Semiconductor substrate 100 form grid the first side wall 102, and the figure after formation as shown in Figure 1A.
Exemplary, the method that forms grid the first side wall 102 can be: in Semiconductor substrate 100, form one deck silicon nitride film, the part that described silicon nitride film is positioned to PMOS district is carried out dry etching, to form described grid the first side wall 102.
Step 3, etching semiconductor substrate 100 form the first groove 103 with the both sides of the grid structure 101 at PMOS, as shown in Figure 1B.
Wherein, the shape of the first groove 103, can be U-shaped, can be Sigma type, can be also other suitable shapes, in this no limit.
The method that forms the first groove 103 is: utilize grid the first side wall 102 for mask, Semiconductor substrate 100 is carried out to etching, form respectively the first groove 103 in the both sides of the grid structure 101 of PMOS.Wherein, the lithographic method adopting can be dry etching, can be wet etching, also can add wet etching etc. for dry etching, does not also limit at this.
Preferably, described the first groove 103 is Sigma type, and this shape can make the germanium silicon layer of follow-up formation more easily approach the channel region of PMOS, thereby the effect of the compression of the enhancing that can bring into play better germanium silicon to raceway groove, improves the device performance of PMOS.Further preferred, when the first groove 103 be shaped as Sigma type time, the degree of depth of the first groove 103 is 60 ~ 80nm.
Preferably, in embodiments of the present invention, the method that forms the first groove 103 is: first, take described grid the first side wall 102 as mask, described Semiconductor substrate 100 is carried out to dry etching, form the first preliminary groove (such as bowl-shape groove); Then, continue take described grid the first side wall 102 as mask, described Semiconductor substrate 100 is carried out to wet etching, change the shape of described the first preliminary groove by wet etching, form the first final groove 103(such as Sigma type).The figure of the first groove forming through abovementioned steps, as shown in Figure 1B.Further, in embodiments of the present invention, after aforementioned wet etching and before the step of follow-up formation germanium silicon layer (the first germanium silicon layer), can also comprise Semiconductor substrate is carried out to prewashed step, to reduce impurity, germanium silicon is formed the impact of technique.
Step 4, at interior formation the first germanium silicon layer 104 of the first groove 103, the figure of formation is as shown in Figure 1 C.
Particularly, form the method for the first germanium silicon layer 104, can adopt epitaxial growth technology.Described epitaxial growth technology can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Wherein, preferred, in step 4, should make the concentration of germanium (Ge) in the first germanium silicon layer 104 by control process conditions is 5% ~ 20%.Now, germanium silicon can be brought into play better compression enhancing effect.
Step 5, described PMOS is carried out to LDD processing.
Particularly, utilize the grid the first side wall 102 of described PMOS as mask, described PMOS is carried out to LDD processing.The object of carrying out LDD processing is, reduces the short-channel effect of device.And, the LDD of this step processes after forming the first germanium silicon layer, with respect to carrying out LDD processing in prior art before forming germanium silicon layer, destroyed can avoid LDD district to form groove (embodiment of the present invention is the first groove) in germanium silicon technology time, thereby can bring into play better the effect of the reduction short-channel effect in LDD district.
Those skilled in the art will appreciate that when short-channel effect when device is not obvious to the performance impact of device, this step can be omitted.
The both sides (concrete, in the both sides of grid the first side wall 102) of the grid structure 101 of step 6, PMOS in Semiconductor substrate 100 form the second sidewall 105 of grid, and the figure after formation as shown in Figure 1 C.
Exemplary, the method that forms grid the second sidewall 105 can be: in Semiconductor substrate 100, form one deck silicon nitride film, the part that described silicon nitride film is positioned to PMOS district is carried out dry etching, to form described grid the second sidewall 105.
Step 7, etching the first germanium silicon layer 104 are with at interior formation the second groove 106 of the first germanium silicon layer 104, as shown in Fig. 1 D.
Because the second groove 106 is formed in the first germanium silicon layer 104, therefore, the periphery of the first germanium silicon layer 104 is retained, and the first germanium silicon layer 104 ' of reservation as shown in Figure 1B.Obviously, the second groove 106 is less than the first groove 103, and is positioned at the inside of the first groove 103.
Wherein, the shape of the second groove 106, can be U-shaped, can be Sigma type, can be also other suitable shapes, in this no limit.
Preferably, the shape of the second groove 106 is consistent with the shape of the first groove 103.Preferred, the second groove 106 and the first groove 103 are Sigma type.This shape can make the final germanium silicon layer forming more easily approach the channel region of PMOS, thereby can bring into play better the effect of the compression of the enhancing raceway groove of germanium silicon, improves the device performance of PMOS.Preferably, when the second groove 106 be shaped as Sigma type time, the degree of depth of the second groove 106 is 40 ~ 70nm.
Particularly, the method that forms the second groove 106 can be: utilize grid the second sidewall 105 for mask, the first germanium silicon layer 104 is carried out to etching, at interior formation the second groove 106 of the first germanium silicon layer 104.Wherein, the lithographic method adopting can be dry etching, can be wet etching, also can add wet etching etc. for dry etching, does not also limit at this.
Preferably, in embodiments of the present invention, the method that forms the second groove 106 is: first, take described grid the second sidewall 105 as mask, described the first germanium silicon layer 104 is carried out to dry etching, form the second preliminary groove (such as bowl-shape groove); Then, continue take described grid the second sidewall 105 as mask, described the first germanium silicon layer 104 is carried out to wet etching, change the shape of described preliminary the second groove (such as bowl-shape groove) by wet etching, form the groove of the second groove 106(such as Sigma type).The figure of the second groove 106 forming through abovementioned steps, as shown in Fig. 1 D.Further, in embodiments of the present invention, after aforementioned wet etching and before the step of follow-up formation germanium silicon layer (the second germanium silicon layer), can also comprise Semiconductor substrate is carried out to prewashed step, to reduce impurity, germanium silicon is formed the impact of technique.
Step 8, at interior formation the second germanium silicon layer 107 of the second groove 106, the figure of formation is as shown in Fig. 1 E.
Particularly, form the method for the second germanium silicon layer 107, can adopt epitaxial growth technology.Described epitaxial growth technology can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Wherein, preferred, in step 8, should make the concentration of germanium (Ge) in the second germanium silicon layer 107 by control process conditions is 15% ~ 60%.In such cases, can bring into play better compression and strengthen effect.Especially when the situation that is 5% ~ 20% when this concentration of Ge in the second germanium silicon layer 107 with the concentration of germanium (Ge) in the first germanium silicon layer 104 matches, final germanium silicon layer (comprising the second germanium silicon layer 107 and the first germanium silicon layer 104 ' retaining) can be brought into play better compression and strengthen effect, is conducive to promote the performance of PMOS.
So far, completed the introduction of the manufacture method of the exemplary semiconductor device of the embodiment of the present invention.Those skilled in the art will appreciate that the method for the embodiment of the present invention is not as limit; And, although other steps in the irrelevant semiconductor device processing procedure of the embodiment of the present invention pair and inventive point, such as forming the step etc. of contact hole, be not described, but this does not represent that the embodiment of the present invention does not comprise these steps, but due to these processing steps and traditional identical the repeating no more of process for fabricating semiconductor device.
The manufacture method of the semiconductor device of the embodiment of the present invention, by being divided into twice, the formation technique of germanium silicon layer realizes, first form the first germanium silicon layer, then in the first germanium silicon layer, form the second germanium silicon layer, having overcome in prior art causes germanium silicon stack to fold the undesirable problem of quality by primary depositing technique formation germanium silicon layer, make germanium silicon layer more approach (comprising the second germanium silicon layer 107 and the first germanium silicon layer 104 ' retaining) channel region of PMOS, therefore the compression that has guaranteed germanium silicon layer strengthens effect, improve the performance of PMOS, and then improve the performance of whole semiconductor device.
With reference to Fig. 2, wherein show the flow chart of a kind of typical method in the manufacture method of semiconductor device that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.The method specifically comprises:
Step S101: the Semiconductor substrate that the grid structure that is formed with PMOS is provided;
Step S102: the both sides at the grid structure of described PMOS form grid the first side wall;
Step S103: take described grid the first side wall as mask, described Semiconductor substrate is carried out to etching, form the first groove in the both sides of the grid structure of described PMOS;
Step S104: form the first germanium silicon layer in described the first groove;
Step S105: the both sides at described grid the first side wall form grid the second sidewall;
Step S106: take described grid the second sidewall as mask, described the first germanium silicon layer is carried out to etching, form the second groove in described the first germanium silicon layer;
Step S107: form the second germanium silicon layer in described the second groove.
Embodiment 2
The embodiment of the present invention provides a kind of semiconductor device, can adopt the method manufacture of embodiment 1.Concrete structure is as follows:
As described in Fig. 1 E, the semiconductor device of the embodiment of the present invention, comprises Semiconductor substrate 100 and the PMOS being located thereon, wherein, in the Semiconductor substrate of grid structure 101 both sides of described PMOS, be formed with the first groove 103, in described the first groove 103, be formed with the first germanium silicon layer 104 '; In described the first germanium silicon layer 104 ', be formed with the second groove 107, in described the second groove 107, be formed with the second germanium silicon layer 108.
Wherein, the shape of the first groove 103, can be U-shaped, can be Sigma type, can be also other suitable shapes, in this no limit.Preferably, the Sigma type that is shaped as of described the first groove.
Wherein, the shape of the second groove 106, can be U-shaped, can be Sigma type, can be also other suitable shapes, in this no limit.Preferably, the Sigma type that is shaped as of described the second groove.Because the second groove 106 is formed in the first germanium silicon layer 104 ', and the first germanium silicon layer 104 ' is formed in the first groove 103, and apparently, the second groove 106 is positioned at the first groove 103 and is less than the first groove 103.
Preferably, the shape of the second groove 106 is consistent with the shape of the first groove 103.Preferred, the second groove 106 and the first groove 103 are Sigma type.This shape can make germanium silicon layer (the first germanium silicon layer 104 ' and the second germanium silicon layer 108) more approach the channel region of PMOS, thereby can bring into play better the effect of the compression of the enhancing raceway groove of germanium silicon, improves the device performance of PMOS.
Preferably, the degree of depth of described the first groove 103 is 60 ~ 80nm, and/or the degree of depth of described the second groove 106 is 40 ~ 70nm.When the degree of depth of the first groove 103 is 60 ~ 80nm, and in the degree of depth of the second groove 106 situation that is 40 ~ 70nm, can bring into play better compression and strengthen effect.
Preferably, in described the first germanium silicon layer, the concentration of germanium is 5% ~ 20%, and/or in described the second germanium silicon layer, the concentration of germanium is 15% ~ 60%.In such cases, can bring into play better compression and strengthen effect.
In embodiments of the present invention, described semiconductor device also comprises the grid the first side wall 102 of grid structure 101 both sides that are positioned at described PMOS, the position that the surface of the outside of grid the first side wall 102 and described Semiconductor substrate 100 has a common boundary, overlaps with the position that the surface of described Semiconductor substrate 100 has a common boundary with described the first groove 103.This structure, can form the first groove 103 as mask etching by grid the first side wall 102 easy to use.
Further, described semiconductor device also comprises grid second sidewall 105 in the outside that is positioned at described grid the first side wall 102, the position that the outside of described grid the second sidewall 105 and the surface of described Semiconductor substrate 100 have a common boundary, overlaps with the position that the surface of described Semiconductor substrate 100 has a common boundary with described the second groove 106.This structure, can form the second groove 106 as mask etching by grid the second sidewall 105 easy to use.
Further, the semiconductor device of the embodiment of the present invention also comprises the Semiconductor substrate 100 Shang LDD districts of grid structure 101 both sides that are positioned at described PMOS, to reduce the short-channel effect of device.
About the concrete structure of semiconductor device and the effect of associated components (rete) of the embodiment of the present invention, can, referring to embodiment 1, repeat no more herein.
The semiconductor device that the embodiment of the present invention provides, its germanium silicon layer comprises the first germanium silicon layer that is positioned at outside and the second germanium silicon layer two parts that are positioned at the first germanium silicon layer inside, this special construction has overcome and in prior art, uses the germanium silicon layer of individual layer to cause germanium silicon stack to fold undesirable problem, make germanium silicon layer more approach the channel region of PMOS, therefore the compression that has guaranteed germanium silicon layer strengthens effect, improve the performance of PMOS, and then improved the performance of whole semiconductor device.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S101: the Semiconductor substrate that the grid structure that is formed with PMOS is provided;
Step S102: the both sides at the grid structure of described PMOS form grid the first side wall;
Step S103: take described grid the first side wall as mask, described Semiconductor substrate is carried out to etching, form the first groove in the both sides of the grid structure of described PMOS;
Step S104: form the first germanium silicon layer in described the first groove;
Step S105: the both sides at described grid the first side wall form grid the second sidewall;
Step S106: take described grid the second sidewall as mask, described the first germanium silicon layer is carried out to etching, form the second groove in described the first germanium silicon layer;
Step S107: form the second germanium silicon layer in described the second groove.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described step S103 comprises:
Take described grid the first side wall as mask carries out dry etching to described Semiconductor substrate, form the first preliminary groove;
Take described grid the first side wall as mask, described Semiconductor substrate is carried out to wet etching, change the shape of described the first preliminary groove by described wet etching, form the first groove.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S104, the method for described formation the first germanium silicon layer is epitaxial growth technology.
4. the manufacture method of semiconductor device as claimed in claim 3, it is characterized in that, described epitaxial growth technology is the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical vapour deposition, rapid heat chemical vapour deposition and molecular beam epitaxy.
5. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described step S106 comprises:
Take described grid the second sidewall as mask carries out dry etching to described Semiconductor substrate, form the second preliminary groove;
Take described grid the second sidewall as mask, described Semiconductor substrate is carried out to wet etching, change the shape of described the second preliminary groove by described wet etching, form the second groove.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S107, the method for described formation the second germanium silicon layer is epitaxial growth technology.
7. the manufacture method of semiconductor device as claimed in claim 6, it is characterized in that, described epitaxial growth technology is the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical vapour deposition, rapid heat chemical vapour deposition and molecular beam epitaxy.
8. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the Sigma type that is shaped as of described the first groove, and/or, the Sigma type that is shaped as of described the second groove.
9. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the degree of depth of described the first groove is 60 ~ 80nm, and/or the degree of depth of described the second groove is 40 ~ 70nm.
10. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described the first germanium silicon layer, the concentration of germanium is 5% ~ 20%, and/or in described the second germanium silicon layer, the concentration of germanium is 15% ~ 60%.
The manufacture method of 11. semiconductor device as described in claim 1 ~ 10 any one, is characterized in that, also comprises: the step of described PMOS being carried out to LDD processing between described step S104 and step S105.
12. 1 kinds of semiconductor device, comprise Semiconductor substrate and the PMOS being located thereon, and it is characterized in that, in the Semiconductor substrate of the grid structure both sides of described PMOS, are formed with the first groove, are formed with the first germanium silicon layer in described the first groove; In described the first germanium silicon layer, be formed with the second groove, in described the second groove, be formed with the second germanium silicon layer.
13. semiconductor device as claimed in claim 12, is characterized in that, the Sigma type that is shaped as of described the first groove, and/or, the Sigma type that is shaped as of described the second groove.
14. semiconductor device as claimed in claim 12, is characterized in that, the degree of depth of described the first groove is 60 ~ 80nm type, and/or the degree of depth of described the second groove is 40 ~ 70nm.
15. semiconductor device as claimed in claim 12, is characterized in that, in described the first germanium silicon layer, the concentration of germanium is 5% ~ 20%, and/or in described the second germanium silicon layer, the concentration of germanium is 15% ~ 60%.
16. semiconductor device as claimed in claim 12, it is characterized in that, described semiconductor device also comprises the grid the first side wall of the grid structure both sides that are positioned at described PMOS, the position that the outside of described grid the first side wall and the surface of described Semiconductor substrate have a common boundary, overlaps with the position that the surface of described Semiconductor substrate has a common boundary with described the first groove.
17. semiconductor device as claimed in claim 16, it is characterized in that, described semiconductor device also comprises grid the second sidewall that is positioned at described grid the first side wall outside, the position that the outside of described grid the second sidewall and the surface of described Semiconductor substrate have a common boundary, overlaps with the position that the surface of described Semiconductor substrate has a common boundary with described the second groove.
18. semiconductor device as described in claim 12 to 17 any one, is characterized in that, described semiconductor device also comprises the Semiconductor substrate Shang LDD district of the grid structure both sides that are positioned at described PMOS.
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