CN103778965B - The adquisitiones damaging bit line address in non-volatile memory - Google Patents
The adquisitiones damaging bit line address in non-volatile memory Download PDFInfo
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- CN103778965B CN103778965B CN201210397321.0A CN201210397321A CN103778965B CN 103778965 B CN103778965 B CN 103778965B CN 201210397321 A CN201210397321 A CN 201210397321A CN 103778965 B CN103778965 B CN 103778965B
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Abstract
The invention discloses the adquisitiones damaging bit line address in a kind of non-volatile memory, non-volatile memory includes a memory cell array and the multiple word-line across described memory cell array, each the plurality of bit line has the first end and the second end, the plurality of bit line is divided into the first group and the second group, mat one detection method is that supply voltage (charging) or ground voltage (electric discharge) are bestowed the bit line of particular demographic, utilize damage bit line two detection-phases (open circuit and short-circuit detecting) cannot be divided to detect the plurality of bit line by the feature of normal discharge and recharge, and then can be by the address date sequentially obtaining damage bit line recording the status data whether each bit line is damaged in page buffer circuit, and the address damaging bit line need not be estimated by extra calculation procedure.
Description
Technical field
The present invention is the address read method about a kind of internal memory, more particularly about the address read method damaging bit line in a kind of non-volatile memory.
Background technology
In non-volatile memory, because of the technical defect of semiconductor fabrication process, it is often possible to cause the fracture of bit line or situation about being short-circuited etc. with neighbouring bit line.Such as: along with the micro of non-volatile memory size, adjacent two bit lines can be fairly close, generation bit line contacting window and adjacent bit lines get too close to the improper short circuit phenomenon caused the most in a manufacturing process.
Therefore, in non-volatile memory, verification operation is necessary, to confirm that electric charge is suitably to be incident upon in memory cell by programming operations.Non-volatile memory is generally tested by verification operation program, to confirm whether body has defect.But, traditionally, generally the most also must set through extra calculation procedure after proving program and provide the address of defective memory cell, for the setting of follow-up standby (redundant) memory cell, this extra calculation procedure i.e. produces time-consuming shortcoming.
Summary of the invention
One purpose of the present invention is to propose a kind of read method that can quickly obtain and damage bit line address.
Another object of the present invention is to shorten the detection time of bit line.
For reaching above-mentioned purpose and other purposes, in the adquisitiones damaging bit line address in the non-volatile memory of the present invention, described non-volatile memory includes a memory cell array and the multiple bit lines across described memory cell array, each the plurality of bit line has the first end and the second end, the plurality of bit line is divided into the first group and the second group, and described adquisitiones comprises the steps of replacement page buffer circuit；Carry out bit line and damage test to be embedded in described page buffer circuit by the status data whether damaged of bit line；According to the sequence of addresses of the bit line of each memory cell, sequentially read the described the status data whether each bit line in described page buffer circuit is damaged；And the address that breech lock is corresponding when the logic level that described status data is representative damage state, it is the address date damaging bit line with the address of breech lock.
In an embodiment, being to comprise the steps of the first end from the plurality of bit line in carry out bit line damaging test so that the damage state of bit line is embedded in the step of described page buffer circuit, described first group's bit line being bestowed supply voltage and is delivered to ground voltage to be charged program and described second group's bit line；Close the charging procedure to described first group's bit line, and bestow ground voltage to carry out discharge procedures from the plurality of bit line of two port of the plurality of bit line；The voltage level having according to described first group's bit line determines the state of each bit line under described first group, wherein has open circuit damage when the voltage level of bit line is non-for bit line described in ground voltage interval scale；From the second end of the plurality of bit line, described second group's bit line is bestowed supply voltage to be charged program, and from the first end of the plurality of bit line, described first group's bit line is bestowed ground voltage to carry out discharge procedures；Close the discharge procedures to described first group's bit line；And the voltage level having according to described first group's bit line determines the state of each bit line under described first group, wherein when the voltage level of bit line non-for bit line described in ground voltage interval scale be with adjacent bitline short circuits and have short circuit damage, wherein, first end of the plurality of bit line is the voltage bestowed of a page buffer circuit receiving described non-volatile memory, and described bit line whether to have the information that open circuit damages be to be recorded in described page buffer circuit.
In an embodiment, described first group's bit line is odd bit lines or even bitlines, and described second group's bit line is to be even bitlines or odd bit lines relative to described first group's bit line.
In an embodiment, wherein damage test, to be embedded in the status data whether damaged of bit line in the step of described page buffer circuit to further include, first group's bit line and the second group bit line are exchanged the step of also duplicate detection method in carrying out bit line, complete the detection of all bit lines further.
Thereby, the address damaging bit line can leave the status data whether damaged in page buffer circuit by specific detection method, and then the address date of bit line can be damaged by sequentially obtaining of the status data that is recorded in page buffer circuit, and the address damaging bit line need not be estimated by extra calculation procedure.
Accompanying drawing explanation
Fig. 1 is the read method flow chart damaging bit line in one embodiment of the invention.
Fig. 2 is for obtaining the partial circuit block chart damaging bit line address in one embodiment of the invention.
Fig. 3 is the detection method flow chart damaging bit line in Fig. 1.
Fig. 4 is the configuration block chart of non-volatile memory.
Fig. 5 is the exemplary plot of one embodiment of the invention neutrality line state.
Drawing reference numeral:
100 control circuits
110 array decoding circuits
120 CAM
130 counting circuits
200 page buffer circuits
300 memory cell arrays
400 bit line select circuitries
500 character line selection circuits
T upper end
B lower end
BL bit line
PB page buffer
WL character line
S100～S400 step
S201～S211 step
Detailed description of the invention
For being fully understood by the purpose of the present invention, feature and effect, hereby by following specific embodiment, and graphic appended by coordinating, the present invention is described in detail, illustrate such as rear:
Referring initially to Fig. 1, it it is the read method flow chart damaging bit line in one embodiment of the invention.Adquisitiones comprises the steps of S100, resets page buffer circuit；S200, carry out bit line damage test so that the status data whether damaged of bit line is embedded in this page buffer circuit；S300, the sequence of addresses of bit line according to each memory cell, sequentially read this status data whether each bit line in this page buffer circuit is damaged；And S400, in this status data be representative damage state logic level time address corresponding to breech lock, be the address date damaging bit line with the address of breech lock.
Then refer to Fig. 2, be for obtaining the partial circuit block chart damaging bit line address in one embodiment of the invention.Comprising control circuit 100 and page buffer circuit 200 in this circuit, wherein this control circuit 100 comprises: array decoding circuit 110, CAM (CAM) 120 and counting circuit 130.This status data whether damaged due to each bit line is to be recorded in page buffer circuit 200, when this state information whether each bit line read in this page buffer circuit 200 is damaged, it is to make CAM (CAM) 120 sequentially read the data in page buffer circuit 200 through array decoding circuit 110 by counting circuit 130 again according to the sequence of addresses of the bit line of each memory cell, and then obtains the data of every string (column).In other words, address information because of every string (column) corresponding only, during so reading data in page buffer circuit 200, counting circuit 130 is based on sequence of addresses makes control circuit 100 carry out the reading of the data in page buffer circuit 200 seriatim.
This CAM (CAM) 120 can have a latch circuit, with the address date that breech lock in time receiving logic level (such as: high logic level " 1 ") representing damage state is corresponding, to shift the plurality of address date when follow-up programming (program) in this CAM (CAM) 120, and then obtain the address date damaging bit line.Therefore, in the step of S400, can comprise: before CAM 120 is programmed, will there is the address latch of the logic level of damage state in this CAM 120.
The present invention carries out damaging the reading of the address of bit line by the specific detection method damaging bit line.Please referring next to Fig. 3, it it is the detection method flow chart damaging bit line in Fig. 1.The embodiment of the present invention is that the multiple bit lines across this memory cell array of non-volatile memory are divided into Liang Ge group, i.e. the first group and the second group.The bit line that preferably can be sorted by the odd number in multiple bit lines of sequential is as the first group, and the bit line of even number sequence is as the second group；Or, the bit line sorted by the odd number in the plurality of bit line of sequential is as the second group, and the bit line of even number sequence is as the first group.Each bit line has two-end-point for the input of signal and output.First end or second end of the multiple bit lines mentioned in the embodiment of the present invention all refer to same direction, for example, first end of multiple bit lines can represent the lower end (B as shown in Figure 4) of memory cell array, second end of the plurality of bit line i.e. represents the upper end (T as shown in Figure 4) of memory cell array, and subsequent embodiment will be in this, as example.
After having distinguished bit line, just supply voltage (charging) or ground voltage (electric discharge) are bestowed the bit line of particular demographic, utilize damage bit line cannot be detected the plurality of bit line by the feature of normal discharge and recharge.
As it is shown on figure 3, the detection method in the embodiment of the present invention comprises the steps of
First, step S201: from first end (B) of multiple bit lines, first group's bit line is bestowed supply voltage (such as: Vcc) to be charged program, further, this second group bit line is bestowed ground voltage (such as: Vss) simultaneously using as shielding (shielding).
Then, step S203: close the charging procedure to this first group bit line, and from second end (T) of the plurality of bit line, the plurality of bit line is bestowed ground voltage to carry out discharge procedures.Wherein, this discharge procedures herein refers to discharge all of bit line.In this discharge procedures; the a bit of time would generally be continued with completely to bit line discharges; for the bit line that open circuit (drop) is damaged, discharge procedures herein will the most i.e. can detect that, to it without effect, the bit line that open circuit (drop) is damaged.
Then, step S205: the voltage level having according to this first group bit line determines the state of each bit line under this first group, wherein when the voltage level of bit line non-for ground voltage (Vss) time represent this bit line and there is open circuit damage；Otherwise, represent this bit line when the voltage level of bit line is for ground voltage (Vss) and damage without open circuit (drop).
Then, step S207: from second end (T) of the plurality of bit line, this the second group bit line is bestowed supply voltage (Vcc) to be charged program, further, from first end (B) of the plurality of bit line, this first group bit line is bestowed ground voltage (Vss) to carry out discharge procedures simultaneously.
After completing the charge and discharge program of step S207, then, step S209: close the discharge procedures to this first group bit line.In this step, a bit of time can be continued so that first group of bit line with short circuit damage can be completely charged by the charging procedure of second group of adjacent bit line.For the bit line that short circuit is damaged, uninterrupted charging procedure herein will be recharged to it, and then can detect, based on this, the bit line that short circuit is damaged.
Then, step S211: the voltage level having according to this first group bit line determines the state of each bit line under this first group.Wherein when the voltage level of bit line is supply voltage (Vcc), represent this bit line and adjacent bitline short circuits and there is short circuit damage, can have supply voltage (Vcc) is because of the bit line in the first group, the charging procedure of the adjacent second group of bit line being shorted connection persistently charges, and in turn results in the non-result for ground voltage of voltage level of bit line；Otherwise, represent this bit line when the voltage level of bit line is ground voltage (Vss) and damage without short circuit.
Aforesaid step S201, S203, S205 are the detection (openbitlinetest) that open circuit is damaged, and step S207, S209, S211 are then the detection (shortbitlinetest) that short circuit is damaged.
Accordingly, short circuit or the open-circuit condition of this first group bit line can be detected, further, when to detect second group's bit line, the detection of second group's bit line can be completed as long as first group's bit line in aforementioned detecting step and second group's bit line being exchanged and repeating foregoing schemes.
Then refer to Fig. 4, be the configuration block chart of non-volatile memory.The non-volatile memory of Fig. 4 comprises: memory cell array 300, page buffer circuit 200, bit line select circuitry 400, character line selection circuit 500 and control circuit 100, connected mode therebetween is as shown in the figure.Control circuit 100 is used for controlling page buffer circuit 200, bit line select circuitry 400 and controlling whether in this and supplies power supply to memory cell array, to perform aforesaid detection method.Supply voltage (Vcc) is for the bit line group that should select through bit line select circuitry 400 by circuit existing in memory cell array.This control circuit 100 can control electricity in supply be from the second end (upper end, T) or from the first end (lower end, B) supply voltage give bit line.
Then Fig. 5 is referred to, being the exemplary plot of one embodiment of the invention neutrality line state, Fig. 5 is using 10 bit lines as example, and as a example by every two bit lines are connected to page buffer PB, wherein the 4th bit lines is to have the bit line that open circuit is damaged, and 7&8 bit lines is the bit line with short circuit damage.It practice, every page buffer PB may be coupled to only one bit lines, two or three bit lines or more a plurality of.
It is that first group's bit line is detected as example in this.Wherein, even bitlines (the 2nd, 4,6,8,10 bit lines) be as first group's bit line, odd bit lines (the 1st, 3,5,7,9 bit lines) as second group's bit line, T direction refers to that the second end, B direction refer to the first end.
First, from the first end (B) to first group's bit line (the 2nd, 4,6,8,10 bit lines) charging, from the first end (B) and/or the second end (T) to second group's bit line (the 1st, 3,5,7,9 bit lines) electric discharge.Now, the 4th bit lines is near the part meeting accumulated charge of the first end (B), and the 8th article of position online will not accumulated charge (electric charge runs off from the 7th bit lines).
Then, close to this first group bit line (the 2nd, 4,6,8,10 bit lines) charging procedure, and from the second end (T) to all bit lines (1-10 bit lines) discharge.In this, owing to being to discharge from the second end (T), the electric charge that therefore the 4th article of position is accumulated near the first end (B) online will not run off；The electric charge without any accumulation is then remained as the 8th bit lines.
Then, owing to the voltage level of the 4th bit lines is power source voltage Vcc, remaining first group's bit line (the 2nd, 6,8,10 bit lines) be ground voltage Vss, page buffer PB can latch state now accordingly.For example, the logical value in the page buffer PB that the 4th bit lines connects can be set to " 1 ", and the logical value in remaining page buffer PB is set to " 0 ".
Then, from the second end (T) to second group's bit line (the 1st, 3,5,7,9 bit lines) charging, and from the first end (B) to this first group bit line (the 2nd, 4,6,8,10 bit lines) electric discharge.Now, the 8th article of position online will not accumulated charge (though electric charge flows into from the 7th bit lines but also flows out from the first end (B)).
Then, close to first group's bit line (the 2nd, 4,6,8,10 bit lines) electric discharge.Now, be simply turned off electric discharge, second group's bit line (the 1st, 3,5,7,9 bit lines) still in charging, electric charge therefore can be made to flow into the 8th bit lines from the 7th bit lines, and then make the 8th bit lines accumulated charge.
Then, owing to the voltage level of the 8th bit lines is power source voltage Vcc, remaining first group's bit line (the 2nd, 4,6,10 bit lines) be ground voltage Vss, page buffer PB can latch state now accordingly.For example, the logical value in the page buffer PB that the 8th bit lines connects can be set to " 1 ", and the logical value in remaining page buffer PB is set to " 0 ", and the page buffer PB wherein, being set to " 1 " will not change.So can be quickly detected from whether first group's bit line has open circuit or short circuit damage, and require no tediously long sequencing/erasing procedure.
Therefore, due under aforesaid specific detection method, the present invention carrys out the breech lock foundation as the address damaging bit line by the specific information having in page buffer circuit, and then can quickly and correctly obtain address information, and it is belonging to the most directly obtain, read without extra operation, after more can promoting detection and damage the overall work flow that bit line address reads.
The present invention discloses with preferred embodiment the most, is so familiar with the technology person and it should be understood that this embodiment is only used for describing the present invention, and is not construed as limiting the scope of the present invention.It should be noted that such as equivalent with this embodiment change and displacement, all should be set to be covered by scope of the invention.Therefore, protection scope of the present invention is when being as the criterion with the defined person of claim.
Claims (5)
1. the adquisitiones damaging bit line address in a non-volatile memory, it is characterized in that, described non-volatile memory includes a memory cell array and the multiple bit lines across described memory cell array, each the plurality of bit line has the first end and the second end, the plurality of bit line is divided into the first group and the second group, and described adquisitiones comprises the steps of
Reset page buffer circuit；
Carry out bit line and damage test to be embedded in described page buffer circuit by the status data whether damaged of bit line；
According to the sequence of addresses of the bit line of each memory cell, sequentially read the described the status data whether each bit line in described page buffer circuit is damaged；And
The address that breech lock is corresponding when the logic level that described status data is representative damage state, is the address date damaging bit line with the address of breech lock；
Wherein, in carry out bit line damage test comprise the steps of so that the status data whether damaged of bit line is embedded in the step in described page buffer circuit
From the first end of the plurality of bit line, described first group's bit line is bestowed supply voltage and is delivered to ground voltage to be charged program and described second group's bit line；
Close the charging procedure to described first group's bit line, and bestow ground voltage to carry out discharge procedures from the plurality of bit line of two port of the plurality of bit line；And
The voltage level having according to described first group's bit line determines the state of each bit line under described first group, wherein has open circuit damage when the voltage level of bit line is non-for bit line described in ground voltage interval scale.
2. adquisitiones as claimed in claim 1, it is characterized in that, the address that breech lock is corresponding when at the logic level that described status data is representative damage state, comprise in the step damage the address date of bit line with the address of breech lock: before a CAM is programmed, will there is the address latch of the logic level of damage state in described CAM.
3. adquisitiones as claimed in claim 1, is characterized in that, comprises the steps of to be embedded in the step of described page buffer circuit by the status data whether damaged of bit line in carrying out bit line damage test
From the second end of the plurality of bit line, described second group's bit line is bestowed supply voltage to be charged program, and from the first end of the plurality of bit line, described first group's bit line is bestowed ground voltage to carry out discharge procedures；
Close the discharge procedures to described first group's bit line；And
The voltage level having according to described first group's bit line determines the state of each bit line under described first group, wherein has short circuit when the voltage level of bit line is non-damage for bit line described in ground voltage interval scale and adjacent bitline short circuits,
Wherein, the first end of the plurality of bit line receives the voltage bestowed of a page buffer circuit of described non-volatile memory, and described bit line whether to have the information that open circuit damages be to be recorded in described page buffer circuit.
4. adquisitiones as claimed in claim 3, is characterized in that, described first group's bit line is odd bit lines or even bitlines, and described second group's bit line is to be even bitlines or odd bit lines relative to described first group's bit line.
5. adquisitiones as claimed in claim 3, is characterized in that, further includes following steps in carrying out bit line damage test to be embedded in the step of described page buffer circuit by the status data whether damaged of bit line:
From the first end of the plurality of bit line, it is to be delivered to ground voltage to carry out discharge procedures to be charged program and described first group's bit line that described second group's bit line is bestowed supply voltage；
Close the charging procedure to described second group's bit line, and bestow ground voltage to carry out discharge procedures from the plurality of bit line of two port of the plurality of bit line；
The voltage level having according to described second group's bit line determines the state of each bit line under described second group, wherein has open circuit damage when the voltage level of bit line is non-for bit line described in ground voltage interval scale；
From the second end of the plurality of bit line, described first group's bit line is bestowed supply voltage to be charged program, and from the first end of the plurality of bit line, described second group's bit line is bestowed ground voltage to carry out discharge procedures；
Close the discharge procedures to described second group's bit line；And
The voltage level having according to described second group's bit line determines the state of each bit line under described second group, wherein when the voltage level of bit line non-for bit line described in ground voltage interval scale be with adjacent bitline short circuits and there is short circuit damage.
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| CN108877867B (en) * | 2017-05-08 | 2020-10-02 | 珠海全志科技股份有限公司 | DRAM cold joint detection method and device |
| CN109979521B (en) * | 2017-12-28 | 2021-03-02 | 长鑫存储技术有限公司 | Detection circuit and memory using same |
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| CN101084556A (en) * | 2002-09-24 | 2007-12-05 | 桑迪士克股份有限公司 | Non-volatile memory and method with improved sensing |
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