TWI476775B - Acquisition Method of Damaged Bit Line in Nonvolatile Memory Device - Google Patents

Description

Method for obtaining damaged bit line address in non-volatile memory device

The present invention relates to a method for reading an address of a memory, and more particularly to an address reading method for a damaged bit line in a non-volatile memory device.

In the non-volatile memory device, due to defects in the semiconductor process technology, it is often the case that the bit line is broken or short-circuited with the adjacent bit line. For example, as the size of the non-volatile memory device is reduced, the adjacent two-element lines will be quite close, and thus it is easy to cause an improper short circuit caused by the bit line contact window being too close to the adjacent bit line in the process.

Therefore, in a non-volatile memory device, a verification operation is necessary to confirm that the charge is properly injected into the memory cell by a stylization operation. Non-volatile memory devices are typically tested by a verification operating procedure to verify that the body is defective. However, traditionally, after the verification procedure, an additional calculation program is usually required to set the address of the defective memory cell for subsequent setting of the redundant memory cell, and this additional calculation program is generated. Time-consuming shortcomings.

An object of the present invention is to provide a reading method capable of quickly obtaining a damaged bit line address.

Another object of the invention is to reduce the detection time of the bit lines.

In order to achieve the above and other objects, in the method for obtaining a damaged bit line address in the non-volatile memory device of the present invention, the non-volatile memory device includes a memory cell array and a complex across the memory cell array. a digit line, each of the bit lines having a first end and a second end, the bit lines being divided into a first group and a second group, the obtaining method comprising the steps of: resetting a page buffer circuit Performing a bit line damage test to record the state data of whether the bit line is damaged in the page buffer circuit; sequentially reading the page buffer circuit according to the address sequence of the bit line of each memory cell Whether the state line data is damaged or not; and when the status data is a logic level representing the damage state, the corresponding address is latched, and the address of the latch is the address data of the damaged bit line.

In one embodiment, the step of performing a bit line damage test to record the damage state of the bit line in the page buffer circuit includes the following steps: from the first end of the bit line, the first The group bit line is supplied with a supply voltage for performing a charging process and the second group bit line is applied with a ground voltage; the charging procedure for the first group of bit lines is turned off, and the bit line is disconnected from the bit line The second end applies a ground voltage to the bit line to perform a discharging process; determining a state of each bit line under the first group according to a voltage level of the first group bit line, wherein When the voltage level of the bit line is not a ground voltage, it represents that the bit line has an open circuit damage; from the second end of the bit line, a supply voltage is applied to the second group bit line for charging procedure And applying a ground voltage to the first group of bit lines from the first end of the bit line to perform a discharging process; turning off a discharging process for the first group of bit lines; and according to the first group The voltage level of the group bit line determines the number The state of each bit line under a group, wherein when the voltage level of the bit line is not a ground voltage, it represents that the bit line is short-circuited with the adjacent bit line and has a short-circuit damage, wherein The first end of the bit line receives the voltage applied by the page buffer circuit of one of the non-volatile memory devices, and the information about whether the bit line has an open circuit damage is recorded in the page buffer circuit.

In an embodiment, the first group of bit lines is an odd bit line or an even bit line, and the second group bit line is an even bit with respect to the first group bit line. Line or odd bit line.

In an embodiment, the step of performing the bit line damage test to record the state data of the bit line damage in the step of the page buffer circuit further comprises: the first group bit line and the second group bit. The steps of the meta-line interchange and repeat detection methods further complete the detection of all bit lines.

Thereby, the address of the damaged bit line can be left in the page buffer circuit by the specific detection method, and the state data of the damaged state can be read by the sequential reading of the state data recorded in the page buffer circuit. Obtain the address data of the damaged bit line without additional calculation procedures to estimate the address of the damaged bit line.

In order to fully understand the objects, features and effects of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings, which are illustrated as follows: First, refer to FIG. A flowchart of a method for reading a damaged bit line in an embodiment of the invention. The acquisition method includes the following steps: S100, heavy a page buffer circuit; S200, performing a bit line damage test to record the state data of the bit line damage in the page buffer circuit; S300, according to the address order of the bit line of each memory cell, And reading the status data of whether each bit line in the page buffer circuit is damaged; and S400, wherein the status data is a logical level of the damage state, the corresponding address of the latch is latched, and the address of the latch is Destroy the address data of the bit line.

Next, please refer to FIG. 2, which is a partial circuit block diagram for obtaining a damaged bit line address in an embodiment of the present invention. The circuit includes a control circuit 100 and a page buffer circuit 200. The control circuit 100 includes a column decoding circuit 110, a content addressable memory (CAM) 120, and a counting circuit 130. The status data of whether each bit line is damaged is recorded in the page buffer circuit 200, and when the status data of each bit line in the page buffer circuit 200 is damaged, the counting circuit is used. The content addressable memory (CAM) 120 sequentially reads the data in the page buffer circuit 200 according to the address sequence of the bit line of each memory cell, and then obtains each column (column). )data of. In other words, since each column corresponds to the unique address information, when the data is read from the page buffer circuit 200, the counting circuit 130 causes the control circuit 100 to perform the data in the page buffer circuit 200 one by one according to the address sequence. Reading.

The content addressable memory (CAM) 120 can have a latch circuit for latching the corresponding address data when receiving a logic level (eg, a high logic level 1") representing a corrupted state. Transferring the address data to the content addressable memory (CAM) 120 during subsequent programming In the middle, the address data of the damaged bit line is obtained. Therefore, in the step of S400, the address of the logical level having the corrupted state may be latched in the content addressable memory 120 before the content addressable memory 120 is programmed.

The invention performs the reading of the address of the damaged bit line by the detection method of the specific damaged bit line. Please refer to FIG. 3, which is a flow chart of the detection method of the damaged bit line in FIG. Embodiments of the present invention divide a plurality of bit lines of a non-volatile memory device across the memory cell array into two groups, namely, a first group and a second group. Preferably, the odd-ordered bit lines in the bit lines arranged in order are used as the first group, and the even-ordered bit lines are used as the second group; or, the sequentially arranged bit lines are sequentially arranged. The odd-ordered bit lines in the equipotential lines are used as the second group, and the even-ordered bit lines are taken as the first group. Each bit line has two ends for input and output of signals. The first end or the second end of the complex bit line mentioned in the embodiment of the present invention refers to the same direction. For example, the first end of the complex bit line can represent the lower end of the memory cell array (such as the fourth B), the second end of the bit line represents the upper end of the memory cell array (as shown in FIG. 4), and the subsequent embodiments will be taken as an example.

After distinguishing the bit line, the power supply voltage (charging) or the ground voltage (discharge) is applied to the bit line of the specific group, and the bit line is detected by the feature that the damaged bit line cannot be normally charged and discharged. .

As shown in FIG. 3, the detection method in the embodiment of the present invention includes the following steps: First, step S201: the first end (B) of the self-complex bit line, the first The group bit line is supplied with a supply voltage (for example, Vcc) to perform a charging process, and at the same time, a ground voltage (for example, Vss) is applied to the second group bit line as a shielding.

Next, in step S203, the charging procedure for the first group of bit lines is turned off, and a ground voltage is applied to the bit lines from the second end (T) of the bit lines to perform a discharging process. Here, the discharge procedure herein refers to discharging all the bit lines. In this discharge procedure, it usually lasts for a short period of time to completely discharge the bit line. For an open (broken) damaged bit line, the discharge program here will have no effect on it, and thus can be detected. Open the broken (broken) bit line.

Next, in step S205, the state of each bit line under the first group is determined according to the voltage level of the first group bit line, wherein the voltage level of the bit line is not the ground voltage (Vss When it is, the bit line has an open circuit damage; conversely, when the voltage level of the bit line is the ground voltage (Vss), it means that the bit line has no open circuit (broken) damage.

Next, in step S207, a supply voltage (Vcc) is applied to the second group bit line from the second end (T) of the bit line to perform a charging process, and simultaneously from the bit line The first end (B) applies a ground voltage (Vss) to the first group of bit lines to perform a discharge process.

After the charging and discharging procedures of step S207 are completed, next, step S209: the discharging procedure for the first group of bit lines is turned off. In this step, it will last for a short time to allow the first group of bit lines with short circuit damage to be fully charged by the charging process of the adjacent second group of bit lines. For short-circuited bit lines, the uninterrupted charging procedure here will recharge them. Electricity, which in turn can detect the bit line of the short circuit damage based on this.

Next, in step S211, the state of each bit line under the first group is determined according to the voltage level of the first group bit line. When the voltage level of the bit line is the power supply voltage (Vcc), it means that the bit line is short-circuited with the adjacent bit line and has a short-circuit damage, and the power supply voltage (Vcc) is caused by the first group. The bit line, the charging procedure of the adjacent second group of bit lines connected by the short circuit is continuously charged, and the voltage level of the bit line is not the result of the ground voltage; otherwise, when the voltage level of the bit line is When it is the ground voltage (Vss), it means that there is no short-circuit damage to the bit line.

The above steps S201, S203, and S205 are open bitline tests, and steps S207, S209, and S211 are short bitline tests.

Accordingly, the short circuit or open state of the first group of bit lines can be detected. Further, when the second group of bit lines is to be detected, the first group of bit lines in the foregoing detecting step is used. The detection of the second group of bit lines can be completed by exchanging with the second group of bit lines and repeating the foregoing process.

Next, please refer to Figure 4, which is a block diagram of the configuration of a non-volatile memory device. The non-volatile memory device of FIG. 4 includes a memory cell array 300, a page buffer circuit 200, a bit line selection circuit 400, a word line selection circuit 500, and a control circuit 100, and the connection therebetween is as shown. The control circuit 100 is here used to control the page buffer circuit 200, the bit line selection circuit 400, and to control whether or not to supply power to the memory cell array to perform the aforementioned detection method. The supply voltage (Vcc) is a group of bit lines selected by the existing circuitry in the memory cell array to be selected by the bit line selection circuit 400. The control The circuit 100 can control the supply to the supply line from the second end (upper end, T) or from the first end (lower end, B) to the bit line.

Next, please refer to FIG. 5, which is an exemplary diagram of a bit line state in an embodiment of the present invention. FIG. 5 is an example of 10 bit lines, and is connected to a page buffer PB by two bit lines. For example, the 4th bit line is a bit line with open circuit damage, and the 7th and 8th bit lines are bit lines with short circuit damage. In fact, each page buffer PB can be coupled to only one bit line, two or three bit lines, or more.

Here, the detection of the first group of bit lines is taken as an example. Wherein, the even bit lines (the 2nd, 4th, 6th, 8th, and 10th bit lines) are used as the first group of bit lines, and the odd bit lines (1st, 3rd, 5th, 7th, and 9th bits) Line) is the second group of bit lines, the T direction refers to the second end, and the B direction refers to the first end.

First, the first group of bit lines (the 2nd, 4th, 6th, 8th, and 10th bit lines) are charged from the first end (B), from the first end (B) and/or the second end (T) Discharge the second group of bit lines (the first, third, fifth, seventh, and nine bit lines). At this time, the portion of the fourth bit line near the first end (B) accumulates electric charge, and the electric charge does not accumulate on the eighth bit line (the electric charge is lost from the seventh bit line).

Next, the charging procedure for the first group of bit lines (the 2nd, 4th, 6th, 8th, and 10th bit lines) is turned off, and all the bit lines are used from the second end (T) (1-10) Strip bit line) discharge. Here, since the discharge is performed from the second end (T), the charge accumulated on the fourth bit line near the first end (B) is not lost; as for the eighth bit line, there is still no The accumulated charge.

Then, since the voltage level of the fourth bit line is the power supply voltage Vcc, the remaining first group of bit lines (the second, sixth, eighth, and tenth bit lines) are The ground voltage Vss, the page buffer PB will latch the state at this time. For example, the logical value in the page buffer PB of the fourth bit line connection is set to "1", and the logical value in the remaining page buffers PB is set to "0".

Then, charging the second group bit line (the first, third, fifth, seventh, and nine bit lines) from the second end (T), and the first group bit from the first end (B) The line (the 2nd, 4th, 6th, 8th, and 10th bit lines) is discharged. At this time, no charge is accumulated on the eighth bit line (the charge flows from the seventh bit line but also flows out from the first end (B)).

Next, the discharge of the first group of bit lines (the 2nd, 4th, 6th, 8th, and 10th bit lines) is turned off. At this time, only the discharge is turned off, and the second group bit line (the first, third, fifth, seventh, and nine bit lines) is still being charged, so that the electric charge can flow from the seventh bit line to the eighth bit. The element line, which in turn causes the 8th bit line to accumulate charge.

Then, since the voltage level of the 8th bit line is the power supply voltage Vcc, the remaining first group bit lines (the 2nd, 4th, 6th, and 10th bit lines) are the ground voltage Vss, the page buffer The PB will latch the state at this time. For example, the logical value in the page buffer PB of the 8th bit line connection is set to "1", and the logical value in the remaining page buffers PB is set to "0", wherein it has been set to The page buffer PB of "1" will not be changed. In this way, it is possible to quickly detect whether the first group of bit lines has an open circuit or a short circuit damage without going through a lengthy stylization/erasing procedure.

Therefore, in the foregoing specific detection method, the present invention uses the special information in the page buffer circuit as a latching basis for destroying the address of the bit line, thereby obtaining the address information quickly and correctly. And its system It is automatically obtained directly, without the need for additional operations to read, and it can improve the overall workflow of the post-detection and damage bit line address reading.

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application.

100‧‧‧Control circuit

110‧‧‧ column decoding circuit

120‧‧‧Content addressable memory

130‧‧‧Counting circuit

200‧‧‧ page buffer circuit

300‧‧‧Memory cell array

400‧‧‧ bit line selection circuit

500‧‧‧word line selection circuit

T‧‧‧Upper

B‧‧‧Bottom

BL‧‧‧ bit line

PB‧‧‧ page buffer

WL‧‧‧ character line

S100~S400‧‧‧Steps

S201~S211‧‧‧Steps

FIG. 1 is a flow chart of a method for reading a damaged bit line in an embodiment of the present invention.

FIG. 2 is a partial circuit block diagram of a method for obtaining a damaged bit line address according to an embodiment of the present invention.

Figure 3 is a flow chart showing the detection method of the damaged bit line in Fig. 1.

Figure 4 is a block diagram of the configuration of a non-volatile memory device.

Fig. 5 is a view showing an example of a state of a bit line in an embodiment of the present invention.

S100~S400‧‧‧Steps

Claims (5)

A method for obtaining a damaged bit line address in a non-volatile memory device, the non-volatile memory device comprising a memory cell array and a plurality of bit lines spanning the memory cell array, each of the bit lines Having a first end and a second end, the bit lines are divided into a first group and a second group, and the obtaining method comprises the steps of: resetting a page buffer circuit; performing a bit line damage test to place the bit The state data of whether the line is damaged is recorded in the page buffer circuit; according to the address sequence of the bit line of each memory cell, the state in which each bit line in the page buffer circuit is damaged is sequentially read. Data; and the status data is the logical position of the damage state, and the address corresponding to the latch is the address of the latched bit line, wherein the bit line damage test is performed to place the bit Whether the state data of the damaged line is recorded in the step of the page buffer circuit includes the steps of: applying a supply voltage to the first group of bit lines from the first end of the bit line for performing Charging procedure The second group of bit lines is applied with a ground voltage; the charging process for the first group of bit lines is turned off, and a ground voltage is applied to the bit lines from the second end of the bit lines Performing a discharge process; and determining a state of each bit line under the first group according to a voltage level of the first group of bit lines, wherein the bit line is electrically When the voltage level is not the ground voltage, it means that the bit line has an open circuit damage. The obtaining method of claim 1, wherein the corresponding address is latched when the state data is a logical level representing a damage state, and the address of the latch is the address data of the damaged bit line. The step includes: latching the address of the logical level having the corrupted state in the content addressable memory before programming the content addressable memory. The method of obtaining the method of claim 1, wherein the step of performing a bit line damage test to record the state data of the bit line in the page buffer circuit further comprises the following steps: a second end of the equipotential line, applying a supply voltage to the second group of bit lines for performing a charging process, and grounding the first group of bit lines from the first end of the bit line Voltage to perform a discharge process; turning off a discharge sequence for the first group of bit lines; and determining a state of each bit line under the first group according to a voltage level of the first group of bit lines Wherein, when the voltage level of the bit line is not a ground voltage, the bit line is short-circuited with the adjacent bit line and has a short-circuit damage, wherein the first end of the bit line receives the non-volatile The voltage applied by the page buffer circuit of one of the memory devices and the information on whether or not the bit line has an open circuit damage are recorded in the page buffer circuit. The obtaining method of claim 3, wherein the first group bit line is an odd bit line or an even bit line, and the second group bit line is relative to the first group The bit line is an even bit line or an odd bit line. The method of claim 3, wherein the step of performing a bit line damage test to record the status data of the bit line in the page buffer circuit further comprises the following steps: from the bit a first end of the line, applying a supply voltage to the second group of bit lines for performing a charging process, and the first group of bit lines is applied with a ground voltage to perform a discharging process; turning off the second group And charging a bit line, and applying a ground voltage to the bit line from the second end of the bit line to perform a discharging process; determining the voltage level according to the second group bit line a state of each bit line under the second group, wherein when the voltage level of the bit line is not a ground voltage, the bit line has an open circuit damage; from the second end of the bit line The first group of bit lines is supplied with a supply voltage for performing a charging process, and a ground voltage is applied to the second group of bit lines from the first end of the bit line to perform a discharging process; a discharge procedure of the group bit line; and according to the second group of bits The voltage level of the line determines the state of each bit line under the second group, wherein when the voltage level of the bit line is not the ground voltage, it represents that the bit line is shorted to the adjacent bit line And it has a short circuit damage.