CN103778957B - A kind of RCAM memories of interval matching CAM cell circuit and its composition - Google Patents
A kind of RCAM memories of interval matching CAM cell circuit and its composition Download PDFInfo
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- CN103778957B CN103778957B CN201410044641.7A CN201410044641A CN103778957B CN 103778957 B CN103778957 B CN 103778957B CN 201410044641 A CN201410044641 A CN 201410044641A CN 103778957 B CN103778957 B CN 103778957B
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Abstract
The present invention relates to ic manufacturing technology field, a kind of RCAM memories of interval matching CAM cell circuit and its composition, the high voltage amplitude of oscillation is more than in interval matching unit GERMC circuits, 5th NMOS tube MN5 and the first PMOS MP1 complementary combinations, MP1 grids are connected with D# ends, source electrode is connected with the 3rd input SL, 6th NMOS tube MN6 and the second PMOS MP2 complementary combinations, MP2 grids are connected with D ends, source electrode is connected with the 4th input SL#, two are serially connected at the node connected between compound tube with first, second NMOS tube MN1, MN2 grid is connected, 3rd NMOS tube MN3 drain electrode is connected with the second input GE path, its grid is connected with D# ends.Transfer tube MN5 and MN6 are become into transmission gate present invention introduces two PMOSs, P point voltage swings is improved, supply voltage VDD can be reached, make to be equal to chain and the signaling rate increase more than chain, circuit speed accelerates, while also improving the robustness of element circuit, improves noise resisting ability.
Description
Technical field
The present invention relates to ic manufacturing technology field, more specifically to a kind of interval matching CAM（Content
Addressable Memory, content addressable memories）The RCAM of element circuit and its composition（Range Content
Addressable Memory, interval matching content addressable memories）Memory.
Background technology
With advancing by leaps and bounds for Internet technology, network traffics persistently increase, and network speed is improved constantly, and this is required mutually
Networking hardware equipment is constantly updated come the need for meeting network high-speed development.For an IPV4 packet, port search operation
Generally completed using RCAM circuits, this just proposes higher requirement to performances such as RCAM circuit speeds and power consumptions.High-performance
Support of the design of RCAM circuits to express network has great importance.The research to RCAM has deployed very early both at home and abroad,
Review of literatures part is shown in correlative study：
【1】SPITZNAGEL,E.,TAYLOR,D.,AND TURNER,J.2003.Packet classification
using extended TCAMs.In Proceedings of the IEEE International Conference on
Network Protocol,120-131.
Extended TCAM concepts are proposed, a kind of interval detection circuit unit is devised.But this element is static knot
Structure and each unit 32 transistors of needs, circuit performance are limited.
【2】KIM,Y.-D.,AHN,H.-S.,PARK,J.-Y.,AND JEONG,D.-K.2006.AStorage-and
Power-Efficient Range-Matching TCAM for Packet Classification.In Proceedings
of the ISSCC Dig.Tech.Paper,168-169.
New interval matching unit is proposed, TCAM can be efficiently solved and go storing caused by inspection search operation
The problem of efficiency is low, but be due to the storage organization for being still static, circuit speed is slow.
【3】SHARMA,M.,THUUMMALAPALLY,D.R.,AND DHANARAJ,T.2004.Range check cell
and a method for the use thereof.US Patent6,766,317.
【4】PEREIRA,J.P.2006.Content Addressable Memory with Range Compare
Function.US Patent7,035,968.
【3】With【4】Dynamic interval mating structure is proposed respectively, and interval matching unit number of tubes is few, simple circuit.
But Circuit Matching line is operated under serial mode, the critical path of circuit is very long, and to result in circuit speed slow.
【5】KIM,Y.-D.,AHN,H.-S.,PARK,J.-Y.,AND YEN,C.2008.AHigh-Speed Range-
Matching TCAM for Storage-Efficient Packet Classification.IEEE Transaction on
Circuit and Systems-I, 56,6,1221-1230.,
This paper presents static and dynamic interval matching unit, and it is single for the preferable motion interval matching of performance
Member, devises a kind of PDML matched lines circuit structure, and number of tubes used in circuit is less and PDML can cause late-class circuit
Pre-arcing causes circuit evaluation speed to accelerate.But matched line does not solve issue of priority and is still work in series mould
Formula, so such a Circuit Matching line power consumption is very big, critical path is also very long to cause circuit speed to be limited.
【6】ZHANG,J.-W.,YU,M.-Y.,LIU,B.-D.,AND HUANG,X.-F.2009.AHigh-Speed and
EDP-Efficient Range-Matching Scheme for Packet Classification.IEEE
Transaction on Circuit and System-II,56,9,729-733.
It is have devised herein according to what size of data relation was innovated equal to chain with being more than the matched line circuit structure that chain is separated,
And interval matching unit is proposed accordingly.The separated circuit structure of two chains can easily solve circuit prior level problem, drop
Low late-class circuit overturns speed, while improving the evaluation speed of circuit using virtual earth effect.But it is due to unit internal inverters
Still it is operated in the presence of electric leakage and circuit under serial mode, this causes the power consumption of circuit larger and limited speed.
【7】Zhang Jianwei, Wu Guoqiang, Wu Zhigang, sand is for army building, and 2011.CAM memory cell, word with interval matching feature
Circuit and memory.Utility model patent, 201120190934
This paper presents a kind of RCAM matching units of Low dark curient and improved couple of PF-CDPD (Pseudo-Footless
Clock-and-Data Precharged Dynamic gate, the clock data precharge dynamic gate of virtual earth) matched chain
Structure.Circuit significantly reduce matching unit presence leakage current the problem of, but matching unit internal node due to
There is the pressure drop of threshold voltage size causes circuit noise resisting ability not good, simultaneously because during evaluation using tandem working mould
Formula, circuit speed is limited.
The content of the invention
In order to overcome the shortcomings of that prior art is present, it is an object of the present invention to provide a kind of interval matching CAM cell circuit and
Its RCAM memory constituted.The interval matching CAM cell circuit newest at present by improving, is abbreviated as interval matching unit
（Range Matching Cell, RMC）, it is proposed that a kind of new cascade RMC element circuits be association of activity and inertia match knot
Structure, new circuit can effectively improve the noise resisting ability of circuit, while improving speed, take into account power dissipation overhead.
In order to realize foregoing invention purpose, problem present in prior art is solved, the present invention is adopted the technical scheme that：
A kind of interval matching CAM cell circuit, selected from more than interval matching unit GERMC circuits, less than interval matching unit LERMC electricity
Road, the high voltage amplitude of oscillation are more than interval matching unit GERMC circuits or the high voltage amplitude of oscillation is less than in interval matching unit LERMC circuits
One kind, in foregoing circuit, two phase inverters from beginning to end are referred to as D ends, the other end as one end of data storage cell
Referred to as D# ends, the D# ends are the logic NOTs at D ends.
The drain electrode of the 3rd NMOS tube MN3 being more than in interval matching unit GERMC circuits and the second input GE path
It is connected, its grid is connected with D# ends, and the source electrode of the 3rd NMOS tube MN3 is connected with the 4th NMOS tube MN4 drain electrode, its source electrode
Ground connection, grid is connected with the 3rd input SL.
The drain electrode of the 3rd NMOS tube MN3 being less than in interval matching unit LERMC circuits and the second input GE path
It is connected, its grid is connected with D ends, and the source electrode of the 3rd NMOS tube MN3 is connected with the 4th NMOS tube MN4 drain electrode, its source electrode
Ground connection, grid is connected with the 4th input SL#, and the SL# is SL logic NOT.
The high voltage amplitude of oscillation is more than in interval matching unit GERMC circuits, the 5th NMOS tube MN5 and the first PMOS
MP1 complementary combinations, the first PMOS MP1 grids are connected with D# ends, source electrode with the 3rd input SL be connected, the 6th NMOS tube MN6 and
Second PMOS MP2 complementary combinations, the second PMOS MP2 grids are connected with D ends, and source electrode is connected with the 4th input SL#, two phases
Grid at the node connected between mutual tandem compound pipe with the first NMOS tube MN1 and the second NMOS tube MN2 is connected, and the 3rd
NMOS tube MN3 drain electrode is connected with the second input GE path, and its grid is connected with D# ends, the source electrode of the 3rd NMOS tube MN3
Drain electrode with the 4th NMOS tube MN4 is connected, its source ground, and grid is connected with the 3rd input SL.
The high voltage amplitude of oscillation is less than in interval matching unit LERMC circuits, the 5th NMOS tube MN5 and the first PMOS
MP1 complementary combinations, the first PMOS MP1 grids are connected with D# ends, source electrode with the 3rd input SL be connected, the 6th NMOS tube MN6 and
Second PMOS MP2 complementary combinations, the second PMOS MP2 grids are connected with D ends, and source electrode is connected with the 4th input SL#, two phases
Grid at the node connected between mutual tandem compound pipe with the first NMOS tube MN1 and the second NMOS tube MN2 is connected, and the 3rd
NMOS tube MN3 drain electrode is connected with the second input GE path, and its grid is connected with D ends, the source electrode of the 3rd NMOS tube MN3
Drain electrode with the 4th NMOS tube MN4 is connected, the source ground of the 4th NMOS tube MN4, and grid is connected with the 4th input SL#.
A kind of RCAM memories of interval matching CAM cell circuit composition, include the RMC element circuits of first order cascade
100th, the RMC element circuits 101 and result treatment element circuit 102 of n rear class cascade, wherein, rear class cascade series n=1,2,
3 ... positive integers.The RMC element circuits 100 of the first order cascade are included equal to chain EQ_Chain circuits 200, more than chain GE_
Chain circuits 201, m circuit 204 and a circuit 205, wherein, the cascade series of circuit 204 m=1,2,3 ... positive integers.It is described
The RMC element circuits 101 of rear class cascade include being equal to chain EQ_Chain circuits 202, more than chain GE_Chain circuits 203, m electricity
Road 204 and a circuit 205, wherein, the cascade series of circuit 204 m=1,2,3 ... positive integers.The RMC of the first order cascade is mono-
The output EQ_G3 equal to chain EQ_Chain circuits 200 in first circuit 100 in second level circuit 101 respectively with being equal to chain EQ_
In the evl ends of Chain circuits 202 and the evl ends connection more than chain GE_Chain circuits 203, the second level circuit 101 etc.
In chain EQ_Chain circuits 202 output EQ_G2 respectively with being equal to chain EQ_Chain circuits 202 in tertiary circuit 101
Evl ends and more than chain GE_Chain circuits 203 evl ends connect, the like go down, in final circuit 101 be equal to chain EQ_
The output EQ_G0 of Chain circuits 202 respectively with the first PMOS MP1 and the 5th NMOS tube in result treatment element circuit 102
The GE_G3 more than chain GE_Chain circuits 201 in MN5 grid connection, the RMC element circuits 100 of the first order cascade
It is connected respectively with the 5th PMOS MP5 and the 4th NMOS tube MN4 grid in result treatment element circuit 102, described second
Level circuit 101 in the GE_G2 more than chain GE_Chain circuits 203 respectively with the 4th in result treatment element circuit 102
PMOS MP4 grid and the 3rd NMOS tube MN3 grid connection ..., are more than chain GE_Chain in the final circuit 101
The grids and the first NMOS tube MN1 of the GE_G0 of circuit 203 respectively with the second PMOS MP2 in result treatment element circuit 102
Grid connection.
The circuit 204 is selected from more than interval matching unit GERMC circuits, less than interval matching unit LERMC circuits, height
Voltage swing is more than interval matching unit GERMC circuits or the high voltage amplitude of oscillation less than one in interval matching unit LERMC circuits
Kind, the circuit 205 be selected from it is a kind of with the identical of circuit 204, while second NMOS tube MN2 in circuit is removed, by the
One NMOS tube MN1 source ground.
It is described to be equal to chain EQ_Chain circuits 200, including PMOS MP0 ... MPm-1, MPm and phase inverter INV1 and institute
There is the first NMOS tube MN1 in the 204 and 205 of cascade, wherein, all PMOS MP0 ... MPm-1, MPm source electrode connect power supply electricity
Pressure, is connected with phase inverter INV1 inputs again after its connection that drains, the grid connection first order circuit 204 of the PMOS MPm
In the 5th NMOS tube MN5 source electrode and the 6th NMOS tube MN6 source electrode tie point Pm.PMOS MPm-1 grid connection the
The source electrode of the 5th NMOS tube MN5 in secondary circuit 204 and the 6th NMOS tube MN6 source electrode tie point Pm-1 ... PMOSs
MP1 grid connects the source electrode and the 6th NMOS tube MN6 source electrode tie point of the 5th NMOS tube MN5 in m grades of circuits 204
P1.PMOS MP0 grid connects the source electrode and the 6th NMOS tube MN6 of the 5th NMOS tube MN5 in m+1 grades of circuits 205
Source electrode tie point P0.Phase inverter INV1 output end is connected with signal E0.Phase inverter INV1 inputs connect cascade first simultaneously
First NMOS tube MN1 of level circuit 204 drain electrode, the first NMOS tube MN1 of cascade first order circuit 204 source electrode connection cascade
First NMOS tube MN1 of second level circuit 204 drain electrode ..., by that analogy.The first NMOS tube MN1 source electrodes in circuit 205
Ground connection, the first NMOS tube MN1 of its connection upper level circuit 204 that drains source electrode.
It is described to be more than chain GE_Chain circuits 201, including PMOS MPm+1, MPm+2, MPm+3, NMOS tube MN1 and MN2,
And in the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the 205 of cascade in the 204 of all cascades
The 3rd NMOS tube MN3, the 4th NMOS tube MN4.Wherein, PMOS MPm+1 source electrode meets supply voltage, grid and signal OPEQ
It is connected, its drain electrode is connected with PMOS MPm+2 and MPm+3 source electrode, NMOS tube MN1 drain electrode and PMOS MPm+2 drain electrode
It is connected again with signal G0 after connection, NMOS tube MN1 source ground.The grid phase of PMOS MPm+2 grid and NMOS tube MN1
Even, the grid phase after PMOS MPm+3 drain electrode is connected with NMOS tube MN2 drain electrode again with PMOS MPm+2 and NMOS tube MN1
Even, PMOS MPm+3 grid is connected with NMOS tube MN2 grid, while clk signal is connected, NMOS tube MN2 source electrode connection
Cascade the second NMOS tube MN2 of first order circuit 204 drain electrode, the 2nd NMOS of its source electrode connection cascade second level circuit 204
Pipe MN2 drain electrode ..., by that analogy.The second of 3rd NMOS tube MN3 drain electrodes connection upper level circuit 204 in circuit 205
NMOS tube MN2 source electrode.
It is described to be equal to chain EQ_Chain circuits 202, including PMOS MP0 ... MPm-1, MPm, MPevl, phase inverter INV1 and
The first NMOS tube MN1 in 3rd NMOS tube MN3 and the 204 of all cascades and 205, wherein, the source electrode of all PMOSs connects
Supply voltage, is connected with phase inverter INV1 input and the 3rd NMOS tube MN3 drain electrode connecting node again after drain electrode connection,
Phase inverter INV1 output end is connected with signal EO, and the grid of the PMOS Mpevl is connected with signal evl.The PMOS
The source electrode and the 6th NMOS tube MN6 source electrode tie point of the 5th NMOS tube MN5 in MPm grid connection first order circuit 204
Pm.The source electrode and the 6th NMOS tube MN6 of the 5th NMOS tube MN5 in PMOS MPm-1 grid connection second level circuit 204
Source electrode tie point Pm-1 ... PMOSs MP1 grid connects the source electrode and the of the 5th NMOS tube MN5 in m grades of circuits 204
Six NMOS tube MN6 source electrode tie point P1.PMOS MP0 grid connects the 5th NMOS tube MN5 in m+1 grades of circuits 205
Source electrode and the 6th NMOS tube MN6 source electrode tie point P0.The grid of the 3rd NMOS tube MN3 is connected with signal evl.3rd
First NMOS tube MN1 of NMOS tube MN3 source electrode connection cascade first order circuit 204 drain electrode, cascade first order circuit 204
First NMOS tube MN1 of the first NMOS tube MN1 source electrode connection cascade second level circuit 204 drain electrode ..., by that analogy.Electricity
The first NMOS tube MN1 source grounds in road 205, the first NMOS tube MN1 of its connection upper level circuit 204 that drains source electrode.
It is described to be more than chain GE_Chain circuits 203, including PMOS MPm+1, MPm+2, MPm+3, NMOS tube MN1, MN2 and
The second NMOS tube MN2's, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and cascade in MN4, and the 204 of all cascades
The 3rd NMOS tube MN3 in 205, the 4th NMOS tube MN4.Wherein, PMOS MPm+1 source electrode connects supply voltage, grid and letter
Number OPEQ is connected, and its drain electrode is connected with PMOS MPm+2 and MPm+3 source electrode, NMOS tube MN1 drain electrode and PMOS MPm+2
Drain electrode connection after be connected again with signal G0, NMOS tube MN1 source ground.PMOS MPm+2 grid is with NMOS tube MN1's
Grid be connected, PMOS MPm+3 drain electrode be connected with NMOS tube MN2 drain electrode after again with PMOS MPm+2's and NMOS tube MN1
Grid is connected, and PMOS MPm+3 grid is connected with NMOS tube MN2 grid, while being connected with signal clk.The NMOS tube
MN4 grid with signal evl with being connected again after MN3 grid connection, drain electrode connection NMOS tube MN2 source electrode.The NMOS tube
Second NMOS tube MN2 of MN4 source electrode connection cascade first order circuit 204 drain electrode, its source electrode connection cascade second level circuit
204 the second NMOS tube MN2 drain electrode ..., by that analogy.3rd NMOS tube MN3 drain electrodes connection upper level electricity in circuit 205
The second NMOS tube MN2 on road 204 source electrode.
Present invention has the advantages that：A kind of RCAM memories of interval matching CAM cell circuit and its composition, the high electricity
The amplitude of oscillation is pressed to be more than in interval matching unit GERMC circuits, the 5th NMOS tube MN5 and the first PMOS MP1 complementary combinations, MP1 grid
Pole is connected with D# ends, and source electrode is connected with the 3rd input SL, the 6th NMOS tube MN6 and the second PMOS MP2 complementary combinations, MP2 grid
Pole is connected with D ends, and source electrode is connected with the 4th input SL#, two be serially connected at the node connected between compound tube with first,
The grid of second NMOS tube MN1, MN2 is connected, and the 3rd NMOS tube MN3 drain electrode is connected with the second input GE path, its grid and
D# ends are connected.Compared with the prior art, in bibliography 7 carries interval matching unit RMC circuits, due to the grid of MN3 pipes
Voltage by NMOS tube transmission high level is influenceed that supply voltage VDD can not possibly be reached, actual value is about that supply voltage cuts NMOS
Pipe threshold voltage is VDD-Vth, and the present invention is that two NMOS tube MN7 are eliminated on the basis of interval matching unit RMC circuits
With MN8, change MN3 grid connected mode, improve the grid voltage amplitude of oscillation of MN3 pipes, enhance the noise resisting ability of circuit.
On this basis, two PMOSs are introduced again and transfer tube MN5 and MN6 are become into transmission gate, improve P point voltage swings, can be with
Supply voltage VDD is reached, makes to be equal to chain and the signaling rate increase more than chain, circuit speed accelerates, also improved simultaneously
The robustness of element circuit, improves noise resisting ability.The RMC element circuits of new cascade use new matching unit RMC
Circuit structure, and it is designed to static criteria cmos circuits equal to chain EQ_chain drop-down passages.New circuit structure can be according to
So keep priority relationship, reduction reversion probability.When being compared operation, EQ_chain can take the lead in carrying out in pre-charging stage
Evaluation, in the evaluation stage, the GE_chain of the RMC units of rear class New Cascading receives upper level EQ_chain result of evaluation.
So being equal to chain EQ_chain can work in precharge, and the time without taking the evaluation stage, evaluation speed is big
It is big to accelerate.
Brief description of the drawings
Fig. 1 is that the present invention is more than interval matching unit GERMC circuits.
Fig. 2 is that the present invention is less than interval matching unit LERMC circuits.
Fig. 3 is that the high voltage amplitude of oscillation of the present invention is more than interval matching unit GERMC circuits.
Fig. 4 is that the high voltage amplitude of oscillation of the present invention is less than interval matching unit LERMC circuits.
Fig. 5 is the RMC element circuit block diagrams of first order cascade of the present invention.
Fig. 6 is the RMC element circuit structure charts of first order cascade of the present invention.
Fig. 7 is the RMC element circuit block diagrams of rear class cascade of the present invention.
Fig. 8 is the RMC element circuit structure charts of rear class cascade of the present invention.
Fig. 9 is RCAM memory block diagram of the present invention using matching cable architecture of being association of activity and inertia.
Figure 10 is RCAM memory circuitry structure chart of the present invention using matching cable architecture of being association of activity and inertia.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
As shown in figure 1, the drain electrode and second of the 3rd NMOS tube MN3 being more than in interval matching unit GERMC circuits
Input GE path to be connected, its grid is connected with D# ends, and D# ends are D ends logic NOTs, the source electrode of the 3rd NMOS tube MN3 and the
Four NMOS tube MN4 drain electrode is connected, its source ground, and grid is connected with the 3rd input SL.
As shown in Fig. 2 the drain electrode and second of the 3rd NMOS tube MN3 being less than in interval matching unit LERMC circuits
Input GE path to be connected, its grid is connected with D ends, the drain electrode of the source electrode and the 4th NMOS tube MN4 of the 3rd NMOS tube MN3
It is connected, its source ground, grid is connected with the 4th input SL#, and the SL# is SL logic NOT.
As shown in figure 3, the high voltage amplitude of oscillation is more than in interval matching unit GERMC circuits, the 5th NMOS tube MN5 and the
One PMOS MP1 complementary combinations, the first PMOS MP1 grids are connected with D# ends, and source electrode is connected with the 3rd input SL, the 6th NMOS
Pipe MN6 and the second PMOS MP2 complementary combinations, the second PMOS MP2 grids are connected with D ends, source electrode and the 4th input SL# phases
Even, two are serially connected the grid phase at the node connected between compound tube with the first NMOS tube MN1 and the second NMOS tube MN2
Even, the 3rd NMOS tube MN3 drain electrode is connected with the second input GE path, and its grid is connected with D# ends, the 3rd NMOS tube
MN3 source electrode is connected with the 4th NMOS tube MN4 drain electrode, its source ground, and grid is connected with the 3rd input SL.
As shown in figure 4, the high voltage amplitude of oscillation is less than in interval matching unit LERMC circuits, the 5th NMOS tube MN5 and the
One PMOS MP1 complementary combinations, the first PMOS MP1 grids are connected with D# ends, and source electrode is connected with the 3rd input SL, the 6th NMOS
Pipe MN6 and the second PMOS MP2 complementary combinations, the second PMOS MP2 grids are connected with D ends, source electrode and the 4th input SL# phases
Even, two are serially connected the grid phase at the node connected between compound tube with the first NMOS tube MN1 and the second NMOS tube MN2
Even, the 3rd NMOS tube MN3 drain electrode is connected with the second input GE path, and its grid is connected with D ends, the 3rd NMOS tube MN3
Source electrode be connected with the 4th NMOS tube MN4 drain electrode, the source ground of the 4th NMOS tube MN4, grid and the 4th input SL#
It is connected.
Operation principle is as follows：It is similar with being less than interval matching unit circuit operation principle more than interval matching unit circuit,
In order to describe the convenient operation principle only described more than interval matching unit circuit herein：As SL=D, P points voltage is height, MN1
Opened with MN2 pipes.It is closing that MN3 has one with MN4 pipes.As SL ＞ D, P points voltage is low, and MN1 is closed with MN2 pipes.MN3
Pipe is opened, and MN4 pipes are opened, and Q points pulled down to ground.As SL ＜ D, P points voltage is low, and MN1 is closed with MN2 pipes.MN3 and MN4
Pipe is all closed.
As shown in Figure 5-10, a kind of RCAM memories of interval matching CAM cell circuit composition, including first order cascade
RMC element circuits 100, the RMC element circuits 101 and result treatment element circuit 102 of the cascade of N number of rear class, wherein, rear class cascade
Series n=1,2,3 ... positive integers.The RMC element circuits 100 of first order cascade include equal to chain EQ_Chain circuits 200,
More than chain GE_Chain circuits 201, m circuit 204 and a circuit 205, wherein, the cascade series of circuit 204 m=1,2,3 ... are just
Integer.The RMC element circuits 101 of the rear class cascade include being equal to chain EQ_Chain circuits 202, more than chain GE_Chain circuits
203, m circuits 204 and a circuit 205, wherein, the cascade series of circuit 204 m=1,2,3 ... positive integers.The first order level
The output EQ_G3 equal to chain EQ_Chain circuits 200 in the RMC element circuits 100 of connection respectively with second level circuit 101
Evl ends equal to chain EQ_Chain circuits 202 and the evl ends connection more than chain GE_Chain circuits 203, the second level circuit
The output EQ_G2 equal to chain EQ_Chain circuits 202 in 101 in tertiary circuit 101 respectively with being equal to chain EQ_Chain
The evl ends of circuit 202 and more than chain GE_Chain circuits 203 evl ends connect, the like go down, in final circuit 101
Equal to chain EQ_Chain circuits 202 output EQ_G0 respectively with the first PMOS MP1 in result treatment element circuit 102 and
It is more than chain GE_Chain circuits in 5th NMOS tube MN5 grid connection, the RMC element circuits 100 of the first order cascade
201 GE_G3 connects with the 5th PMOS MP5 in result treatment element circuit 102 and the 4th NMOS tube MN4 grid respectively
Connect, the GE_G2 more than chain GE_Chain circuits 203 in the second level circuit 101 respectively with result treatment element circuit 102
In the 4th PMOS MP4 grid and the 3rd NMOS tube MN3 grid connection ..., in the final circuit 101 be more than chain
The grids and first of the GE_G0 of GE_Chain circuits 203 respectively with the second PMOS MP2 in result treatment element circuit 102
NMOS tube MN1 grid connection.
The circuit 204 is selected from more than interval matching unit GERMC circuits, less than interval matching unit LERMC circuits, height
Voltage swing is more than interval matching unit GERMC circuits or the high voltage amplitude of oscillation less than one in interval matching unit LERMC circuits
Kind, the circuit 205 be selected from it is a kind of with the identical of circuit 204, while second NMOS tube MN2 in circuit is removed, by the
One NMOS tube MN1 source ground.
It is described to be equal to chain EQ_Chain circuits 200, including PMOS MP0 ... MPm-1, MPm and phase inverter INV1 and institute
There is the first NMOS tube MN1 in the 204 and 205 of cascade, wherein, all PMOS MP0 ... MPm-1, MPm source electrode connect power supply electricity
Pressure, is connected with phase inverter INV1 inputs again after its connection that drains, the grid connection first order circuit 204 of the PMOS MPm
In the 5th NMOS tube MN5 source electrode and the 6th NMOS tube MN6 source electrode tie point Pm.PMOS MPm-1 grid connection the
The source electrode of the 5th NMOS tube MN5 in secondary circuit 204 and the 6th NMOS tube MN6 source electrode tie point Pm-1 ... PMOSs
MP1 grid connects the source electrode and the 6th NMOS tube MN6 source electrode tie point of the 5th NMOS tube MN5 in m grades of circuits 204
P1.PMOS MP0 grid connects the source electrode and the 6th NMOS tube MN6 of the 5th NMOS tube MN5 in m+1 grades of circuits 205
Source electrode tie point P0.Phase inverter INV1 output end is connected with signal E0.Phase inverter INV1 inputs connect cascade first simultaneously
First NMOS tube MN1 of level circuit 204 drain electrode, the first NMOS tube MN1 of cascade first order circuit 204 source electrode connection cascade
First NMOS tube MN1 of second level circuit 204 drain electrode ..., by that analogy.The first NMOS tube MN1 source electrodes in circuit 205
Ground connection, the first NMOS tube MN1 of its connection upper level circuit 204 that drains source electrode.
It is described to be more than chain GE_Chain circuits 201, including PMOS MPm+1, MPm+2, MPm+3, NMOS tube MN1 and MN2,
And in the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the 205 of cascade in the 204 of all cascades
The 3rd NMOS tube MN3, the 4th NMOS tube MN4.Wherein, PMOS MPm+1 source electrode meets supply voltage, grid and signal OPEQ
It is connected, its drain electrode is connected with PMOS MPm+2 and MPm+3 source electrode, NMOS tube MN1 drain electrode and PMOS MPm+2 drain electrode
It is connected again with signal G0 after connection, NMOS tube MN1 source ground.The grid phase of PMOS MPm+2 grid and NMOS tube MN1
Even, the grid phase after PMOS MPm+3 drain electrode is connected with NMOS tube MN2 drain electrode again with PMOS MPm+2 and NMOS tube MN1
Even, PMOS MPm+3 grid is connected with NMOS tube MN2 grid, while clk signal is connected, NMOS tube MN2 source electrode connection
Cascade the second NMOS tube MN2 of first order circuit 204 drain electrode, the 2nd NMOS of its source electrode connection cascade second level circuit 204
Pipe MN2 drain electrode ..., by that analogy.The second of 3rd NMOS tube MN3 drain electrodes connection upper level circuit 204 in circuit 205
NMOS tube MN2 source electrode.
It is described to be equal to chain EQ_Chain circuits 202, including PMOS MP0 ... MPm-1, MPm, MPevl, phase inverter INV1 and
The first NMOS tube MN1 in 3rd NMOS tube MN3 and the 204 of all cascades and 205, wherein, the source electrode of all PMOSs connects
Supply voltage, is connected with phase inverter INV1 input and the 3rd NMOS tube MN3 drain electrode connecting node again after drain electrode connection,
Phase inverter INV1 output end is connected with signal EO, and the grid of the PMOS Mpevl is connected with signal evl.The PMOS
The source electrode and the 6th NMOS tube MN6 source electrode tie point of the 5th NMOS tube MN5 in MPm grid connection first order circuit 204
Pm.The source electrode and the 6th NMOS tube MN6 of the 5th NMOS tube MN5 in PMOS MPm-1 grid connection second level circuit 204
Source electrode tie point Pm-1 ... PMOSs MP1 grid connects the source electrode and the of the 5th NMOS tube MN5 in m grades of circuits 204
Six NMOS tube MN6 source electrode tie point P1.PMOS MP0 grid connects the 5th NMOS tube MN5 in m+1 grades of circuits 205
Source electrode and the 6th NMOS tube MN6 source electrode tie point P0.The grid of the 3rd NMOS tube MN3 is connected with signal evl.3rd
First NMOS tube MN1 of NMOS tube MN3 source electrode connection cascade first order circuit 204 drain electrode, cascade first order circuit 204
First NMOS tube MN1 of the first NMOS tube MN1 source electrode connection cascade second level circuit 204 drain electrode ..., by that analogy.Electricity
The first NMOS tube MN1 source grounds in road 205, the first NMOS tube MN1 of its connection upper level circuit 204 that drains source electrode.
It is described to be more than chain GE_Chain circuits 203, including PMOS MPm+1, MPm+2, MPm+3, NMOS tube MN1, MN2 and
The second NMOS tube MN2's, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and cascade in MN4, and the 204 of all cascades
The 3rd NMOS tube MN3 in 205, the 4th NMOS tube MN4.Wherein, PMOS MPm+1 source electrode connects supply voltage, grid and letter
Number OPEQ is connected, and its drain electrode is connected with PMOS MPm+2 and MPm+3 source electrode, NMOS tube MN1 drain electrode and PMOS MPm+2
Drain electrode connection after be connected again with signal G0, NMOS tube MN1 source ground.PMOS MPm+2 grid is with NMOS tube MN1's
Grid be connected, PMOS MPm+3 drain electrode be connected with NMOS tube MN2 drain electrode after again with PMOS MPm+2's and NMOS tube MN1
Grid is connected, and PMOS MPm+3 grid is connected with NMOS tube MN2 grid, while being connected with signal clk.The NMOS tube
MN4 grid with signal evl with being connected again after MN3 grid connection, drain electrode connection NMOS tube MN2 source electrode.The NMOS tube
Second NMOS tube MN2 of MN4 source electrode connection cascade first order circuit 204 drain electrode, its source electrode connection cascade second level circuit
204 the second NMOS tube MN2 drain electrode ..., by that analogy.3rd NMOS tube MN3 drain electrodes connection upper level electricity in circuit 205
The second NMOS tube MN2 on road 204 source electrode.
The RMC element circuit differences that the first order of the present invention and rear class are cascaded be late-class circuit EQ-Chain with
A NMOS tube is added on GE-Chain passages respectively, control signal is evl, evl signals connection prime EO signals, in prime
During the scene being not equal to, this NMOS tube will be transmitted low level shut-off by prime EO.
EQ_Chain passages are by static criteria cmos circuits（static standard cmos circuit）Constitute.GE_
Chain passages are made up of dynamic PF-CDPD AND gates.The GE_Chain courses of work include pre-charging stage and evaluation stage.This
The invention first order and the RMC element circuit operation principles that rear class is cascaded are as follows：Assuming that OPEQ signals are low, then in precharge rank
Section, clk voltages are low, and SL lines loading search data, GO points are charged to low level in advance.In the evaluation stage, clk voltages are height, GO roots
The height of voltage is determined according to whether drop-down passage is opened.If pulling down passage to open, GO points are high level.If drop-down passage is not beaten
Open, GO points keep low level.
Divide three kinds of situation discussion below：
（1）Work as SLmSLm-1…SL0=DmDm-1…D0（SL=D）When, the EQ_Chain nmos logics of first order passage over the ground
Open, pmos logics are closed, EO output HIGH voltages.The output voltage of EO points on the EQ_Chain of rear class is determined according to evl signals
It is fixed.If evl is high level（SL=D of prime）, then EO export high level.If evl is low level（The SL of prime!=D,!=represent
It is unequal）, then EO export low level.For GE_Chain, in evaluation stage, no matter the first order or rear class, GE_Chain's
Passage is all not turned on over the ground, so GO remains low level.
（2）Work as SLmSLm-1…SL0＞ DmDm-1…D0（SL ＞ D）When, for EQ_Chain, whether the first order or after
Level, nmos logics over the ground closed by passage, and pmos logics are opened, EO output low-voltages.For GE_Chain, in evaluation stage,
The GE_Chain of one-level over the ground open by passage, and GO is output as high level.In the evaluation stage, for the GE_Chain of rear class, if evl
For high level（SL=D of prime）, then GE_Chain passage over the ground open, GO is output as high level.If evl is low level（Before
The SL of level!=D）, then GE_Chain passage over the ground be not turned on, GO is output as low level.
（3）Work as SLmSLm-1…SL0＜ DmDm-1…D0（SL ＜ D）When, for EQ_Chain, whether the first order or after
Level, nmos logics over the ground closed by passage, and pmos logics are opened, EO output low-voltages.For GE_Chain, in the evaluation stage, no
By being the first order or rear class, no matter whether evl is high voltage or low-voltage, GE_Chain passage over the ground is not turned on,
GO is output as low level.
The present invention is as follows using the RCAM memory circuitry operation principles for matching cable architecture of being association of activity and inertia：
1st, as OPEQ=0, OPGE=1：
In pre-charging stage, search data are loaded on SL.The Gate3-Gate1 that 4 sections of EQ_Chain are constituted is according to matching
As a result overturn, be as a result output on EQ_G3-EQ_G1 nodes, meanwhile, the data of these nodes also serve as subordinate GE_
Nmos control signals on Chain control the switch of GE_Chain passage over the ground.Now Gate0 can both be completed in this stage
Evaluation, also can complete evaluation in the evaluation stage.Now the clk on 4 sections of GE_Chain is now low level, circuit precharge.
Clk on the evaluation stage, 4 sections of GE_Chain is now high level, the Gate7- being at this moment made up of GE_Chain
Gate4 according to the magnitude relationship of search data and data storage and by prime transmission come control signal decide whether to turn over
Turn.When certain one-level occur search data be more than data storage and by prime transmission come control signal for high level when, this level
Gate is overturn, and exports high level 1.GE_Chain output node GE_G3-GE_G0 and EQ_Chain output node EQ_
G0 is sent to last nor gate, exports final matching operation result.
2nd, as OPEQ=1, OPGE=0：
Circuit is accurately searched, and operation principle is similar to content addressable memories CAM.Now GE_chain, which is in, stops
Dormancy state, saves power consumption.The matching work of circuit is completed by static EQ_chain.
Claims (6)
1. a kind of RCAM memories of interval matching CAM cell circuit composition, it is characterised in that：The RMC cascaded including the first order
RMC element circuits 101 and result treatment element circuit 102 that element circuit 100, three rear classes are cascaded；The first order cascade
RMC element circuits 100 include equal to chain EQ_Chain circuits 200, more than chain GE_Chain circuits 201, the m He of circuit 204
One circuit 205, wherein, the cascade series m of circuit 204 is the positive integer more than zero；The RMC element circuits of the rear class cascade
101 include being equal to chain EQ_Chain circuits 202, more than chain GE_Chain circuits 203, m circuit 204 and a circuit 205,
Wherein, the cascade series m of circuit 204 is the positive integer more than zero；Being equal in the RMC element circuits 100 of the first order cascade
The output EQ_G3 of chain EQ_Chain circuits 200 respectively with the evl equal to chain EQ_Chain circuits 202 in second level circuit 101
It is equal to chain EQ_ in end and the evl ends connection more than chain GE_Chain circuits 203, the second level and tertiary circuit 101
The output EQ_G2 of Chain circuits 202 in the third level and fourth stage circuit 101 respectively with being equal to chain EQ_Chain circuits 202
It is equal to chain EQ_Chain circuits in evl ends and the evl ends connection more than chain GE_Chain circuits 203, fourth stage circuit 101
202 output EQ_G0 respectively with the first PMOS MP1 and the 5th NMOS tube MN5 grid in result treatment element circuit 102
The GE_G3 more than chain GE_Chain circuits 201 in connection, the RMC element circuits 100 of first order cascade respectively with result
In the grid connection of the 5th PMOS MP5 and the 4th NMOS tube MN4 in processing unit circuit 102, the second level circuit 101
The grid respectively with the 4th PMOS MP4 in result treatment element circuit 102 of the GE_G2 more than chain GE_Chain circuits 203
The GE_G2 more than chain GE_Chain circuits 203 in pole and the 3rd NMOS tube MN3 grid connection, the tertiary circuit 101
It is connected respectively with the grid of the 3rd PMOS MP4 in result treatment element circuit 102 and the second NMOS tube MN3 grid, institute
State the GE_G0 more than chain GE_Chain circuits 203 in fourth stage circuit 101 respectively with result treatment element circuit 102
Second PMOS MP2 grid and the first NMOS tube MN1 grid connection.
2. the RCAM memories that a kind of interval matching CAM cell circuit is constituted according to claim 1, it is characterised in that：Institute
Circuit 204 is stated to be selected from more than interval matching unit GERMC circuits, big less than interval matching unit LERMC circuits, the high voltage amplitude of oscillation
It is less than one kind in interval matching unit LERMC circuits, the circuit in interval matching unit GERMC circuits or the high voltage amplitude of oscillation
205 selected from a kind of with the identical of circuit 204, while second NMOS tube MN2 in circuit is removed, by first NMOS tube
MN1 source ground.
3. the RCAM memories that a kind of interval matching CAM cell circuit is constituted according to claim 1, it is characterised in that：Institute
State equal to chain EQ_Chain circuits 200, including m+1 PMOS MP0-MPm, phase inverter INV1 and all cascades 204 and
The first NMOS tube MN1 in 205；Wherein, the source electrode of the m+1 PMOS MP0-MPm connects supply voltage, and it drains after connection
It is connected again with phase inverter INV1 inputs, the grid of the m+1 PMOS MP0-MPm connects the He of m circuit 204 respectively
The source electrode and the 6th NMOS tube MN6 source electrode tie point of the 5th NMOS tube MN5 in one circuit 205；Phase inverter INV1
Output end be connected with signal E0, phase inverter INV1 inputs connect the first NMOS tube MN1 of cascade first order circuit 204 simultaneously
Drain electrode, cascade first order circuit 204 and cascade final circuit 204 between, the first of all cascade circuits 204
First NMOS pipes MN1 of NMOS tube MN1 source electrode connection next stage cascade circuit 204 drain electrode；Cascade final circuit
First NMOS pipes MN1 of 204 the first NMOS pipes MN1 source electrode connection circuit 205 drain electrode, circuit 205
In the first NMOS pipe MN1 source grounds.
4. the RCAM memories that a kind of interval matching CAM cell circuit is constituted according to claim 1, it is characterised in that：Institute
State more than chain GE_Chain circuits 201, including PMOS MPm+1, MPm+2, MPm+3, NMOS tube MN1 and MN2, and all levels
The second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 in the 204 of connection and the 3rd NMOS in the 205 of cascade
Pipe MN3, the 4th NMOS tube MN4；Wherein, PMOS MPm+1 source electrode connects supply voltage, and grid is connected with signal OPEQ, and it leaks
Pole is connected with PMOS MPm+2 and MPm+3 source electrode, NMOS tube MN1 drain electrode be connected with PMOS MPm+2 drain electrode after again with
Signal G0 is connected, NMOS tube MN1 source ground；PMOS MPm+2 grid is connected with NMOS tube MN1 grid, PMOS
Grid again with PMOS MPm+2 and NMOS tube MN1 is connected after MPm+3 drain electrode is connected with NMOS tube MN2 drain electrode, PMOS
MPm+3 grid is connected with NMOS tube MN2 grid, while clk signal is connected, NMOS tube MN2 source electrode connection cascade first
Second NMOS tube MN2 of level circuit 204 drain electrode, between cascade first order circuit 204 and cascade final circuit 204, owns
Second NMOS tube MN2 of the second NMOS tube MN2 of cascade circuit 204 source electrode connection next stage cascade circuit 204 drain electrode；Level
3rd NMOS tube MN3 drain electrode in the source electrode connection circuit 205 for the second NMOS tube MN2 for joining final circuit 204.
5. the RCAM memories that a kind of interval matching CAM cell circuit is constituted according to claim 1, it is characterised in that：Institute
State equal to chain EQ_Chain circuits 202, including m+2 PMOS MP0-MPm and Mpevl, phase inverter INV1 and the 3rd NMOS tube
The first NMOS tube MN1 in MN3 and the 204 of all cascades and 205, wherein, the source electrode of the m+2 PMOS connects power supply electricity
Pressure, is connected with phase inverter INV1 input and the 3rd NMOS tube MN3 drain electrode connecting node again after drain electrode connection, phase inverter
INV1 output end is connected with signal EO, and the grid of the PMOS Mpevl is connected with signal evl；The m+1 PMOS
MP0-MPm grid connect respectively the source electrode of the 5th NMOS tube MN5 in the m circuit 204 and one circuit 205 with
6th NMOS tube MN6 source electrode tie point, the grid of the 3rd NMOS tube MN3 is connected with signal evl, the 3rd NMOS tube MN3
Source electrode connection cascade first order circuit 204 the first NMOS tube MN1 drain electrode, in cascade first order circuit 204 and cascade end
Between level circuit 204, the first of the first NMOS tube MN1 of all cascade circuits 204 source electrode connection next stage cascade circuit 204
NMOS tube MN1 drain electrode；First NMOS tube in the source electrode connection circuit 205 for the first NMOS tube MN1 for cascading final circuit 204
The source ground of the first NMOS tube MN1 in MN1 drain electrode, circuit 205.
6. the RCAM memories that a kind of interval matching CAM cell circuit is constituted according to claim 1, it is characterised in that：Institute
State more than chain GE_Chain circuits 203, including PMOS MPm+1, MPm+2, MPm+3, NMOS tube MN1, MN2 and MN4, Yi Jisuo
There is the 3rd in the 205 of the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 in the 204 of cascade and cascade
NMOS tube MN3, the 4th NMOS tube MN4；Wherein, PMOS MPm+1 source electrode connects supply voltage, and grid is connected with signal OPEQ,
Its drain electrode is connected with PMOS MPm+2 and MPm+3 source electrode, after NMOS tube MN1 drain electrode is connected with PMOS MPm+2 drain electrode
It is connected again with signal G0, NMOS tube MN1 source ground；PMOS MPm+2 grid is connected with NMOS tube MN1 grid,
Grid again with PMOS MPm+2 and NMOS tube MN1 is connected after PMOS MPm+3 drain electrode is connected with NMOS tube MN2 drain electrode,
PMOS MPm+3 grid is connected with NMOS tube MN2 grid, while being connected with signal clk；The grid of the NMOS tube MN4
It is connected again with signal evl after being connected with MN3 grid, drain electrode connection NMOS tube MN2 source electrode, the source electrode of the NMOS tube MN4
Second NMOS tube MN2 of connection cascade first order circuit 204 drain electrode, in cascade first order circuit 204 and cascade final circuit
Between 204, all NMOS tube MN2 of the cascade circuit 204 second NMOS tube MN2 of source electrode connection next stage cascade circuit 204 second
Drain electrode；Cascade the drain electrode of the 3rd NMOS tube MN3 in the NMOS tube MN2 of final circuit 204 second source electrode connection circuit 205.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102354526A (en) * | 2011-06-08 | 2012-02-15 | 大连市恒珑科技发展有限公司 | CAM (content-addressable memory) memory cell capable of interval matching, word circuit and memory |
| CN103366808A (en) * | 2012-03-27 | 2013-10-23 | 瑞萨电子株式会社 | Content addressable memory chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2004295967A (en) * | 2003-03-26 | 2004-10-21 | Kawasaki Microelectronics Kk | Association memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102354526A (en) * | 2011-06-08 | 2012-02-15 | 大连市恒珑科技发展有限公司 | CAM (content-addressable memory) memory cell capable of interval matching, word circuit and memory |
| CN103366808A (en) * | 2012-03-27 | 2013-10-23 | 瑞萨电子株式会社 | Content addressable memory chip |
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