CN103771335A - Gecko-foot-simulated micro-nano grading structure and manufacturing technology thereof - Google Patents
Gecko-foot-simulated micro-nano grading structure and manufacturing technology thereof Download PDFInfo
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Abstract
The invention discloses a manufacturing technology for a gecko-foot-simulated micro-nano grading structure. The manufacturing technology comprises the steps of S1, thermally growing a layer of SiO2 thin film on a clean silicon slice through an LPCVD (low pressure chemical vapor deposition) equipment; S2, spin-coating the surface of the silicon slice with the SiO2 layer with photoresist for photoetching to prepare a circular-hole array pattern; S3, etching the exposed SiO2 through a buffering hydrofluoric acid solution, and transferring the pattern on the photoresist to the SiO2 layer; S4, plating the surface of a sample with a layer of Cu film; S5, performing ultrasonic treatment on acetone or ethyl alcohol, and removing the photoresist from the surface and Cu from the surface of the photoresist through a soluble stripping-off technology; S6, growing a Si micron linear array through a CVD-VLS (chemical vapor deposition-vapor liquid solid) growth technology by taking the Cu prepared by the technology as a catalyst, SiCl4 as a silicon source and H2 as carrier gas; S7, plating the surface of a silicon wire with a layer of Cu film; S8, growing Si nano wires on the surface of the Si micron wire through the CVD-VLS growth technology by taking the Cu prepared in the S7 as a catalyst, the SiCl4 as the silicon source and the H2 as the carrier gas. The Si nano wires are distributed on the surface of the Si micron wire in the micro-nano grading structure provided by the invention, so that the gecko-foot-simulated micro-nano grading structure is obtained; a solution is supplied to design and manufacturing of a dry adhesive material.
Description
Technical field
The invention belongs to field of micro-Na manufacture, be specifically related to a kind of manufacturing process of bionical micro-nano hierarchy.
Background technology
Occurring in nature gecko can walk freely on smooth wall, even can be attached to Quick-climbing on ceiling, and this phenomenon was just observed by Aristotle as far back as B.C. fourth century.This of gecko pin be species specific sticks characteristic and has caused many scholars' concern, also carries out continuing for the research of its Mechanism of Adhesion.2000, the people such as the Autumn of Louis-Clarke institute of the U.S. write articles on Nature, their Accurate Measurement the bonding force of single gecko pin foot bristle, point out gecko to rely on the Van der Waals force between pin foot bristle and body surface and be attached on body surface, disclose the gecko micro-nano hierarchical level structure that easily secret-gecko pin of walking foot bristle itself has fast and guaranteed enough large adhesive force, and can form moment and disappear.The adhesive mechanism of gecko pin is rich in enlightenment, for bionical exploration design, the manufacture of full Van der Waals force dry adhesive provide fabulous reference.
The preparation technology of existing a large amount of imitative gecko pin micro-nano hierarchies has been developed out at present: 2003, the people such as the Geim of Univ Manchester UK have developed the dry adhesive " gecko tape " of imitative gecko pin bristle, and it is mainly based on beamwriter lithography and plasma dry etching (ICP) technique; 2008, the people such as the Hoon Eui Jeong of South Korea Seoul university proposed a kind of manufacturing process of the multistage imitative gecko toe feathering based on organic copy mold.And so on, also have a lot of processes, obtained the micro-nano hierarchy of various imitative gecko pin.But, these manufacture methods are the micro-nano processing technology based on from top to bottom mainly, conventionally neither micro wire and the hierarchy of nano wire, and said method need to use traditional IC equipment such as dry etching equipment, beamwriter lithography equipment conventionally, process costs is high, difficulty of processing is large, unsuitable large-scale production and practical popularization.
At present, also have the hierarchy of grow nanowire on micro wire, this hierarchy includes metal oxide nano-wire (as zinc oxide, tin oxide, titanium oxide etc.) prepared by hydro-thermal method and the nano wire (as silicon, silica etc.) of CVD-VLS growth.The speed of growth of hydro-thermal method is conventionally slow, and in growth course, may need to change solution solution.The method speed of CVD-VLS growth is fast, is mainly ventilation body, easy to prepare.
Because silicon itself has hydrophobicity, the hydrophobic effect of integrated micro-nano hierarchy is well more a lot of than other nano wires of growing on silicon micro wire (as zinc oxide etc.), have automatically cleaning characteristic.In addition, surface of silicon nanowires has oxide layer, and acid and alkali-resistance is nontoxic, with conditional electronic material compatibility, stablizes therefore, adopts silicon more and more to become the focus of research as the material of nano wire.
But, the growth needs of silicon nanowires plates one deck noble metal film equably, as copper, gold etc., and existing metal film coating method, as electron beam evaporation deposition, magnetron sputtering plating etc., on the silicon micro wire that does depth-to-width ratio, be difficult to the uniform film of preparation, thereby cause the hierarchy performance of current silicon nanowires undesirable, process costs and practicality all have problems.
Summary of the invention
The object of the invention is to provide a kind of imitative gecko pin micro-nano hierarchy and manufacturing process, its CVD-VLS nanowire growth technique based on from top to bottom, by adopting the method for then annealing with dipping metal nanoparticle colloidal solution, be to prepare metal film on rice noodles array at silicon more uniformly, thereby can be used for the preparation of Seed Layer.It is low that the method possesses process costs, is convenient to the feature of large-scale production, can realize the practical and industrialization of bionical dryness pasting material.
According to one aspect of the present invention, a kind of manufacturing process of imitative gecko pin micro-nano hierarchy is provided, the method concrete steps comprise:
S1, on clean silicon chip heat growth one deck SiO
2film;
S2, there iing SiO
2the silicon chip surface spin coating photoresist of thin layer also carries out photoetching, prepares array of circular apertures figure;
S3, use buffered hydrofluoric acid solution are to the SiO exposing
2carry out etching, the figure on photoresist is transferred to SiO
2layer;
S4, at sample surfaces plating Cu rete;
S5, in acetone or alcohol, carry out ultrasonicly, remove the Cu rete on surperficial photoresist and photoresist surface by solution-off stripping technology;
S6, the Cu preparing take above-mentioned technique are catalyst, with SiCl
4for silicon source, with H
2for carrier gas, growth Si micro wire array;
S7, in the method for described Si micro wire array surface dipping Cu nano particle colloidal solution after annealing, on the side of silicon micro wire and end face, all prepare Cu film equably;
S8, take the Cu film of described Si micro wire array surface as catalyst, with SiCl
4for silicon source, with H
2for carrier gas, at Si micro wire superficial growth Si nano wire, thereby complete the making of imitating gecko pin micro-nano hierarchy.
Further, SiO described in step S1
2the thickness of film is preferably 300-600nm.
Further, the Circularhole diameter described in step S2 is 3-10 μ m, and center of circle spacing is 7-50 μ m, is right angle or hexagon distribution.
Further, the etch period of mentioning in step S3 is 2-5min.
Further, the Cu film thickness of mentioning in step S4 is 300-800nm, and film plating process comprises magnetron sputtering and electron beam evaporation.
Further, the growth of mentioning in step S6, the time is 5-60min, SiCl
4at H
2in concentration be 1-5%, the length of silicon micro wire is 10-500 μ m.
Further, the Cu film of mentioning in step S7, thickness is 20-100nm, film plating process is the method that then dipping Cu nano particle colloidal solution anneal.
Further, the growth of mentioning in step S8, the time is 1-30min, SiCl
4at H
2in concentration be 1-5%, the end face of silicon micro wire and side surface are all grown silicon nanowires, the length of silicon nanowires is 100nm-30 μ m.
Further, the growth of described Si nano wire and Si micro wire realizes by CVD-VLS growth technique.
The invention also discloses a kind of prepared imitative gecko pin micro-nano hierarchy of above-mentioned technique that utilizes.
In addition, the invention also discloses a kind of imitative gecko pin micro-nano hierarchy, it comprises Si substrate, Si micro wire in described Si substrate surface array distribution, and is covered with the Si nano wire on described Si micro wire surface.
In general, the manufacturing process of micro-nano hierarchy of the present invention is than prior art, technique effect specific as follows:
(1) for the preparation of silicon micro wire, current main flow be prepared by the method for etching from top to bottom.And the present invention to be the method for growing from down to up prepare, can in non-silicon base, grow, save material to reduce costs, also facilitate scale manufacturing simultaneously.
(2) silicon materials itself are hydrophobic materials, and silicon micro wire grow silicon nanowires forms the hierarchy of micro/nano-scale, has hydrophobicity, and hydrophobic effect is well more a lot of than other nano wires of growing on silicon micro wire (as zinc oxide etc.), have automatically cleaning characteristic.In addition natural situation, surface of silicon nanowires has oxide layer, and acid and alkali-resistance is nontoxic, with conditional electronic material compatibility, stable, and is the method preparation of growing from down to up, uses the silicon nanowires cycle of CVD growth short, and cost is low.
(3) the even preparation of nano wire seed is the key of micro-nano integrated technique, requirement film thickness is even, thickness is controlled etc., the process that tradition is prepared seed is difficult to realize at advanced money than structural even preparation as magnetron sputtering, evaporation etc., the present invention has solved this key issue with the method for dipping metal nanoparticle colloidal solution, can be to prepare metal film on rice noodles array at silicon more uniformly, thereby can be used for the preparation of Seed Layer.
(4) this micro-nano structure of the present invention possesses the characteristic of sticking of the biological micro-nano structure of similar gecko pin, can be used for that bionical dryness is sticked, design and the manufacture of super-hydrophobic, self-cleaning material.
Accompanying drawing explanation
Fig. 1 is according to the preparation technology's of the imitative gecko pin micro-nano hierarchy of the embodiment of the present invention flow chart;
Fig. 2 is according to the schematic diagram of the imitative gecko pin micro-nano hierarchy of the embodiment of the present invention, and wherein, 1 is Si substrate, and 2 is Si micro wire, and 3 is Si nano wire.
The specific embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The manufacturing process of a kind of imitative gecko pin micro-nano hierarchy of the present invention, the method concrete steps comprise:
S1, on clean silicon chip heat growth one deck SiO
2film;
S2, there iing SiO
2the silicon chip surface spin coating photoresist of thin layer also carries out photoetching, prepares array of circular apertures figure;
S3, use buffered hydrofluoric acid solution are to the SiO exposing
2carry out etching, the figure on photoresist is transferred to SiO
2layer;
S4, at sample surfaces plating Cu rete;
S5, in acetone or alcohol, carry out ultrasonicly, remove the Cu rete on surperficial photoresist and photoresist surface by solution-off stripping technology;
S6, the Cu preparing take above-mentioned technique are catalyst, with SiCl
4for silicon source, with H
2for carrier gas, growth Si micro wire array;
S7, in the method for described Si micro wire array surface dipping Cu nano particle colloidal solution after annealing, on the side of silicon micro wire and end face, all prepare Cu film equably;
S8, take the Cu film of described Si micro wire array surface as catalyst, with SiCl
4for silicon source, with H
2for carrier gas, at Si micro wire superficial growth Si nano wire, thereby complete the making of imitating gecko pin micro-nano hierarchy.
Below in conjunction with specific embodiment, technical scheme of the present invention is specifically described.
Embodiment 1:
The manufacturing process of the micro-nano hierarchy of a kind of imitative gecko pin in the present embodiment, specifically can comprise step:
S1, use LPCVD equipment is heat growth one deck 300nm SiO on clean silicon chip
2film;
S2, there iing SiO
2the silicon chip surface spin coating photoresist of layer also carries out photoetching, prepares array of circular apertures figure, and Circularhole diameter is 3 microns, and center of circle spacing is 7 microns, for right angle distributes;
S3, use buffered hydrofluoric acid solution are to the SiO exposing
2carry out etching 2min, the figure on photoresist is transferred to SiO
2layer;
S4, at plated surface one deck 300nm of above-mentioned sample Cu film;
S5, in acetone or alcohol, carry out ultrasonicly, remove the Cu on surperficial photoresist and photoresist surface by solution-off stripping technology;
S6, utilize CVD-VLS growth technique, the Cu preparing take above-mentioned technique is catalyst, with SiCl
4for silicon source, with H
2for carrier gas, concentration is 1%, growth Si micro wire array 10min;
S7, use the method for dipping Cu nano particle colloidal solution after annealing to prepare one deck Cu film on silicon micro wire surface;
S8, utilize CVD-VLS growth technique, the Cu film of preparing take S7 is catalyst, with SiCl
4for silicon source, with H
2for carrier gas, concentration is 1%, at Si micro wire superficial growth Si nano wire (time is 1min such as).
Embodiment 2
A kind of manufacturing process of micro-nano hierarchy of imitative gecko pin in the present embodiment, specifically can comprise step:
S1, use LPCVD equipment is heat growth one deck 600nm SiO on clean silicon chip
2film;
S2, there iing SiO
2the silicon chip surface spin coating photoresist of layer also carries out photoetching, prepares array of circular apertures figure, and Circularhole diameter is 10 microns, and center of circle spacing is 50 microns, for hexagon distributes;
S3, use buffered hydrofluoric acid solution are to the SiO exposing
2carry out etching 5min, the figure on photoresist is transferred to SiO
2layer;
S4, at plated surface one deck 800nm of above-mentioned sample Cu film;
S5, in acetone or alcohol, carry out ultrasonicly, remove the Cu on surperficial photoresist and photoresist surface by solution-off stripping technology;
S6, utilize CVD-VLS growth technique, the Cu preparing take above-mentioned technique is catalyst, with SiCl
4for silicon source, with H
2for carrier gas, concentration is 5%, growth Si micro wire array 60min;
S7, use the method for dipping Cu nano particle colloidal solution after annealing to prepare one deck Cu film on silicon micro wire surface;
S8, utilize CVD-VLS growth technique, the Cu film of preparing take S7 is catalyst, with SiCl
4for silicon source, with H
2for carrier gas, concentration is 5%, at Si micro wire superficial growth Si nano wire 60min.
Certainly, above-described embodiment is only that technical scheme of the present invention is not restricted to the described embodiments for explaining the present invention, for example, in step S1, on silicon chip, the technique of heat growth silicon dioxide film is not limited to LPCVD equipment, and film thickness all can between 300nm～600nm.The size of the array of circular apertures in step S2 can determine according to actual needs, and for example Circularhole diameter can be 3-10 micron, and center of circle spacing can be preferably 7-50 micron, array can be at right angles or hexagon distribute.Etch period in step S3 is not limited to above-mentioned value, for example, all can at 2-5min.Cu film thickness in step S4 between 300nm～800nm all can, film plating process can be selected existing maturation process, such as magnetron sputtering and electron beam evaporation etc.In step S6, in the growth of Si micro wire array, SiCl
4at H
2in concentration be preferably 1-5%, growth time can according to actual conditions determine, for example, in 5-60min.In step S7, Cu film thickness can be determined as required, for example, be preferably 20-100nm.In step S8, SiCl
4at H
2in concentration be preferably 1-5%, growth time can according to actual conditions determine, for example, in 1-60min.In addition, the growth of Si nano wire and Si micro wire preferably realizes by CVD-VLS growth technique, can certainly adopt other techniques.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a preparation method for imitative gecko pin micro-nano hierarchy, for the preparation of the micro-nano hierarchy with gecko pin character, is characterized in that, the method comprises the steps:
S1, on silicon chip heat growth one deck SiO
2film;
S2, containing described SiO
2the silicon chip surface spin coating photoresist of thin layer also carries out photoetching, prepares array of circular apertures figure;
S3, use buffered hydrofluoric acid solution are to the SiO exposing
2carry out etching, the figure on photoresist is transferred to SiO
2layer;
S4, through step S3 sample surfaces after treatment plating one deck Cu film;
S5, in acetone or alcohol, carry out ultrasonicly, remove the Cu film on surperficial photoresist and photoresist surface by solution-off stripping technology;
S6, take above-mentioned Cu film as catalyst, with SiCl
4for silicon source, with H
2for carrier gas, at the Si micro wire array of growing on step S5 sample after treatment;
S7, use the method for dipping Cu nano particle colloidal solution after annealing to prepare one deck Cu film in described Si micro wire array surface;
S8, the Cu film of preparing take step S7 are catalyst, with SiCl
4for silicon source, with H
2for carrier gas, at Si micro wire superficial growth Si nano wire, can realize the preparation of imitative gecko pin micro-nano hierarchy.
2. preparation method as claimed in claim 1, is characterized in that, SiO described in step S1
2the thickness of film is 300-600nm.
3. preparation method as claimed in claim 1 or 2, is characterized in that, the Circularhole diameter described in step S2 is preferably 3-10 micron, and each circular hole center of circle spacing is preferably 7-50 micron.
As described in any one in claim 1-3 preparation method, it is characterized in that, etch period described in step S3 is 2-5min.
As described in any one in claim 1-4 preparation method, it is characterized in that, the Cu film thickness described in step S4 is 300-800nm.
As described in any one in claim 1-5 preparation method, it is characterized in that, the growth described in step S6 and S8, the time is 5-60min, SiCl
4at H
2in concentration be 1-5%, the length of silicon micro wire is 10-500 μ m.
As described in any one in claim 1-6 preparation method, it is characterized in that, the Cu film thickness described in step S7 is 20-100nm.
As described in any one in claim 1-7 preparation method, it is characterized in that, the growth of mentioning in step S8, the time is 1-30min, SiCl
4at H
2in concentration be 1-5%, the end face of silicon micro wire and side surface are all grown silicon nanowires, the length of silicon nanowires is 100nm-10 μ m.
9. an imitative gecko pin micro-nano hierarchy that adopts the preparation method described in claim 1-8 any one to obtain.
10. an imitative gecko pin micro-nano hierarchy, is characterized in that, comprises Si substrate, Si micro wire in described Si substrate surface array distribution, and is covered with the Si nano wire on described Si micro wire surface.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104627952A (en) * | 2015-01-13 | 2015-05-20 | 华中科技大学 | Preparation method of flexible super-hydrophobic and super-oleophobic structure |
| CN105668511A (en) * | 2016-03-03 | 2016-06-15 | 广东工业大学 | Method for preparing electronic device through micro-nano machining |
| CN106281217A (en) * | 2016-07-26 | 2017-01-04 | 中国石油大学(北京) | A kind of bionic surface, Preparation Method And The Use |
| CN109232965A (en) * | 2018-10-08 | 2019-01-18 | 中国工程物理研究院化工材料研究所 | A kind of preparation method of bionical dry state bonding silicon rubber foam |
| CN109545730A (en) * | 2017-09-21 | 2019-03-29 | 三星电子株式会社 | Supporting substrate, electronic device manufacturing method, semiconductor package part and manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070166899A1 (en) * | 2006-01-14 | 2007-07-19 | Tsinghua University | Method of synthesizing silicon wires |
| CN101779271A (en) * | 2007-07-19 | 2010-07-14 | 加利福尼亚技术学院 | Structure of the silicon linear array of vertical arrangement and forming method thereof |
| CN101823685A (en) * | 2010-04-30 | 2010-09-08 | 华中科技大学 | Bionic micro/nano structure preparing method |
| CN102738298A (en) * | 2012-06-01 | 2012-10-17 | 华中科技大学 | Micro-nano composite structure of solar battery photo anode and preparation method thereof |
-
2014
- 2014-01-15 CN CN201410017421.5A patent/CN103771335B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070166899A1 (en) * | 2006-01-14 | 2007-07-19 | Tsinghua University | Method of synthesizing silicon wires |
| CN101779271A (en) * | 2007-07-19 | 2010-07-14 | 加利福尼亚技术学院 | Structure of the silicon linear array of vertical arrangement and forming method thereof |
| CN101823685A (en) * | 2010-04-30 | 2010-09-08 | 华中科技大学 | Bionic micro/nano structure preparing method |
| CN102738298A (en) * | 2012-06-01 | 2012-10-17 | 华中科技大学 | Micro-nano composite structure of solar battery photo anode and preparation method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104627952A (en) * | 2015-01-13 | 2015-05-20 | 华中科技大学 | Preparation method of flexible super-hydrophobic and super-oleophobic structure |
| CN105668511A (en) * | 2016-03-03 | 2016-06-15 | 广东工业大学 | Method for preparing electronic device through micro-nano machining |
| CN105668511B (en) * | 2016-03-03 | 2017-06-09 | 广东工业大学 | A kind of method that micro-nano technology prepares electronic device |
| CN106281217A (en) * | 2016-07-26 | 2017-01-04 | 中国石油大学(北京) | A kind of bionic surface, Preparation Method And The Use |
| CN109545730A (en) * | 2017-09-21 | 2019-03-29 | 三星电子株式会社 | Supporting substrate, electronic device manufacturing method, semiconductor package part and manufacturing method |
| CN109232965A (en) * | 2018-10-08 | 2019-01-18 | 中国工程物理研究院化工材料研究所 | A kind of preparation method of bionical dry state bonding silicon rubber foam |
| CN109232965B (en) * | 2018-10-08 | 2021-01-26 | 中国工程物理研究院化工材料研究所 | Preparation method of bionic dry-state bonding silicone rubber foam |
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