CN103763188B

CN103763188B - A kind of polymorphic type message real-time processing method and device

Info

Publication number: CN103763188B
Application number: CN201410030118.9A
Authority: CN
Inventors: 张炼; 余林; 刘元春; 冯涛
Original assignee: Sichuan Jiuzhou ATC Technology Co Ltd
Current assignee: Sichuan Jiuzhou ATC Technology Co Ltd
Priority date: 2014-01-22
Filing date: 2014-01-22
Publication date: 2016-08-31
Anticipated expiration: 2034-01-22
Also published as: CN103763188A

Abstract

The present invention relates to ADS B system Data Detection field, particularly relate to a kind of polymorphic type message real-time processing method and device.The technical problem to be solved is: the problem existed for prior art, a kind of Large Copacity polymorphic type message real-time processing method and device are provided, this method and device are by arranging multi-level buffer and all types of message of synchronization process, meet ADS B system needs and possess reception per second more than 700 ADS B messages of process and the ability of more than 32 FIS B messages, in the case of guaranteeing that message is not lost, to greatest extent message is processed in real time, substantially increase the work efficiency of system.This device includes receiving packet storage module, synchronous head detection module, time wait module, L2 cache module, message decoding module and plaintext extraction module, for FIS B type and ADS B type message data are carried out multiple threads parallel processing.Present invention application and Large Volume Data diversiform data Message processing field.

Description

A kind of polymorphic type message real-time processing method and device

Technical field

The present invention relates to ADS-B system data detection field, particularly relate to a kind of polymorphic type message real-time processing method and Device.

Background technology

In order to enable the aircraft on course line in spatial domain safely, effectively with planned flight, need to fly in spatial domain The flight of machine monitors the most in real time.Radar surveillance means of the prior art use interrogator-responder system to visit target Surveying, the straightline propagation of radar beam defines a large amount of radar shadown, it is impossible to cover the area such as ocean and desert；Radar swing circle Limit the raising of data updating rate, thus limit the raising monitoring precision；Additionally, radar surveillance cannot obtain the meter of aircraft Draw the situation data such as air route, speed, limit raising and the ability of short-term collision detection alarm of tracking accuracy.

In automatic dependent surveillance broadcast, (Automatic Dependent Surveillance Broadcast is called for short ADS-B), in system, ground installation and other airborne vehicles receive by airborne satellite-based navigation and alignment system raw by aeronautical data chain The precise location information become.Wherein, satellite system, aircraft and ground based system realize air-ground integrated association by high-speed data chain With monitoring that in spatial domain, the flight of aircraft is dynamic.ADS-B not only overcomes the defect existed in prior art by radar surveillance, with Time have that precision is high, turnover rate fast, applied range, ground installation construction and the advantage such as maintenance cost is low.

ADS-B is as an important surveillance technology in navigation system, at radar-covered area, and can be as radar surveillance Effectively supplement, radar surveillance is calibrated or mends blind；At non-radar-covered area, can as independent surveillance technology, New supervision means are provided.When being embodied as, certain ADS-B system needs possess reception per second and processes 700 ADS-B messages and 32 The ability of bar FIS-B message, processes capacity to system and process real-time is proposed the highest requirement.

Certain ADS-B system needs possess reception per second and processes 700 ADS-B messages and the ability of 32 FIS-B messages, right The capacity that processes of system is proposed the highest requirement with processing real-time.Prior art has the disadvantage that:

1, can not be suitable power system capacity is set, power system capacity is crossed conference and is consumed major part resource, causes system to be run slow Slow and unstable, the least meeting of power system capacity causes message dropping；

2, system real time processes the highest, and real-time processes not, can cause the message that previously arrived the most untreated complete just Expired, and the message of follow-up arrival can not be processed and lose.

3, system works long hours a process, causes other tasks of system to be hung up for a long time, and system processes appoints at one In business, cause running efficiency of system low.

Summary of the invention

The technical problem to be solved is: the problem existed for prior art, it is provided that a kind of polymorphic type message Real-time processing method and device, this method and device, by arranging multi-level buffer and all types of message of synchronization process, meet ADS-B System needs possess reception per second and processes more than 700 ADS-B messages and the ability of more than 32 FIS-B messages, is guaranteeing report In the case of literary composition is not lost, to greatest extent message is processed in real time, substantially increase the work efficiency of system.Solution of the present invention Determine problems with:

1, the message first arrived in first order relief area is read by relief area, the second level, thus avoids a large amount of message to pile up, The message above arrived is covered by the message causing follow-up arrival, reaches to discharge the purpose in the space of first order relief area.

2, system uses multiple message types method for parallel processing, in the case of not knowing message particular type, reads Message synchronizes to carry out the synchronous head detection of FIS-B, ADS-B LONG and ADS-B BASIC, is determining that message is ADS-B type, But in the case of being not determined as ADS-B LONG and ADS-B BASIC, read message and synchronize to carry out ADS-B LONG and ADS-B The detection of BASIC, is greatly improved the processing capability in real time of system；

3, system uses the mode of synchronization on processing, and while receiving message, processes message in real time, will receive and process Synchronous working, while using multistage Large Copacity relief area to guarantee that message is not lost, the detection of synchronization process synchronous head, type of message Decoding, multi-process synchronizes to carry out, substantially increases the work efficiency of system.

The technical solution used in the present invention is as follows:

A kind of polymorphic type message real-time processing method includes:

Step 1: receive packet storage module 1 and FIS-B message reception memory element 11 and ADS-B packet storage unit is set 12, described FIS-B message receives memory element 11, ADS-B packet storage unit 12 receives simultaneously and stores and inputs from outside Message；

Step 2: synchronous head detection module 2 reads and receives FIS-B message reception memory element 11 and ADS-B packet storage list The data message of storage in unit 12, carries out FIS-B type of synchronization head and the detection of ADS-B type of synchronization head, if FIS-B message receives Memory element 11 has FIS-B categorical data message, then FIS-B categorical data start of message (SOM) address is stored in FIS-B message and synchronizes Head detector unit 21, and export FIS-B type of synchronization leader will；If ADS-B packet storage unit 12 has FIS-B number of types simultaneously According to message, then ADS-B categorical data start of message (SOM) address is stored in ADS-B message synchronous head detector unit 22, and exports ADS-B Type of synchronization leader will；

Step 3: the time waits that module 3 detects FIS-B synchronous head mark and ADS-B type of synchronization leader will, according to right Answer FIS-B type message waiting time and ADS-B type message waiting time, it is ensured that complete FIS-B type or ADS-B type Data message stores the FIS-B message of correspondence and receives memory element 11 or ADS-B packet storage unit 12；

Step 4: L2 cache module 4 is respectively provided with FIS-B message L2 cache unit 41, ADS-B message L2 cache Unit 42, FIS-B message L2 cache unit 41 is used for detecting the empty flag bit of FIS-B message synchronous head detector unit 21, if Empty flag bit is 0, then it represents that FIS-B message synchronous head detector unit storage has FIS-B categorical data start of message (SOM) address；FIS- B message L2 cache unit 41 is according to FIS-B categorical data start of message (SOM) address, FIS-B type message waiting time, from FIS- B receives packet storage module 11 and reads FIS-B message, and is deposited in FIS-B message level 2 buffering unit 41, has stored one FIS-B message flag signal is exported after the FIS-B message that bar is complete；ADS-B message L2 cache unit 42 is used for detecting ADS-B The empty flag bit of message synchronous head detector unit 22, if empty flag bit is 0, then it represents that ADS-B message synchronous head detector unit is deposited Contain ADS-B categorical data start of message (SOM) address；ADS-B message L2 cache unit 42 rises according to ADS-B categorical data message Beginning address, ADS-B type message waiting time, receive packet storage module 12 from ADS-B and read ADS-B message, and deposited Enter in ADS-B message level 2 buffering unit 42, after having stored a complete ADS-B message, export ADS-B message flag signal；

Step 5: message decoding module reads FIS-B message and the ADS-B message of L2 cache module 4 output, goes forward side by side The message decoding of row corresponding types, exports successfully decoded mark to extraction module in plain text；

Step 6, in plain text extraction module are according to successfully decoded mark, it is thus achieved that the particular type of message and the plaintext of message.

Further, in described step 1, FIS-B message receives memory element, ADS-B message receives memory element storage number According to identical, described FIS-B message receives memory element and includes the first buffer RAM1 and the second buffer RAM2, ADS-B message Receive memory element and include the 3rd buffer RAM3 and the 4th buffer RAM4, described first buffer RAM1 and the second buffer RAM2 is ping-pong operation, and described 3rd buffer RAM3 and the 4th buffer RAM4 is ping-pong operation, described first buffer RAM1, the second buffer RAM2, the 3rd buffer RAM3, the 4th buffer RAM4 data depth are 2ⁿ, then FIS-B message receives Memory element 11 I/O Address width is (n+1) position, and FIS-B message receives memory element 11 address highest order and distinguishes The order that message reaches, the message first arrived exists in the first buffer RAM1 that address highest order is 0, when the first buffer After RAM1 is filled with, FIS-B message receives memory element 11 address highest order will become 1, and the message now arrived exists second and delays In storage RAM2, after the first buffer RAM2 is filled with, FIS-B message receives memory element 11 address highest order and becomes 0, subsequently The message reached exists in the first buffer RAM1, circulation storage；ADS-B message receives memory element 12 address highest order to be come Distinguishing the order that message reaches, the message first arrived exists in the 3rd buffer RAM3 that address highest order is 0, when the 3rd caching After device RAM3 is filled with, ADS-B message receives memory element 12 address highest order will become 1, and the message now arrived exists the 4th In buffer RAM4, after the 4th buffer RAM4 is filled with, ADS-B message receives memory element 12 address highest order will become 0, The message consequently reached exists in the 3rd buffer RAM3, circulation storage；The described FIS-B type waiting time is FIS-B message Length M1 byte, each bit transmission time is K1, then the FIS-B type waiting time is M1*8*K1；ADS-B type etc. The time for the treatment of is M2 byte of FIS-B message length, and each bit transmission time is K2, then the ADS-B type waiting time is M2* 8*K2, wherein 550 < M1 < 600;40<M2<50.

Further, in described step 2, synchronous head detection module 2 reads and receives relief area storage in packet storage module Message, carries out FIS-B type message and the detection of ADS-B type message synchronous head, and concrete steps include:

Step 21: synchronous head detection module reads FIS-B message and receives the first buffer RAM1 data in memory element 11 Data message in message and the second buffer RAM2, reads N bit data in FIS-B message reception memory element 1 in order and enters Row synchronous head detects, and when FIS-B message reception memory element 11 address highest addresses is 0, reads in the first buffer RAM1 Data, FIS-B message receives memory element 11 address highest addresses when being 1, reads the data in the second buffer RAM2； Meanwhile, synchronous head detection module reads ADS-B message and receives the 3rd buffer RAM3 or the 4th buffer in memory element 12 Data message in RAM4, is read out N bit data in order and carries out synchronous head detection, and ADS-B message receives memory element 12 When address highest addresses is 0, reading the data in the 3rd buffer RAM3, ADS-B message receives memory element 12 address When high address is 1, read the data in the 4th buffer RAM4；

Step 22: when synchronous head detection module 2 carries out synchronous head detection to FIS-B message, reads the reception of FIS-B message and deposits When the top N data of FIS-B message are identical with standard FIS-B message synchronous head in storage unit, then it is judged to occur that FIS-B reports Literary composition, FIS-B message synchronous head detector unit 21 records FIS-B message corresponding to now FIS-B message and receives memory element 11 Address, and export FIS-B message synchronous head mark；Otherwise, for FIS-B message does not occurs, return step 21 simultaneously；

Step 23: when synchronous head detection module 2 carries out synchronous head detection to ADS-B message, reads the reception of ADS-B message and deposits When the top N data of ADS-B message are identical with standard ADS-B message synchronous head in storage unit, then it is judged to occur that ADS-B reports Literary composition, ADS-B message synchronous head detector unit 22 records ADS-B message corresponding to now ADS-B message and receives memory element 12 Address, and export ADS-B message synchronous head mark；Otherwise, for ADS-B message does not occurs, return step 21 simultaneously.

Further, described step 5 read the message of L2 cache module 4 output according to message decoding module and carry out The message decoding of corresponding types, exports successfully decoded mark in plain text extraction module, and detailed process is:

Step 51: if the FIS-B message decoding unit of message decoding module 5 detect that L2 cache module 4 exports be During FIS-B message flag signal, the complete FIS-B message read from FIS-B message L2 cache unit 41, i.e. root According to the message amount of FIS-B message L2 cache unit 41 storage, by FIS-B message L2 cache unit 41 indicates message bar Adding up in the address of number, reads FIS-B message；

Step 52；The FIS-B message read from FIS-B message L2 cache unit 41 decodes；If be decoded into Merit, FIS-B message decoding unit 51 exports the successfully decoded mark of FIS-B message, if decoding failure, returns step 51, reads Next message decodes；

If the ADS-B LONG message decoding unit of step 53 message decoding module 5 detects, L2 cache module 4 is defeated During the ADS-B message flag signal gone out, the complete ADS-B message read from ADS-B message L2 cache unit 42, I.e. read the ADS-B message in ADS-B message L2 cache unit 42 according to ADS-B LONG message length, be decoded, if Successfully decoded, then the ADS-B LONG message decoding unit output ADS-B successfully decoded mark of LONG message；

Step 54: if the ADS-B BASIC message decoding unit of message decoding module 5 detects, L2 cache module 4 is defeated During the ADS-B message flag signal gone out, the complete ADS-B message read from ADS-B message L2 cache unit 42, I.e. read the ADS-B message in ADS-B message L2 cache unit 42 according to ADS-B BASIC message length, be decoded, if Successfully decoded, then the ADS-B BASIC message decoding unit output ADS-B successfully decoded mark of BASIC message.

Further, described step 6 concrete steps include:

FIS-B in extraction module extraction unit in plain text in plain text, according to the successfully decoded mark of FIS-B message, it is thus achieved that FIS-B In plain text, FIS-B message is stored in FIS-B extraction unit in plain text plus FIS-B synchronous head mark to message in plain text；

ADS-B in extraction module extraction unit in plain text in plain text, according to the ADS-B successfully decoded mark of LONG message, it is thus achieved that In plain text, ADS-B message is stored in ADS-B extraction unit in plain text plus ADS-B LONG synchronous head mark to ADS-BLONG message in plain text；

ADS-B in extraction module extraction unit in plain text, according to the ADS-B successfully decoded mark of BASIC message, obtains in plain text Obtaining ADS-B BASIC message in plain text, ADS-B message is stored in ADS-B extraction in plain text plus ADS-B BASIC synchronous head mark in plain text Unit.

A kind of polymorphic type message real-time processing device includes:

Receive packet storage module 1, being used for, FIS-B message is set and receives memory element 11 and ADS-B packet storage unit 12, described FIS-B message receives memory element 11, ADS-B packet storage unit 12 receives simultaneously and stores and inputs from outside Message；

Synchronous head detection module 2, is used for reading reception FIS-B message and receives memory element 11 and ADS-B packet storage list The data message of storage in unit 12, carries out FIS-B type of synchronization head and the detection of ADS-B type of synchronization head, if FIS-B message receives Memory element 11 has FIS-B categorical data message, then FIS-B categorical data start of message (SOM) address is stored in FIS-B message and synchronizes Head detector unit 21, and export FIS-B type of synchronization leader will；If ADS-B packet storage unit 12 has ADS-B number of types simultaneously According to message, then ADS-B categorical data start of message (SOM) address is stored in ADS-B message synchronous head detector unit 22, and exports ADS-B Type of synchronization leader will;

Time waits module, for according to FIS-B or the ADS-B type message waiting time, detects that synchronous head detects mould When the FIS-B synchronous head mark of block output and ADS-B type of synchronization leader will, receive FIS-B type message and ADS-B type report Literary composition also stores corresponding FIS-B message reception memory element 11, ADS-B packet storage unit 12；

L2 cache module, is respectively provided with FIS-B message L2 cache unit 41, ADS-B message L2 cache unit 42, FIS-B message L2 cache unit 41 is for detecting the empty flag bit of FIS-B message synchronous head detector unit 21, if empty flag bit It is 0, then it represents that FIS-B message synchronous head detector unit storage has FIS-B categorical data start of message (SOM) address；FIS-B message two Level buffer unit 41, according to FIS-B categorical data start of message (SOM) address, FIS-B type message waiting time, receives report from FIS-B Literary composition memory module 11 reads FIS-B message, and is deposited in FIS-B message level 2 buffering unit 41, has stored one completely FIS-B message after export FIS-B message flag signal；It is same that ADS-B message L2 cache unit 42 is used for detecting ADS-B message The empty flag bit of step head detector unit 22, if empty flag bit is 0, then it represents that ADS-B message synchronous head detector unit storage has ADS-B categorical data start of message (SOM) address；ADS-B message L2 cache unit 42 is according to ADS-B categorical data start of message (SOM) ground Location, ADS-B type message waiting time, receive packet storage module 12 from ADS-B and read ADS-B message, and be deposited into In ADS-B message level 2 buffering unit 42, after having stored a complete ADS-B message, export ADS-B message flag signal；

Message decoding module, message decoding module reads FIS-B message and the ADS-B report of L2 cache module 4 output Literary composition, and carry out the message decoding of corresponding types, export successfully decoded mark to extraction module in plain text；

Extraction module in plain text, for according to successfully decoded mark, it is thus achieved that the particular type of message and the plaintext of message.

Further, described reception packet storage module 1 includes that FIS-B message receives memory element and ADS-B message connects Harvesting storage unit, it is identical with ADS-B message reception storage unit stores data that FIS-B message receives memory element, described FIS-B Message receives memory element and includes the first buffer RAM1 and the second buffer RAM2, and FIS-B message receives memory element and includes 3rd buffer RAM3 and the 4th buffer RAM4, described first buffer RAM1 and the second buffer RAM2 is ping-pong operation, Described 3rd buffer RAM3 and the 4th buffer RAM4 is ping-pong operation, described first buffer RAM1, the second buffer RAM2, the 3rd buffer RAM3, the 4th buffer RAM4 data depth are 2ⁿ, then FIS-B message reception memory element 11 inputs OPADD width is (n+1) position, and it is suitable that FIS-B message receives that memory element 11 address highest order distinguishes that message reaches Sequence, the message first arrived exists in the first buffer RAM1 that address highest order is 0, after the first buffer RAM1 is filled with, FIS-B message receives memory element 11 address highest order will become 1, and the message now arrived exists in the second buffer RAM2, After the first buffer RAM2 is filled with, FIS-B message receives memory element 11 address highest order and becomes 0, the message consequently reached Exist in the first buffer RAM1, circulation storage；ADS-B message reception memory element 12 is distinguished message by address highest order and is reached The order arrived, the message first arrived exists in the 3rd buffer RAM3 that address highest order is 0, when the 3rd buffer RAM3 is filled with After, ADS-B message receives memory element 12 address highest order will become 1, and the message now arrived exists the 4th buffer RAM4 In, after the 4th buffer RAM4 is filled with, ADS-B message receives memory element 12 address highest order will become 0, consequently reach Message exists in the 3rd buffer RAM3, circulation storage；Described FIS-B or the ADS-B type waiting time calculates process: FIS- The B type waiting time is M1 byte of FIS-B message length, and each bit transmission time is K1, then when FIS-B type waits Between be M1*8*K1；The ADS-B type waiting time is M2 byte of FIS-B message length, and each bit transmission time is K2, Then the ADS-B type waiting time is M2*8*K2.

Further, synchronous head detection module 2 reads and receives the message of relief area storage in packet storage module, carries out FIS-B type message and the detection of ADS-B type message synchronous head, concrete steps include:

Further, described message decoding module reads the message of L2 cache module 4 output and carries out corresponding types Message decodes, and exports successfully decoded mark in plain text extraction module, and detailed process is:

Further, described plaintext extraction module specific works process includes；

In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:

1, the problem arranged for power system capacity, solves by arranging the jumbo relief area of two-stage, adopts in technical scheme Jointly solve by reception packet storage module and L2 cache module.Receive packet storage module, for according to FIS-B type and ADS-B type each opens up two jumbo relief areas, uses two jumbo bufferings in turn by address highest order District, by the message Coutinuous store twice to the UNKNOWN TYPE received, is divided into FIS-B type and ADS-B type by UNKNOWN TYPE, It is easy to follow-up parallel work-flow, by utilizing address highest order to use relief area in turn, while extending buffer pool size, keeps away Exempt from relief area and open up excessive problem.L2 cache module, for the time arrived according to complete message, rising in conjunction with message Beginning address, reads message from first order relief area and is stored in Secondary buffer, makes effective message and unknown message isolation so that report Literary composition synchronous head detection and message decoding are able to parallel processing.Release (by reading the message in first order relief area, reaches release The purpose of capacity) while buffer pool size, serial process flow process is converted into parallel processing, makes power system capacity and work effect Rate is greatly enhanced.

2, process problem for system real time, technical scheme uses and receives packet storage module, synchronous head detection mould Block, the time waits module, L2 cache module, and the multimode such as message decoding module is mutually linked, and method for parallel processing solves. Receive packet storage module, for each opening up two jumbo relief areas according to FIS-B type and ADS-B type, will not Know that type is divided into FIS-B type and ADS-B type, it is simple to rear end carries out different types of synchronous head detection parallel；Synchronous head is examined Survey module, parallel FIS-B type and ADS-B type are detected, decrease first detection FIS-B type and detect ADS-B class again The time of type；Time waits module, arranges the different waiting time for FIS-B type and ADS-B type, it is to avoid system is long The wait of time；L2 cache module, stores respectively by effective FIS-B type and ADS-B type, it is simple to follow-up carry out parallel Different types of message decodes；Message decoding module, by synchronizing the message of FIS-B and the ADS-B type determined, carry out must The message decoding operation of FIS-B, ADS-B LONG and the ADS-B BASIC type wanted, decreases and successively carries out dissimilar The time that decoding waits.Each module each works and associated working all substantially increases the processing capability in real time of system.

3, work long hours in some process for system, cause the problem that running efficiency of system is low, in technical scheme Using and receive packet storage module, synchronous head detection module, the time waits module, L2 cache module, message decoding module etc. The method for parallel processing of multimode solves.Stored by parallel reception, use parallel synchronous head to detect, pass through synchronous head The result of detection, the parallel time that arranges wait, carry out L2 cache parallel, by the result of L2 cache, parallel carrying out Message decodes, multiple parallel settings carried out and process, enables the system to be operated in multiple process simultaneously, substantially increases system Operational efficiency.Article one, message is while carrying out subsequent treatment, processes next message.Be equivalent to a flowing water Line has carried out the fractionation of multi-process.It is serial for a message, is parallel for a plurality of.

4, a length of 4448bit of a FIS-B message, the reception time is 4.2ms；Process a message time be 4.59ms；If serial operation mode, the time processing a message is 8.79ms for both sums；Described in employing system Method, accepts to process, and is included in the process time reception time, only completes a message with the time of 4.59ms Reception and process；RAM1 and RAM2 opened up is 8192bit, can accommodate the message more than 3, but when Article 2 is completely reported The when that literary composition arriving, Article 1 message has been read out to RAM5 process, and having vacateed space can continue to, and level cache is protected Demonstrate,prove space and can receive message, excessive relief area need not have been opened up again simultaneously；L2 cache reads the data of level cache Being simultaneously used for subsequent treatment, be equivalent to the continuity in space, two-stage completes the solution problem of capacity jointly；

Article one, a length of 416bit, RAM3 of ADS-B message can accommodate 20 messages, two totally 40 messages；Receive Article one, the time of ADS-B is 400us, and the time processing one is 700us, if serial process needs 1.1ms, with system approach only Needing 700us, when disposable arrival 40 when, have been processed by 400*40/700=23 bar, RAM3 has soared, Ke Yijie Receive subsequent packet, with FIS-B principle..

5, FIFO is characterised by, when not having data to be stored in FIFO, can export empty mark, and data storage can be defeated time full Going out full scale will, the data once stored are read, and data will no longer be present.Do not have reception packet storage module data to lose yet Mistake situation.When FIFO is full, receiving packet storage module and will not send data to FIFO, time non-full, receiving packet storage module can To send data to FIFO.

Accompanying drawing explanation

Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:

Fig. 1 is the schematic flow sheet of the inventive method embodiment one；

Fig. 2 is the schematic flow sheet of the inventive method embodiment two；

Fig. 3 (a), Fig. 3 (b) are the schematic flow sheet of embodiment illustrated in fig. 2 two step 202；

Fig. 4 (a), Fig. 4 (b), Fig. 4 (c) are the schematic flow sheet of embodiment illustrated in fig. 2 two step 205；

Fig. 5 is the structural representation of apparatus of the present invention embodiment one；

Fig. 6 is the structural representation of apparatus of the present invention embodiment two.

Detailed description of the invention

All features disclosed in this specification, or disclosed all methods or during step, except mutually exclusive Feature and/or step beyond, all can combine by any way.

Any feature disclosed in this specification (including any accessory claim, summary and accompanying drawing), unless chatted especially State, all can be by other equivalences or there is the alternative features of similar purpose replaced.I.e., unless specifically stated otherwise, each feature is only It it is an example in a series of equivalence or similar characteristics.

According to successfully decoded mark, it is thus achieved that the particular type of message and the plaintext of message.Successfully decoded according to FIS-B message Mark, it is thus achieved that FIS-B message, according to the ADS-B successfully decoded mark of LONG message, it is thus achieved that ADS-B LONG message, according to ADS- The successfully decoded mark of BBASIC message, it is thus achieved that ADS-B BASIC message.

1, (FIS-B message receives memory element and ADS-B message to receive two Large Copacity relief areas in packet storage module Receive memory element) ping-pong operation in turn.Two jumbo bufferings are each opened up according to FIS-B type and ADS-B type District, i.e. RAM1 and RAM2 are used for storing FIS-B message, RAM3 and RAM4 is used for storing ADS-B message.Come by the highest order of address Distinguishing the order that message arrives, the message first arrived exists in RAM1 and RAM3 that address highest order is 0, when RAM1 and RAM3 deposits After storage is full, the highest order of address will become 1, and the message now arrived exists in RAM2 and RAM4, when RAM2 and RAM4 stores After Man, the highest order of address will become 0, and circulation stores, the ping-pong operation in turn of two Large Copacity relief areas, it is to avoid opened up The most great relief area, is greatly saved the resource of system.

2, receiving packet storage module, synchronous head detection module, time wait module, L2 cache module, message decodes Being mutually linked and parallel processing mechanism of the multimodes such as module.By receiving packet storage module, the unknown message is divided into FIS-B Type and ADS-B type, be converted to concurrent working mode by follow-up a series of work in series mode；Synchronous head detection module, Parallel detection FIS-B type and the synchronous head of ADS-B type, when arranging, by output identification, the wait that the time waits module Between, the long FIS-B type waiting time is split up into FIS-B type waiting time and ADS-B type waiting time, shortens The waiting as long for of system；L2 cache module, by the message of effective known type and the message of the UNKNOWN TYPE of reception Distinguish, while release level cache, carry out the work decoding of subsequent packet, separately carry out independent to reception and process；Message Decoding module, carries out the message decoding fortune of ADS-B LONG and ADS-B BASIC type according to the ADS-B type of synchronization of message Calculate, shorten the time successively carrying out two kinds of message decodings.Collaboration process and the parallel processing mechanism of multimode substantially increase The operational efficiency of system.

3, FIS-B message synchronous head detector unit is a FIFO.ADS-B message synchronous head detector unit is second FIFO。

4, FIS-B message reception memory element includes the first buffer RAM1 and the second buffer RAM2.FIS-B message connects Harvesting storage unit includes the 3rd buffer RAM3 and the 4th buffer RAM4.FIS-B message L2 cache unit is by the 5th Buffer RAM5 realizes.ADS-B message L2 cache unit is to be realized by the 6th buffer RAM5.FIS-B extracts single in plain text Unit is to be realized by the 7th RAM.ADS-B LONG in plain text extraction unit, ADS-B BASIC extraction unit in plain text is all by the Eight RAM8 realize.First buffer RAM1, the second buffer RAM2, the 3rd buffer RAM3, the space of the 4th buffer RAM4 Address is more than the 5th buffer RAM5, the 6th buffer RAM6.7th buffer RAM7, the 8th buffer RAM8 memory space are big In the 5th buffer RAM5, the 6th buffer RAM6.

6, ADS-B BASIC message length is how many 30*8 bytes.

7, ADS-B LONG message length how many 48*8 bytes.

8, this device includes: receive packet storage module, for each opening up two according to FIS-B type and ADS-B type Individual jumbo relief area, i.e. RAM1 and RAM2 is used for storing FIS-B message, RAM3 and RAM4 is used for storing ADS-B message；With Step head detection module, for according to reading the data of storage in relief area RAM1 or RAM2 or RAM3 or RAM4, synchronizing to carry out The message synchronous head detection of FIS-B and ADS-B type, detects FIS-B message synchronous head, writes down the ground of FIS-B start of message (SOM) Location, is stored in FIFO1, ADS-B message synchronous head detected, writes down the address of ADS-B start of message (SOM), be stored in FIFO2;Time waits Module, calculates the waiting time for FIS-B or the ADS-B type according to message, it is ensured that a complete message receives and stores In relief area RAM1 or RAM2 or RAM3 or RAM4；L2 cache module, the time arrived according to complete message, in conjunction with The initial address of message in FIFO1, FIFO2, reads message from RAM1 or RAM2 or RAM3 or RAM4 and is stored in RAM5 and RAM6； Message decoding module, for according to from RAM5 and RAM6 read a complete message carry out FIS-B, ADS-B LONG and The message of ADS-B BASIC type carries out decoding operation, exports successfully decoded mark；Extraction module in plain text, for according to decoding Success Flag, it is thus achieved that the particular type of message and the plaintext of message.

Preferred embodiment one:

As it is shown in figure 1, comprise the following steps:

Step 101, according to the message amount that is likely to occur and type of message, open up sufficiently large relief area and receive and store Message；

Step 102, message according to storage synchronize to carry out the synchronous head of several type of message and its message is detected and stored rises Beginning address；

Step 103, basis detect the synchronous head mark of message, wait the time that a complete message arrives；

Step 104, the time arrived according to complete message, in conjunction with start of message (SOM) address, read message and be stored in and newly open up Relief area；

Step 105, basis read a complete message and carry out all types of message decoding from the relief area newly opened up；

Step 106, according to successfully decoded mark, it is judged that message particular type also extracts in plain text.

Preferred embodiment two: as in figure 2 it is shown, comprise the following steps:

Step 201, each open up two jumbo relief areas according to FIS-B type and ADS-B type, i.e. RAM1 and RAM2 is used for storing FIS-B message, RAM3 and RAM4 is used for storing ADS-B message.Report may be received continuously in view of system Literary composition, in the case of not knowing type of message and message amount, need to open up relief area is sufficiently large, to guarantee that data will not Lose, because FIS-B type and ADS-B type message synchronous head differ, and ADS-B LONG and the synchronization of ADS-B BASIC Identical, so existing in identical relief area by ADS-B LONG and ADS-B BASIC, i.e. RAM1, RAM2 is used for storing FIS-B message, RAM3, RAM4 are used for storing ADS-B message.

Step 202, according to reading the data of storage in RAM1/RAM2 and RAM3/RAM4 of relief area, synchronize to carry out FIS-B Its start of message (SOM) address is detected and stored with the message synchronous head of ADS-B type.FIS-B message and the synchronous head of ADS-B message Difference, in order to improve the real-time that system processes, detects the message in RAM1/RAM2 and RAM3/RAM4 simultaneously.

Specifically, Fig. 3 (a), Fig. 3 (b) they are the schematic flow sheet of embodiment illustrated in fig. 2 two step 202, as it is shown on figure 3, root According to reading the data of storage in RAM1/RAM2 and RAM3/RAM4 of relief area, the message synchronizing to carry out FIS-B and ADS-B type is same The process of step head detection is as follows:

Step 2021, the data read in RAM1 or RAM2 of relief area, add up according to address, be read out 36 in order Data carry out synchronous head detection, when address highest addresses is 0, read the data in RAM1, when address highest addresses is 1, Read the data in RAM2；

Step 2022, FIS-B message is carried out synchronous head detection, by 36 bit data that read and standard FIS-B message with Step head is compared, identical, then be judged to find FIS-B message synchronous head, different, then be judged to not find synchronous head, simultaneously Return step 2021, read data and carry out the detection of next round synchronous head；

Step 2023, result of determination according to step 2022, export FIS-B message synchronous head mark, and by FIS-B message Initial address is stored in FIFO1；

Step 2024, the data read in RAM3 or RAM4 of relief area, add up according to address, be read out 36 in order Data carry out synchronous head detection, when address highest addresses is 0, read the data in RAM3, when address highest addresses is 1, Read the data in RAM4；

Step 2025, ADS-B message is carried out synchronous head detection, by 36 bit data that read and standard ADS-B message with Step head is compared, identical, then be judged to find ADS-B message synchronous head, different, then be judged to not find synchronous head, simultaneously Return step 2024, read data and carry out the detection of next round synchronous head；

Step 2026, result of determination according to step 2025, output ADS-B message synchronous head mark by ADS-B message Initial address is stored in FIFO2.

Step 203, message synchronous head mark detected, calculate the waiting time according to FIS-B or the ADS-B type of message, Guarantee that a complete message receives and stores in relief area RAM1 or RAM2 or RAM3 or RAM4.

Step 204, the time arrived according to complete message, in conjunction with the initial address of message in FIFO1, FIFO2, from RAM1 Or reading message is stored in RAM5 and RAM6 in RAM2 and RAM3 or RAM4.

Step 205, according to from RAM5 and RAM6 read a complete message carry out FIS-B, ADS-B LONG and The message of ADS-BBASIC type decodes.

Specifically, Fig. 4 (a), Fig. 4 (b), Fig. 4 (c) are the schematic flow sheet of embodiment illustrated in fig. 2 two step 205, such as Fig. 4 Shown in, a complete message according to reading from RAM5 and RAM6 carries out FIS-B, ADS-B LONG and ADS-BBASIC class The process that the message of type carries out decoding is as follows:

Step 2051, the complete FIS-B message read from RAM5, i.e. according to the message number of storage in RAM5 Amount, by indicating the address of message bar number to add up in RAM5, reads FIS-B message；

Step 2052, in RAM5 read FIS-B message decode；

Step 2053, according to decoding result, output identification, if successfully decoded, export the successfully decoded mark of FIS-B message Will, if decoding failure, returns step 2051, reads next message and decode；

Step 2054, the complete ADS-B LONG message read from RAM6, i.e. according to the report of storage in RAM6 Literary composition quantity, by indicating the address of message bar number to add up in RAM6, reads ADS-B LONG message；

Step 2055, in RAM6 read ADS-B LONG message decode；

Step 2056, according to decoding result, output identification, if successfully decoded, output ADS-B LONG message be decoded into Merit mark, if decoding failure, returns step 2054, reads next message and decode；

Step 2057, the complete ADS-B BASIC message read from RAM6, i.e. according to the report of storage in RAM6 Literary composition quantity, by indicating the address of message bar number to add up in RAM6, reads ADS-B BASIC message；

Step 2055, in RAM6 read ADS-B BASIC message decode；

Step 2056, according to decoding result, output identification, if successfully decoded, output ADS-B BASIC message be decoded into Merit mark, if decoding failure, returns step 2057, reads next message and decode.

Step 206, according to successfully decoded mark, it is thus achieved that the particular type of message and the plaintext of message.According to FIS-B message Successfully decoded mark, it is thus achieved that FIS-B message, according to the ADS-B successfully decoded mark of LONG message, it is thus achieved that ADS-B LONG message, According to the ADS-B successfully decoded mark of BASIC message, it is thus achieved that ADS-B BASIC message.

Fig. 5 is the structural representation of the present invention a kind of Large Copacity polymorphic type message real-time processing method embodiment one, and this is real A kind of Large Copacity polymorphic type message real-time processing method executing example can be used for realizing enforcement shown in above-mentioned Fig. 1 or Fig. 2 of the present invention A kind of Large Copacity polymorphic type message real-time processing method flow process.As it is shown in figure 5, include: receive packet storage module 51, synchronous head Detection module 52, time wait module 53, L2 cache module 54, message decoding module 55 and plaintext extraction module 56.

Wherein, packet storage module 51 is received for each opening up two Large Copacity according to FIS-B type and ADS-B type Relief area, i.e. RAM1 and RAM2 be used for store FIS-B message, RAM3 and RAM4 be used for store ADS-B message；Synchronous head detects Module 52 system for according to reading the data of storage in relief area RAM1 or RAM2 or RAM3 or RAM4, synchronize to carry out FIS-B and The message synchronous head detection of ADS-B type, detects FIS-B message synchronous head, writes down the address of FIS-B start of message (SOM), be stored in FIFO1, detects ADS-B message synchronous head, writes down the address of ADS-B start of message (SOM), be stored in FIFO2；Time waits module 53 The waiting time is calculated, it is ensured that a complete message receives and store buffering for FIS-B or the ADS-B type according to message In district RAM1 or RAM2 or RAM3 or RAM4；The time that L2 cache module 54 arrives according to complete message, in conjunction with FIFO1, The initial address of message in FIFO2, reads message from RAM1 or RAM2 or RAM3 or RAM4 and is stored in RAM5 and RAM6；Message is translated Code module 55 is for carrying out FIS-B or ADS-B LONG or ADS-according to the complete message read from RAM5 and RAM6 The message of B SHORT type carries out decoding operation, exports successfully decoded mark；Extraction module 56 is for according to successfully decoded in plain text Mark, it is thus achieved that the particular type of message and the plaintext of message.

The invention provides a kind of Large Copacity polymorphic type message real-time processing method, open up what Large Copacity relief area, adopt By the method for all types of message parallel processings, in the case of guaranteeing that message is not lost, to greatest extent message is located in real time Reason, substantially increases the work efficiency of system.

Fig. 6 is the structural representation of the embodiment of the method two that the present invention a kind of Large Copacity polymorphic type message processes in real time, should The method that a kind of Large Copacity polymorphic type message of embodiment processes in real time can be used for realizing reality shown in above-mentioned Fig. 1 or Fig. 2 of the present invention Execute the method flow that a kind of Large Copacity polymorphic type message of example processes in real time.As shown in Figure 6, including: receive packet storage module 51, synchronous head detection module 52, time wait module 53, L2 cache module 54, message decoding module 55 and extract mould in plain text Block 56.

On the basis of above-mentioned embodiment illustrated in fig. 5, in the present embodiment, receive packet storage module 51 and farther include: FIS-B message receives memory element 511 and ADS-B message and receives memory element 512.

Specifically, FIS-B message receives memory element 511.Setting the data depth of RAM1, RAM2 as 8192, data are defeated Entering to export width and be 1bit, I/O Address width is 15, distinguishes, by the highest order of address, the order that message arrives, The message first arrived exists in the RAM1 that address highest order is 0, and after RAM1 storage is full, the highest order of address will become 1, this Time the FIS-B message that arrives exist in RAM2, after RAM2 storage is full, the highest order of address will become 0, and circulation stores；

ADS-B message receives memory element 512.Set the data depth of RAM3, RAM4 as 8192, data input and output width Degree is 1bit, and I/O Address width is 15, distinguishes, by the highest order of address, the order that message arrives, first arrives Message exists in the RAM3 that address highest order is 0, and after RAM3 storage is full, the highest order of address will become 1, now arrive ADS-B message exists in RAM4, and after RAM4 storage is full, the highest order of address will become 0, circulation storage；

The feature of RAM is that data will remain stored in the address area of correspondence, writes until again address being carried out data Operation；

It should be noted that in now RAM1, RAM2, RAM3, RAM4, the message of storage is identical, is equivalent to identical report Literary composition each stores once as FIS-B type and ADS-B type.

On the basis of above-mentioned embodiment illustrated in fig. 5, in the present embodiment, synchronous head detection module 52 farther includes: FIS-B message synchronous head detector unit 521 and ADS-B message synchronous head detector unit 522.

Specifically, FIS-B message synchronous head detector unit 521.Read the data in RAM1 or RAM2 of relief area, step-by-step with 36 standard FIS-B message synchronous heads are compared detection, FIS-B message synchronous head once detected, write down and now read The address of RAM1 or RAM2, it is FIS-B message that this address mark subsequent packet, and this address adds 1 and is follow-up FIS-B The first address of message, it is 16 that this address is stored in FIFO1, FIFO1 data depth, and data I/O width is 15bit, I/O Address width is 4, can store the initial address of 16 messages；

ADS-B message synchronous head detector unit 522.Read the data in RAM3 or RAM4 of relief area, step-by-step and 36 marks Quasi-ADS-B message synchronous head is compared detection, ADS-B message synchronous head once detected, writes down the RAM3 now read Or the address of RAM4, it is ADS-B message that this address mark subsequent packet, and this address adds 1 and is follow-up ADS-B message First address, it is 16 that this address is stored in FIFO2, FIFO2 data depth, and data I/O width is 15bit, inputs defeated Going out address width is 4, can store the initial address of 16 messages；

FIFO is characterised by, when not having data to be stored in FIFO, can export empty mark, and data storage can export time full Full scale will, the data once stored are read, and data will no longer be present.

On the basis of above-mentioned embodiment illustrated in fig. 5, in the present embodiment, the time waits that module 53 farther includes: FIS-B Message waits that unit 531 and ADS-B message waits unit 532.

Specifically, FIS-B message waits unit 531.Once obtain FIS-B message synchronous head mark, calculate FIS-B message Waiting time, FIS-B message length is 552 bytes, and each byte packet contains 8 bits, and the time of each bit is 960ns, the i.e. FIS-B message waiting time is about 552*8*960=4239360ns, sets the waiting time as 4300000ns；

ADS-B message waits unit 532.Once obtain ADS-B message synchronous head mark, calculate the wait of ADS-B message Time, a length of 48 bytes of ADS-B LONG message, a length of 30 bytes of ADS-B BASIC message, cannot be bright The when of the particular type of true ADS-B message, carry out evaluation time according to ADS-B LONG message, i.e. ADS-B message length is 48 Byte, each byte packet contains 8 bits, and the time of each bit is 960ns, i.e. the ADS-B message waiting time is about 48* 8*960=36840ns, sets the waiting time as 40000ns.

On the basis of above-mentioned embodiment illustrated in fig. 5, in the present embodiment, L2 cache module 54 farther includes: FIS-B Message L2 cache unit 541 and ADS-B message L2 cache unit 542.

Specifically, FIS-B message L2 cache unit 541.The FIS-B message waiting time set arrives, and checks FIFO1 Empty mark, if sky is masked as 1, represents and do not have message to find, if sky is masked as 0, represent FIFO1 stores have FIS-B The first address of message, also indicates in RAM1 or RAM2 have complete FIS-B message simultaneously, in conjunction with reading message from FIFO1 First address, the FIS-B message reading 552 bytes from RAM1 or RAM2 is stored in the I/O Address width of RAM5, RAM5 Being 11, data input width is 1bit, and data output width is 8bit, is used to refer to message by high 2 of 11 bit address Quantity, low 9 contents being used to refer to message.Send marking signal after having stored a complete FIS-B message, indicate readable Take FIS-B message to decode;

ADS-B message L2 cache unit 542.The ADS-B message waiting time set arrives, and checks the empty mark of FIFO2 Will, if sky is masked as 1, represents and does not has message to find, if sky is masked as 0, represents that in FIFO2, storage has ADS-B message First address, also indicates in RAM3 or RAM4 have complete ADS-B message simultaneously, in conjunction with the first ground reading message from FIFO2 Location, the ADS-B message reading 48 bytes from RAM3 or RAM4 is stored in RAM6.The I/O Address width of RAM6 is 11, Data input width is 1bit, and data output width is 8bit, by high 5 quantity being used to refer to message of 11 bit address, low by 6 Position is used to refer to the content of message.Sending marking signal after having stored a complete ADS-B message, instruction can read ADS-B Message decodes.

On the basis of above-mentioned embodiment illustrated in fig. 5, in the present embodiment, message decoding module 55 farther includes: FIS-B Message decoding unit 551, ADS-B LONG message decoding unit 552 and ADS-B BASIC message decoding unit 553.

Specifically, FIS-B message decoding unit 551.The FIS-B message flag letter that L2 cache module sends detected Number, from RAM5 read FIS-B message decode, successfully decoded after, export the successfully decoded mark of FIS-B message；

ADS-B LONG message decoding unit 552.The ADS-B message flag signal that L2 cache module sends detected, Because now cannot distinguish between ADS-B message is ADS-B LONG message or ADS-B BASIC message, needs to read message and carry out The decoding of ADS-BLONG message and ADS-B BASIC message decode, and read message by ADS-B LONG message length 48 byte and carry out ADS-BLONG message decode, successfully decoded after, export the ADS-B successfully decoded mark of LONG message；

ADS-B BASIC message decoding unit 553.Read message by ADS-B BASIC message length 30 byte to carry out ADS-BBASIC message decode, successfully decoded after, export the ADS-B successfully decoded mark of BASIC message.

On the basis of above-mentioned embodiment illustrated in fig. 5, in the present embodiment, message decoding module 56 farther includes: FIS-B Extraction unit 561, ADS-B LONG extraction unit 562 and ADS-B BASIC in plain text extraction unit 563 in plain text in plain text.

Specifically, FIS-B extraction unit 561 in plain text.The successfully decoded mark of FIS-B message detected, read FIS-B bright Literary composition, adds the FIS-B message synchronous head mark of internal agreement, stores in RAM7, the I/O Address width of RAM7 is 11 Position, data input width is 1bit, and data output width is 8bit, by high 2 quantity being used to refer to message of 11 bit address, Low 9 contents being used to refer to message；

ADS-B LONG extraction unit 562 in plain text.The ADS-B successfully decoded mark of LONG message detected, read ADS-B LONG in plain text, adds the ADS-B message synchronous head mark of internal agreement, stores in RAM8, the I/O Address width of RAM8 Degree is 11, and data input width is 1bit, and data output width is 8bit, is used to refer to message by high 5 of 11 bit address Quantity, low 6 contents being used to refer to message；

ADS-B BASIC extraction unit 563 in plain text.The ADS-B successfully decoded mark of BASIC message detected, read ADS- BBASIC in plain text, adds the ADS-B message synchronous head mark of internal agreement, stores in RAM8, the I/O Address of RAM8 Width is 11, and data input width is 1bit, and data output width is 8bit, is used to refer to report by high 5 of 11 bit address The quantity of literary composition, low 6 contents being used to refer to message.

The invention is not limited in aforesaid detailed description of the invention.The present invention expands to any disclose in this manual New feature or any new combination, and the arbitrary new method that discloses or the step of process or any new combination.

Claims

1. a polymorphic type message real-time processing method, it is characterised in that including:

Step 1: receive packet storage module and FIS-B message reception memory element and ADS-B packet storage unit are set, described FIS-B message receives memory element, ADS-B packet storage unit receives simultaneously and store the message from outside input；

Step 2: synchronous head detection module reads to receive in FIS-B message reception memory element and ADS-B packet storage unit and deposits The data message of storage, carries out FIS-B type of synchronization head and the detection of ADS-B type of synchronization head, if FIS-B message receives memory element There is FIS-B categorical data message, then FIS-B categorical data start of message (SOM) address be stored in FIS-B message synchronous head detector unit, And export FIS-B type of synchronization leader will；If ADS-B packet storage unit has FIS-B categorical data message, then by ADS-simultaneously B categorical data start of message (SOM) address is stored in ADS-B message synchronous head detector unit, and exports ADS-B type of synchronization leader will；

Step 3: the time waits that module detects FIS-B synchronous head mark and ADS-B type of synchronization leader will, according to corresponding FIS- B type message waiting time and ADS-B type message waiting time, it is ensured that complete FIS-B type or ADS-B categorical data report Literary composition storage receives memory element or ADS-B packet storage unit to corresponding FIS-B message；

Step 4: L2 cache module is respectively provided with FIS-B message L2 cache unit, ADS-B message L2 cache unit, FIS-B message L2 cache unit is for detecting the empty flag bit of FIS-B message synchronous head detector unit, if empty flag bit is 0, Then represent that FIS-B message synchronous head detector unit storage has FIS-B categorical data start of message (SOM) address；FIS-B message two grades delays Memory cell, according to FIS-B categorical data start of message (SOM) address, FIS-B type message waiting time, receives packet storage from FIS-B Module reads FIS-B message, and is deposited in FIS-B message level 2 buffering unit, has stored a complete FIS-B message Rear output FIS-B message flag signal；ADS-B message L2 cache unit is used for detecting ADS-B message synchronous head detector unit Empty flag bit, if empty flag bit is 0, then it represents that ADS-B message synchronous head detector unit storage has ADS-B categorical data message Initial address；ADS-B message L2 cache unit waits according to ADS-B categorical data start of message (SOM) address, ADS-B type message Time, receive packet storage module from ADS-B and read ADS-B message, and be deposited in ADS-B message level 2 buffering unit, ADS-B message flag signal is exported after having stored a complete ADS-B message；

Step 5: message decoding module reads FIS-B message and the ADS-B message of L2 cache module output, and carries out correspondence The message decoding of type, exports successfully decoded mark to extraction module in plain text；

A kind of polymorphic type message real-time processing method the most according to claim 1, it is characterised in that FIS-in described step 1 B message reception memory element, ADS-B message reception storage unit stores data are identical, and described FIS-B message receives memory element Including the first buffer RAM1 and the second buffer RAM2, ADS-B message receive memory element include the 3rd buffer RAM3 and 4th buffer RAM4, described first buffer RAM1 and the second buffer RAM2 is ping-pong operation, described 3rd buffer RAM3 and the 4th buffer RAM4 is ping-pong operation, described first buffer RAM1, the second buffer RAM2, the 3rd buffer RAM3, the 4th buffer RAM4 data depth are 2ⁿ, then FIS-B message receives memory element I/O Address width is (n+ 1) position, FIS-B message receives memory element address highest order and distinguishes the order that message reaches, and the message first arrived exists ground Location highest order is in the first buffer RAM1 of 0, and after the first buffer RAM1 is filled with, FIS-B message receives memory element ground Location highest order will become 1, and the message now arrived exists in the second buffer RAM2, after the first buffer RAM2 is filled with, FIS-B message receives memory unit address highest order and becomes 0, and the message consequently reached exists in the first buffer RAM1, circulation Storage；ADS-B message receives memory element address highest order and distinguishes the order that message reaches, and the message first arrived exists ground Location highest order is in the 3rd buffer RAM3 of 0, and after the 3rd buffer RAM3 is filled with, ADS-B message receives memory element ground Location highest order will become 1, and the message now arrived exists in the 4th buffer RAM4, after the 4th buffer RAM4 is filled with, ADS-B message receives memory unit address highest order will become 0, and the message consequently reached exists in the 3rd buffer RAM3, follows Ring stores；The described FIS-B type waiting time is M1 byte of FIS-B message length, and each bit transmission time is K1, then The FIS-B type waiting time is M1*8*K1；The ADS-B type waiting time is M2 byte of FIS-B message length, each bit The position transmission time is K2, then the ADS-B type waiting time is M2*8*K2, wherein 550 < M1 < 600;40<M2<50.

A kind of polymorphic type message real-time processing method the most according to claim 2, it is characterised in that synchronize in described step 2 Head detection module reads and receives the message of relief area storage in packet storage module, carries out FIS-B type message and ADS-B type Message synchronous head detects, and concrete steps include:

Step 21: synchronous head detection module read FIS-B message receive in memory element the first buffer RAM1 data message with Data message in second buffer RAM2, reads N bit data in FIS-B message reception memory element 1 in order and synchronizes Head detection, when FIS-B message reception memory unit address highest addresses is 0, reads the data in the first buffer RAM1, When FIS-B message reception memory unit address highest addresses is 1, read the data in the second buffer RAM2；Meanwhile, synchronize Head detection module reads the datagram that ADS-B message receives in memory element in the 3rd buffer RAM3 or the 4th buffer RAM4 Literary composition, is read out N bit data in order and carries out synchronous head detection, and it is 0 that ADS-B message receives memory unit address highest addresses Time, reading the data in the 3rd buffer RAM3, ADS-B message receives memory unit address highest addresses when being 1, reads the Data in four buffer RAM4；

Step 22: when synchronous head detection module carries out synchronous head detection to FIS-B message, reads FIS-B message and receives storage list When the top N data of FIS-B message are identical with standard FIS-B message synchronous head in unit, then it is judged to that FIS-B message occurs, The FIS-B message that FIS-B message synchronous head detector unit record now FIS-B message is corresponding receives access unit address, and Output FIS-B message synchronous head mark；Otherwise, for FIS-B message does not occurs, return step 21 simultaneously；

Step 23: when synchronous head detection module carries out synchronous head detection to ADS-B message, reads ADS-B message and receives storage list When the top N data of ADS-B message are identical with standard ADS-B message synchronous head in unit, then it is judged to that ADS-B message occurs, The ADS-B message that ADS-B message synchronous head detector unit record now ADS-B message is corresponding receives access unit address, and Output ADS-B message synchronous head mark；Otherwise, for ADS-B message does not occurs, return step simultaneously.

A kind of polymorphic type message real-time processing method the most according to claim 2, it is characterised in that basis in described step 5 Message decoding module reads the message of L2 cache module output and carries out the message decoding of corresponding types, exports successfully decoded mark Knowing to extraction module in plain text, detailed process is:

Step 51: if what the FIS-B message decoding unit of message decoding module detected that L2 cache module exports is FIS-B report During literary composition marking signal, the complete FIS-B message read from FIS-B message L2 cache unit, i.e. report according to FIS-B The message amount of literary composition L2 cache unit storage, enters by indicating the address of message bar number in FIS-B message L2 cache unit 41 Row is cumulative, reads FIS-B message；

Step 52；The FIS-B message read from FIS-B message L2 cache unit decodes；If successfully decoded, FIS- The B message decoding unit output successfully decoded mark of FIS-B message, if decoding failure, returns step 51, reads next message Decode；

If the ADS-B LONG message decoding unit of step 53 message decoding module detects, L2 cache module 4 output During ADS-B message flag signal, the complete ADS-B message read from ADS-B message L2 cache unit, i.e. basis ADS-B LONG message length reads the ADS-B message in ADS-B message L2 cache unit 42, is decoded, if being decoded into Merit, then the ADS-B LONG message decoding unit output ADS-B successfully decoded mark of LONG message；

Step 54: if the ADS-B BASIC message decoding unit of message decoding module detects, the output of L2 cache module During ADS-B message flag signal, the complete ADS-B message read from ADS-B message L2 cache unit, i.e. basis ADS-B BASIC message length reads the ADS-B message in ADS-B message L2 cache unit, is decoded, if being decoded into Merit, then the ADS-B BASIC message decoding unit output ADS-B successfully decoded mark of BASIC message.

A kind of polymorphic type message real-time processing method the most according to claim 2, it is characterised in that described step 6 specifically walks Suddenly include:

FIS-B in extraction module extraction unit in plain text in plain text, according to the successfully decoded mark of FIS-B message, it is thus achieved that FIS-B message In plain text, FIS-B message is stored in FIS-B extraction unit in plain text plus FIS-B synchronous head mark in plain text；

ADS-B in extraction module extraction unit in plain text in plain text, according to the ADS-B successfully decoded mark of LONG message, it is thus achieved that FIS- In plain text, ADS-B message is stored in ADS-B extraction unit in plain text plus ADS-B LONG synchronous head mark to B LONG message in plain text；

ADS-B in extraction module extraction unit in plain text in plain text, according to the ADS-B successfully decoded mark of BASIC message, it is thus achieved that In plain text, ADS-B message is stored in ADS-B plus ADS-B BASIC synchronous head mark and extracts single in plain text ADS-B BASIC message in plain text Unit.

6. a polymorphic type message real-time processing device, it is characterised in that including:

Receive packet storage module, being used for, FIS-B message is set and receives memory element and ADS-B packet storage unit, described FIS-B message receives memory element, ADS-B packet storage unit receives the most simultaneously and store the message from outside input；

Synchronous head detection module, reads reception FIS-B message for correspondence respectively and receives memory element and ADS-B packet storage list The data message of storage in unit, correspondence carries out FIS-B type of synchronization head and the detection of ADS-B type of synchronization head respectively, if FIS-B report Literary composition receives memory element FIS-B categorical data message, then FIS-B categorical data start of message (SOM) address is stored in FIS-B message Synchronous head detector unit, and export FIS-B type of synchronization leader will；If ADS-B packet storage unit has ADS-B number of types simultaneously According to message, then ADS-B categorical data start of message (SOM) address is stored in ADS-B message synchronous head detector unit, and exports ADS-B class Type synchronous head mark;

Time waits module, and for according to FIS-B or the ADS-B type message waiting time, correspondence detects that synchronous head is examined respectively When surveying FIS-B synchronous head mark and the ADS-B type of synchronization leader will of module output, receive FIS-B type message and ADS-B class Type message also stores corresponding FIS-B message reception memory element 11, ADS-B packet storage unit；

L2 cache module, is respectively provided with FIS-B message L2 cache unit, ADS-B message L2 cache unit, and FIS-B reports Literary composition L2 cache unit is for detecting the empty flag bit of FIS-B message synchronous head detector unit, if empty flag bit is 0, then it represents that FIS-B message synchronous head detector unit storage has FIS-B categorical data start of message (SOM) address；FIS-B message L2 cache unit According to FIS-B categorical data start of message (SOM) address, FIS-B type message waiting time, receive packet storage module from FIS-B and read Take FIS-B message, and be deposited in FIS-B message level 2 buffering unit, export after having stored a complete FIS-B message FIS-B message flag signal；ADS-B message L2 cache unit is for detecting the empty mark of ADS-B message synchronous head detector unit Will position, if empty flag bit is 0, then it represents that ADS-B message synchronous head detector unit storage has ADS-B categorical data start of message (SOM) ground Location；ADS-B message L2 cache unit according to ADS-B categorical data start of message (SOM) address, ADS-B type message waiting time, Receive packet storage module from ADS-B and read ADS-B message, and be deposited in ADS-B message level 2 buffering unit, stored Article one, after complete ADS-B message, export ADS-B message flag signal；

Message decoding module, message decoding module reads FIS-B message and the ADS-B message of L2 cache module output, and Carry out the message decoding of corresponding types, export successfully decoded mark to extraction module in plain text；

A kind of polymorphic type message real-time processing device the most according to claim 6, it is characterised in that described reception message is deposited Storage module includes that FIS-B message receives memory element and ADS-B message receives memory element, and FIS-B message receives memory element Receiving storage unit stores data with ADS-B message identical, described FIS-B message receives memory element and includes the first buffer RAM1 and the second buffer RAM2, FIS-B message receives memory element and includes the 3rd buffer RAM3 and the 4th buffer RAM4, Described first buffer RAM1 and the second buffer RAM2 is ping-pong operation, described 3rd buffer RAM3 and the 4th buffer RAM4 is ping-pong operation, described first buffer RAM1, the second buffer RAM2, the 3rd buffer RAM3, the 4th buffer RAM4 data depth is 2ⁿ, then FIS-B message receives memory element I/O Address width is (n+1) position, and FIS-B message connects Harvesting storage unit address highest order distinguishes the order that message reaches, and the message first arrived exists that address highest order is 0 In one buffer RAM1, after the first buffer RAM1 is filled with, FIS-B message receives memory unit address highest order will become 1, The message now arrived exists in the second buffer RAM2, and after the first buffer RAM2 is filled with, it is single that FIS-B message receives storage Unit's address highest order becomes 0, and the message consequently reached exists in the first buffer RAM1, circulation storage；ADS-B message receives and deposits Storage unit 12 address highest order distinguishes the order that message reaches, and the message first arrived exists the 3rd that address highest order is 0 In buffer RAM3, after the 3rd buffer RAM3 is filled with, ADS-B message receives memory unit address highest order will become 1, this Time the message that arrives exist in the 4th buffer RAM4, after the 4th buffer RAM4 is filled with, ADS-B message receives memory element Address highest order will become 0, and the message consequently reached exists in the 3rd buffer RAM3, circulation storage；Described FIS-B or ADS- The B type waiting time calculates process: the FIS-B type waiting time is M1 byte of FIS-B message length, and each bit passes The defeated time is K1, then the FIS-B type waiting time is M1*8*K1；The ADS-B type waiting time is FIS-B message length M2 Byte, each bit transmission time is K2, then the ADS-B type waiting time is M2*8*K2.

A kind of polymorphic type message real-time processing device the most according to claim 7, it is characterised in that described synchronous head detects Module reads and receives the message of relief area storage in packet storage module, carries out FIS-B type message and ADS-B type message is same Step head detection, concrete steps include:

Step 21: synchronous head detection module read FIS-B message receive in memory element the first buffer RAM1 data message with Data message in second buffer RAM2, reads N bit data in FIS-B message reception memory element in order and carries out synchronous head Detection, when FIS-B message reception memory unit address highest addresses is 0, reads the data in the first buffer RAM1, FIS- When B message reception memory unit address highest addresses is 1, read the data in the second buffer RAM2；Meanwhile, synchronous head inspection Survey module and read the data message that ADS-B message receives in memory element in the 3rd buffer RAM3 or the 4th buffer RAM4, It is read out N bit data in order and carries out synchronous head detection, when ADS-B message reception memory unit address highest addresses is 0, Read the data in the 3rd buffer RAM3, when ADS-B message reception memory unit address highest addresses is 1, read the 4th Data in buffer RAM4；

Step 23: when synchronous head detection module carries out synchronous head detection to ADS-B message, reads ADS-B message and receives storage list When the top N data of ADS-B message are identical with standard ADS-B message synchronous head in unit, then it is judged to that ADS-B message occurs, The ADS-B message that ADS-B message synchronous head detector unit record now ADS-B message is corresponding receives access unit address, and Output ADS-B message synchronous head mark；Otherwise, for ADS-B message does not occurs, return step 21 simultaneously.

A kind of polymorphic type message real-time processing device the most according to claim 7, it is characterised in that described message decoding mould Block reads the message of L2 cache module 4 output and carries out the message decoding of corresponding types, exports successfully decoded mark in plain text Extraction module, detailed process is:

Step 51: if what the FIS-B message decoding unit of message decoding module detected that L2 cache module exports is FIS-B report During literary composition marking signal, the complete FIS-B message read from FIS-B message L2 cache unit, i.e. report according to FIS-B The message amount of literary composition L2 cache unit storage, is carried out by indicating the address of message bar number in FIS-B message L2 cache unit Cumulative, read FIS-B message；

If the ADS-B LONG message decoding unit of step 53 message decoding module detects, the output of L2 cache module During ADS-B message flag signal, the complete ADS-B message read from ADS-B message L2 cache unit, i.e. basis ADS-B LONG message length reads the ADS-B message in ADS-B message L2 cache unit, is decoded, if successfully decoded, The then ADS-B LONG message decoding unit output ADS-B successfully decoded mark of LONG message；

A kind of polymorphic type message real-time processing device the most according to claim 7, it is characterised in that described plaintext extracts mould Block specific works process includes；

ADS-B in extraction module extraction unit in plain text in plain text, for according to the ADS-B successfully decoded mark of LONG message, it is thus achieved that In plain text, ADS-B message is stored in ADS-B plus ADS-B LONG synchronous head mark and extracts single in plain text ADS-B LONG message in plain text Unit；

ADS-B in extraction module extraction unit in plain text, for according to the ADS-B successfully decoded mark of BASIC message, obtains in plain text Obtaining ADS-B BASIC message in plain text, ADS-B message is stored in ADS-B extraction in plain text plus ADS-B BASIC synchronous head mark in plain text Unit.