CN103762608A - Non-disturbance multi-level compensating circuit for AC electricity utilization system power factor - Google Patents
Non-disturbance multi-level compensating circuit for AC electricity utilization system power factor Download PDFInfo
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Abstract
The invention relates to a non-disturbance multi-level compensating circuit for an AC electricity utilization system power factor. The non-disturbance multi-level compensating circuit comprises a stabilized voltage supply circuit, a phase voltage and current signal conditioning circuit and a compensation control circuit and specifically comprises a voltage transformer VS1, a current transformer CS1, a voltage follower IC1, a current follower IC2, a processor IC3, a drive chip IC4, a stabilized voltage supply module U0, a large solid-state relay U1, a small solid-state relay U2, a middle solid-state relay U3, a lower solid-state relay U4, a large compensation capacitor C1, a small compensation capacitor C2, a reference tube D1, an upper stabilivolt D2, a lower stabilivolt D3, a load resistor R1 and the like. According to the non-disturbance multi-level compensating circuit for the AC electricity utilization system power factor, non-disturbance combination switching on a grid is performed on the two compensation capacitors based on the four zero passing type AC solid-state relays so as to achieve four-level compensation control on the power factor, the requirement for power factor compensation control of most of AC loads can be met, and the method is high in cost performance, good in universality, safe and reliable.
Description
Technical field
The invention belongs to industrial measurement and control field, relate to a kind of circuit, be particularly related to a kind of undisturbed Multilevel compensating circuit that exchanges using electricity system power factor, be applicable to AC inductive load automatically to carry out the application scenario of power factor compensation control, to improve power supply, to use electrical efficiency.
Background technology
Interchange is mostly inductive load by electric loading, and current phase lags behind voltage-phase, and power, the power factor of using electricity system is the important indicator in electric energy running quality.At present, for the conventional scheme that improves power factor, be: the one, when to monitor power factor to a certain extent low, be often in parallel upper one for compensating the compensation condenser of inductive load power factor; The 2nd, the compensation condenser of the thuristor throw-in and throw-off of employing based on phase shifting control, that is: every each compensation condenser adopts two inverse parallel inverse-impedance type thyristors or a bidirectional thyristor to carry out the switching control of phased approach.The weak point of existing scheme is: the one, and single capacitor can only be realized comparatively ideal compensation effect to a bit; The 2nd, phase shift switching type will produce additional harmonic pollution to electrical network.
Summary of the invention
The object of the invention is the deficiency existing for prior art, propose a kind of undisturbed Multilevel compensating circuit that exchanges using electricity system power factor.The power factor that integrates this circuit detects and has a grade composite type to cross zero-compensation control program, employing is carried out the undisturbed combination of electrical network based on four zero type ac solid relays to two compensation condensers and is switched, and to realize, the level Four compensation of power factor is controlled.
The present invention includes voltage-stabilized power supply circuit, phase voltage current signal conditioning circuit, compensation control circuit.
Voltage-stabilized power supply circuit comprises power module of voltage regulation U0, power capacitor C0, voltage regulation resistance R2, prover pipe D1, the phase feeder ear L end of power module of voltage regulation U0 is connected with electrical network phase voltage end L end, the zero line side N end of power module of voltage regulation U0 is connected with electrical network zero line side N end, out-put supply end+V end and the stabilized voltage power supply anode VCC end of power module of voltage regulation U0, one end of power capacitor C0, one end of voltage regulation resistance R2 connects, the other end ground connection of power capacitor C0, the negative electrode of the other end of voltage regulation resistance R2 and prover pipe D1, reference voltage terminal VZ holds connection, the plus earth of prover pipe D1.
Phase voltage current signal conditioning circuit comprises voltage transformer VS1, current transformer CS1, using electricity system PU1, voltage follower IC1, current follower IC2, load resistance R1, bias resistance R3, voltage filter resistance R 4, voltage filter capacitor C 3, upper voltage-stabiliser tube D2, biasing resistance R5, current filtering resistance R 6, current filtering capacitor C 4, lower voltage-stabiliser tube D3, the phase test side L end of voltage transformer VS1 is connected with electrical network phase voltage end L end, the zero line side N end of voltage transformer VS1 is connected with electrical network zero line side N end, the positive output end OUT1 end of voltage transformer VS1 is connected with one end of voltage filter resistance R 4, the negative output terminal OUT2 end ground connection of voltage transformer VS1, positive input terminal+IN end of the other end of voltage filter resistance R 4 and voltage follower IC1, one end of bias resistance R3, the negative electrode of upper voltage-stabiliser tube D2, one end of voltage filter capacitor C 3 connects, the other end of bias resistance R3 is connected with voltage reference end VZ end, the other end ground connection of voltage filter capacitor C 3, the plus earth of upper voltage-stabiliser tube D2, negative input end-IN end of voltage follower IC1 and the output OUT end of voltage follower IC1, the upper A/D translation interface end ADC1 end of processor IC3 connects, positive power source terminal+V end of voltage follower IC1 is connected with stabilized voltage power supply anode VCC end, negative power end-V of voltage follower IC1 holds ground connection, the phase feeder ear L end of using electricity system PU1 connects through the detection Kong Houyu electrical network phase voltage end L end of current transformer CS1 through line, the zero line side N end of using electricity system PU1 is connected with electrical network zero line side N end, the negative output terminal AC2 ground connection of current transformer CS1, the positive output end AC1 of current transformer CS1 and one end of load resistance R1, one end of current filtering resistance R 6 connects, the other end ground connection of load resistance R1, positive input terminal+IN end of the other end of current filtering resistance R 6 and current follower IC2, one end of biasing resistance R5, the negative electrode of lower voltage-stabiliser tube D3, one end of current filtering capacitor C 4 connects, the other end of biasing resistance R5 is connected with voltage reference end VZ end, the other end ground connection of current filtering capacitor C 4, the plus earth of lower voltage-stabiliser tube D3, negative input end-IN end of current follower IC2 and the output OUT end of current follower IC2, the lower A/D translation interface end ADC2 end of processor IC3 connects, positive power source terminal+V end of current follower IC2 is connected with stabilized voltage power supply anode VCC end, negative power end-V of current follower IC2 holds ground connection.
Compensation control circuit comprises processor IC3, drive chip IC 4, the clock U5 that shakes, large compensation capacitor C 1, little building-out capacitor C2, large solid-state relay U1, little solid-state relay U2, middle solid-state relay U3, lower solid-state relay U4, the power end VCC end of processor IC3 is connected with stabilized voltage power supply anode VCC end, the ground end GND end ground connection of processor IC3, the shake output OUT of U5 of the clock end XT end of processor IC3 and clock is connected, the clock power end of U5+V end that shakes is held and is connected with stabilized voltage power supply anode VCC, the clock ground end GND end ground connection of U5 of shaking, the 1st output O1 end of processor IC3 is connected with the 1st passage input IN1 that drives chip IC 4, the 2nd output O2 end of processor IC3 is connected with the 2nd passage input IN2 that drives chip IC 4, the 3rd output O3 end of processor IC3 is connected with the 3rd passage input IN3 that drives chip IC 4, the 4th output O4 end of processor IC3 is connected with the 4th passage input IN4 that drives chip IC 4, drive the power end VCC end of chip IC 4 to be connected with stabilized voltage power supply anode VCC end, drive the ground end GND end ground connection of chip IC 4, drive the 1st output OUT1 end of chip IC 4 and negative input end-IN end of large solid-state relay U1 to be connected, drive the 2nd output OUT2 end of chip IC 4 and negative input end-IN end of little solid-state relay U2 to be connected, drive the 3rd output OUT3 end of chip IC 4 and negative input end-IN end of middle solid-state relay U3 to be connected, drive the 4th output OUT4 end of chip IC 4 and negative input end-IN end of lower solid-state relay U4 to be connected, positive input terminal+IN end of large solid-state relay U1, positive input terminal+IN end of little solid-state relay U2, positive input terminal+IN end of positive input terminal+IN end of middle solid-state relay U3 and lower solid-state relay U4 is all connected with stabilized voltage power supply anode VCC end, the 1st of large solid-state relay U1 exchanges end AC1 end, the 1st of little solid-state relay U2 exchanges end AC1 end and is all connected with electrical network phase voltage end L end, the 2nd of large solid-state relay U1 exchanges end AC2 end and is connected with one end of large compensation capacitor C 1, the 2nd of little solid-state relay U2 exchanges one end of end AC2 end and little building-out capacitor C2, the 1st of middle solid-state relay U3 exchanges end AC1 end and connects, the other end of large compensation capacitor C 1, the other end of little building-out capacitor C2 all exchanges end AC1 end with the 1st of lower solid-state relay U4 and is connected, the 2nd of middle solid-state relay U3 exchanges end AC2 end, the 2nd of lower solid-state relay U4 exchanges end AC2 end and is all connected with electrical network zero line side N end.
Beneficial effect of the present invention is as follows:
Utilization of the present invention is carried out the undisturbed combination to electrical network based on four zero type ac solid relays to two compensation condensers and is switched, to realize, the level Four compensation of power factor is controlled, can meet the requirement of most AC load to power factor compensation control, the method cost performance is high, versatility good, safe and reliable.
The easy expanded application of this circuit methods is in the power factor compensation control of three-phase alternating current load system.
Accompanying drawing explanation
Fig. 1 is circuit diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
As shown in Figure 1, exchange the undisturbed Multilevel compensating circuit of using electricity system power factor, comprise voltage-stabilized power supply circuit, phase voltage current signal conditioning circuit, compensation control circuit.
Voltage-stabilized power supply circuit comprises power module of voltage regulation U0, power capacitor C0, voltage regulation resistance R2, prover pipe D1, the phase feeder ear L end of power module of voltage regulation U0 is connected with electrical network phase voltage end L end, the zero line side N end of power module of voltage regulation U0 is connected with electrical network zero line side N end, out-put supply end+V end and the stabilized voltage power supply anode VCC end of power module of voltage regulation U0, one end of power capacitor C0, one end of voltage regulation resistance R2 connects, the other end ground connection of power capacitor C0, the negative electrode of the other end of voltage regulation resistance R2 and prover pipe D1, reference voltage terminal VZ holds connection, the plus earth of prover pipe D1.
Phase voltage current signal conditioning circuit comprises voltage transformer VS1, current transformer CS1, using electricity system PU1, voltage follower IC1, current follower IC2, load resistance R1, bias resistance R3, voltage filter resistance R 4, voltage filter capacitor C 3, upper voltage-stabiliser tube D2, biasing resistance R5, current filtering resistance R 6, current filtering capacitor C 4, lower voltage-stabiliser tube D3, the phase test side L end of voltage transformer VS1 is connected with electrical network phase voltage end L end, the zero line side N end of voltage transformer VS1 is connected with electrical network zero line side N end, the positive output end OUT1 end of voltage transformer VS1 is connected with one end of voltage filter resistance R 4, the negative output terminal OUT2 end ground connection of voltage transformer VS1, positive input terminal+IN end of the other end of voltage filter resistance R 4 and voltage follower IC1, one end of bias resistance R3, the negative electrode of upper voltage-stabiliser tube D2, one end of voltage filter capacitor C 3 connects, the other end of bias resistance R3 is connected with voltage reference end VZ end, the other end ground connection of voltage filter capacitor C 3, the plus earth of upper voltage-stabiliser tube D2, negative input end-IN end of voltage follower IC1 and the output OUT end of voltage follower IC1, the upper A/D translation interface end ADC1 end of processor IC3 connects, positive power source terminal+V end of voltage follower IC1 is connected with stabilized voltage power supply anode VCC end, negative power end-V of voltage follower IC1 holds ground connection, the phase feeder ear L end of using electricity system PU1 connects through the detection Kong Houyu electrical network phase voltage end L end of current transformer CS1 through line, the zero line side N end of using electricity system PU1 is connected with electrical network zero line side N end, the negative output terminal AC2 ground connection of current transformer CS1, the positive output end AC1 of current transformer CS1 and one end of load resistance R1, one end of current filtering resistance R 6 connects, the other end ground connection of load resistance R1, positive input terminal+IN end of the other end of current filtering resistance R 6 and current follower IC2, one end of biasing resistance R5, the negative electrode of lower voltage-stabiliser tube D3, one end of current filtering capacitor C 4 connects, the other end of biasing resistance R5 is connected with voltage reference end VZ end, the other end ground connection of current filtering capacitor C 4, the plus earth of lower voltage-stabiliser tube D3, negative input end-IN end of current follower IC2 and the output OUT end of current follower IC2, the lower A/D translation interface end ADC2 end of processor IC3 connects, positive power source terminal+V end of current follower IC2 is connected with stabilized voltage power supply anode VCC end, negative power end-V of current follower IC2 holds ground connection.
Compensation control circuit comprises processor IC3, drive chip IC 4, the clock U5 that shakes, large compensation capacitor C 1, little building-out capacitor C2, large solid-state relay U1, little solid-state relay U2, middle solid-state relay U3, lower solid-state relay U4, the power end VCC end of processor IC3 is connected with stabilized voltage power supply anode VCC end, the ground end GND end ground connection of processor IC3, the shake output OUT of U5 of the clock end XT end of processor IC3 and clock is connected, the clock power end of U5+V end that shakes is held and is connected with stabilized voltage power supply anode VCC, the clock ground end GND end ground connection of U5 of shaking, the 1st output O1 end of processor IC3 is connected with the 1st passage input IN1 that drives chip IC 4, the 2nd output O2 end of processor IC3 is connected with the 2nd passage input IN2 that drives chip IC 4, the 3rd output O3 end of processor IC3 is connected with the 3rd passage input IN3 that drives chip IC 4, the 4th output O4 end of processor IC3 is connected with the 4th passage input IN4 that drives chip IC 4, drive the power end VCC end of chip IC 4 to be connected with stabilized voltage power supply anode VCC end, drive the ground end GND end ground connection of chip IC 4, drive the 1st output OUT1 end of chip IC 4 and negative input end-IN end of large solid-state relay U1 to be connected, drive the 2nd output OUT2 end of chip IC 4 and negative input end-IN end of little solid-state relay U2 to be connected, drive the 3rd output OUT3 end of chip IC 4 and negative input end-IN end of middle solid-state relay U3 to be connected, drive the 4th output OUT4 end of chip IC 4 and negative input end-IN end of lower solid-state relay U4 to be connected, positive input terminal+IN end of large solid-state relay U1, positive input terminal+IN end of little solid-state relay U2, positive input terminal+IN end of positive input terminal+IN end of middle solid-state relay U3 and lower solid-state relay U4 is all connected with stabilized voltage power supply anode VCC end, the 1st of large solid-state relay U1 exchanges end AC1 end, the 1st of little solid-state relay U2 exchanges end AC1 end and is all connected with electrical network phase voltage end L end, the 2nd of large solid-state relay U1 exchanges end AC2 end and is connected with one end of large compensation capacitor C 1, the 2nd of little solid-state relay U2 exchanges one end of end AC2 end and little building-out capacitor C2, the 1st of middle solid-state relay U3 exchanges end AC1 end and connects, the other end of large compensation capacitor C 1, the other end of little building-out capacitor C2 all exchanges end AC1 end with the 1st of lower solid-state relay U4 and is connected, the 2nd of middle solid-state relay U3 exchanges end AC2 end, the 2nd of lower solid-state relay U4 exchanges end AC2 end and is all connected with electrical network zero line side N end.
All devices including voltage transformer VS1, current transformer CS1, power module of voltage regulation U0, large solid-state relay U1, little solid-state relay U2, middle solid-state relay U3, lower solid-state relay U4, voltage follower IC1, current follower IC2, processor IC3, driving chip IC 4, prover pipe D1, upper voltage-stabiliser tube D2, lower voltage-stabiliser tube D3 etc. used in the present invention all adopt existing matured product, can obtain by market.For example: voltage transformer adopts JDZX10 series of products, voltage source instrument transformer adopts BH-0.66 series of products, power module of voltage regulation adopts WAN2.5-3.3, solid-state relay adopts SSR-H380D zero-based series of products, voltage follower, current follower are all used TLC2274, processor adopting STM32F103, drives chip to adopt anti-phase type to drive chip MC1413, and prover pipe, voltage-stabiliser tube all adopt BZX84-B3 etc.
Main circuit parameter and input/output relation in the present invention are as follows:
The output signal u of voltage transformer VS1 in Fig. 1
v0with electrical network phase voltage u
abetween relation as the formula (1), k wherein
vfor transformer ratio; The output signal u of current transformer CS1
i0with electrical network phase current i
abetween relation as the formula (2), k wherein
ifor unsteady flow coefficient.
u
vo＝k
vu
a （1）
u
io＝R1·k
ii
a （2）
Above-mentioned u
v0, u
i0signal becomes unipolar signal u after electrical level transfer and impedance transformation are followed
v, u
i, after capacitance-resistance filter, respectively suc as formula shown in (3), formula (4), formula (5) is to guarantee that voltage signal, current signal carry out the condition of circuit synchronous filtering.
The course of work of the present invention is as follows:
The output signal u of voltage transformer, current transformer
v0, u
i0after following, capacitance-resistance filter, electrical level transfer, impedance transformation become the signal u that A/D translation interface that unipolarity and amplitude meet processor IC3 requires
v, u
i, be input to respectively the upper A/D translation interface of processor IC3, lower A/D translation interface, by the program that is built in processor, undertaken calculating voltage after synchronous filtering, phase difference between current signal and power-factor of load cos φ value, and in program, be provided with level Four power factor threshold value A, B, C, D, wherein A>B>C>DGreatT. GreaT.GT0, and then processor is according to following discriminant, through each output O1, O2, O3, the O4 end corresponding high level of output or low level control signal, through drive control each zero-cross ssr after chip conducting whether, control the required building-out capacitor putting into operation, capacitor C 1>C2 in Fig. 1.
(1) cos φ >=A: power factor meets the requirements, without the compensation condenser that puts into operation, four solid-state relays are all in off state;
(2) A > cos φ >=B: the fourth stage that puts into operation (minimum) building-out capacitor, now processor output control signal is through driving chip to make solid-state relay U1, U3, U4 conducting, and the capacitance putting into operation is C1 × C2/ (C1+C2);
(3) B > cos φ >=C: the third level of putting into operation (inferior little) building-out capacitor, now processor output control signal is through driving chip to make solid-state relay U2, U4 conducting, and the capacitance putting into operation is C2;
(4) C > cos φ >=D: the second level of putting into operation (inferior large) compensation condenser, now processor output control signal is through driving chip to make solid-state relay U1, U4 conducting, and the capacitance putting into operation is C1;
(5) cos φ < D: the first order that puts into operation (maximum) compensation condenser, now processor output control signal is through driving chip to make solid-state relay U1, U2, U4 conducting, and the capacitance putting into operation is C1+C2.
Therefore, with two capacitors, can realize the compensation control of level Four power factor, and adopt zero passage formula solid-state relay, make the switching process of compensation condenser to electrical network undisturbed, not produce additional harmonic wave.This circuit methods easily expanded application in the power factor compensation control of three-phase alternating current load system.
Claims (3)
1. the undisturbed Multilevel compensating circuit that exchanges using electricity system power factor, comprises voltage-stabilized power supply circuit, phase voltage current signal conditioning circuit, compensation control circuit, it is characterized in that:
Voltage-stabilized power supply circuit comprises power module of voltage regulation U0, power capacitor C0, voltage regulation resistance R2, prover pipe D1, the phase feeder ear L end of power module of voltage regulation U0 is connected with electrical network phase voltage end L end, the zero line side N end of power module of voltage regulation U0 is connected with electrical network zero line side N end, out-put supply end+V end and the stabilized voltage power supply anode VCC end of power module of voltage regulation U0, one end of power capacitor C0, one end of voltage regulation resistance R2 connects, the other end ground connection of power capacitor C0, the negative electrode of the other end of voltage regulation resistance R2 and prover pipe D1, reference voltage terminal VZ holds connection, the plus earth of prover pipe D1,
Phase voltage current signal conditioning circuit comprises voltage transformer VS1, current transformer CS1, using electricity system PU1, voltage follower IC1, current follower IC2, load resistance R1, bias resistance R3, voltage filter resistance R 4, voltage filter capacitor C 3, upper voltage-stabiliser tube D2, biasing resistance R5, current filtering resistance R 6, current filtering capacitor C 4, lower voltage-stabiliser tube D3, the phase test side L end of voltage transformer VS1 is connected with electrical network phase voltage end L end, the zero line side N end of voltage transformer VS1 is connected with electrical network zero line side N end, the positive output end OUT1 end of voltage transformer VS1 is connected with one end of voltage filter resistance R 4, the negative output terminal OUT2 end ground connection of voltage transformer VS1, positive input terminal+IN end of the other end of voltage filter resistance R 4 and voltage follower IC1, one end of bias resistance R3, the negative electrode of upper voltage-stabiliser tube D2, one end of voltage filter capacitor C 3 connects, the other end of bias resistance R3 is connected with voltage reference end VZ end, the other end ground connection of voltage filter capacitor C 3, the plus earth of upper voltage-stabiliser tube D2, negative input end-IN end of voltage follower IC1 and the output OUT end of voltage follower IC1, the upper A/D translation interface end ADC1 end of processor IC3 connects, positive power source terminal+V end of voltage follower IC1 is connected with stabilized voltage power supply anode VCC end, negative power end-V of voltage follower IC1 holds ground connection, the phase feeder ear L end of using electricity system PU1 connects through the detection Kong Houyu electrical network phase voltage end L end of current transformer CS1 through line, the zero line side N end of using electricity system PU1 is connected with electrical network zero line side N end, the negative output terminal AC2 ground connection of current transformer CS1, the positive output end AC1 of current transformer CS1 and one end of load resistance R1, one end of current filtering resistance R 6 connects, the other end ground connection of load resistance R1, positive input terminal+IN end of the other end of current filtering resistance R 6 and current follower IC2, one end of biasing resistance R5, the negative electrode of lower voltage-stabiliser tube D3, one end of current filtering capacitor C 4 connects, the other end of biasing resistance R5 is connected with voltage reference end VZ end, the other end ground connection of current filtering capacitor C 4, the plus earth of lower voltage-stabiliser tube D3, negative input end-IN end of current follower IC2 and the output OUT end of current follower IC2, the lower A/D translation interface end ADC2 end of processor IC3 connects, positive power source terminal+V end of current follower IC2 is connected with stabilized voltage power supply anode VCC end, negative power end-V of current follower IC2 holds ground connection,
Compensation control circuit comprises processor IC3, drive chip IC 4, the clock U5 that shakes, large compensation capacitor C 1, little building-out capacitor C2, large solid-state relay U1, little solid-state relay U2, middle solid-state relay U3, lower solid-state relay U4, the power end VCC end of processor IC3 is connected with stabilized voltage power supply anode VCC end, the ground end GND end ground connection of processor IC3, the shake output OUT of U5 of the clock end XT end of processor IC3 and clock is connected, the clock power end of U5+V end that shakes is held and is connected with stabilized voltage power supply anode VCC, the clock ground end GND end ground connection of U5 of shaking, the 1st output O1 end of processor IC3 is connected with the 1st passage input IN1 that drives chip IC 4, the 2nd output O2 end of processor IC3 is connected with the 2nd passage input IN2 that drives chip IC 4, the 3rd output O3 end of processor IC3 is connected with the 3rd passage input IN3 that drives chip IC 4, the 4th output O4 end of processor IC3 is connected with the 4th passage input IN4 that drives chip IC 4, drive the power end VCC end of chip IC 4 to be connected with stabilized voltage power supply anode VCC end, drive the ground end GND end ground connection of chip IC 4, drive the 1st output OUT1 end of chip IC 4 and negative input end-IN end of large solid-state relay U1 to be connected, drive the 2nd output OUT2 end of chip IC 4 and negative input end-IN end of little solid-state relay U2 to be connected, drive the 3rd output OUT3 end of chip IC 4 and negative input end-IN end of middle solid-state relay U3 to be connected, drive the 4th output OUT4 end of chip IC 4 and negative input end-IN end of lower solid-state relay U4 to be connected, positive input terminal+IN end of large solid-state relay U1, positive input terminal+IN end of little solid-state relay U2, positive input terminal+IN end of positive input terminal+IN end of middle solid-state relay U3 and lower solid-state relay U4 is all connected with stabilized voltage power supply anode VCC end, the 1st of large solid-state relay U1 exchanges end AC1 end, the 1st of little solid-state relay U2 exchanges end AC1 end and is all connected with electrical network phase voltage end L end, the 2nd of large solid-state relay U1 exchanges end AC2 end and is connected with one end of large compensation capacitor C 1, the 2nd of little solid-state relay U2 exchanges one end of end AC2 end and little building-out capacitor C2, the 1st of middle solid-state relay U3 exchanges end AC1 end and connects, the other end of large compensation capacitor C 1, the other end of little building-out capacitor C2 all exchanges end AC1 end with the 1st of lower solid-state relay U4 and is connected, the 2nd of middle solid-state relay U3 exchanges end AC2 end, the 2nd of lower solid-state relay U4 exchanges end AC2 end and is all connected with electrical network zero line side N end.
2. the undisturbed Multilevel compensating circuit of interchange using electricity system power factor as claimed in claim 1, is characterized in that:
The output signal u of described voltage transformer VS1
v0with electrical network phase voltage u
abetween relation as the formula (1), k wherein
vfor transformer ratio; The output signal u of current transformer CS1
i0with electrical network phase current i
abetween relation as the formula (2), k wherein
ifor unsteady flow coefficient:
u
vo＝k
vu
a （1）
u
io＝R1·k
ii
a （2）
Above-mentioned u
v0, u
i0signal becomes unipolar signal u after electrical level transfer and impedance transformation are followed
v, u
i, after capacitance-resistance filter, suc as formula shown in (3), formula (4), formula (5) is for to guarantee that voltage signal, current signal carry out the condition of circuit synchronous filtering respectively:
3. the undisturbed Multilevel compensating circuit of interchange using electricity system power factor as claimed in claim 1, is characterized in that:
Described voltage transformer VS1, current transformer CS1, power module of voltage regulation U0, large solid-state relay U1, little solid-state relay U2, middle solid-state relay U3, lower solid-state relay U4, voltage follower IC1, current follower IC2, processor IC3, drive chip IC 4, prover pipe D1, upper voltage-stabiliser tube D2, lower voltage-stabiliser tube D3 all adopts existing matured product, voltage transformer adopts JDZX10 series of products, voltage source instrument transformer adopts BH-0.66 series of products, power module of voltage regulation adopts WAN2.5-3.3, solid-state relay adopts SSR-H380D zero-based series of products, voltage follower, current follower is all used TLC2274, processor adopting STM32F103, drive chip to adopt anti-phase type to drive chip MC1413, prover pipe, voltage-stabiliser tube all adopts BZX84-B3.
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| CN201410040859.5A CN103762608B (en) | 2014-01-28 | 2014-01-28 | Exchange the undisturbed Multilevel compensating circuit of using electricity system power factor |
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| JP3404936B2 (en) * | 1994-09-08 | 2003-05-12 | ソニー株式会社 | Current resonant switching power supply circuit |
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| CN101286639A (en) * | 2007-04-09 | 2008-10-15 | 香港理工大学 | Continuously adjustable reactive power compensator with low cost |
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Effective date of registration: 20180522 Address after: 211302 3 3, North Pine Road, Chun Xi Town, Gaochun District, Nanjing, Jiangsu. Patentee after: NANJING DING CHUN ELECTRIC Co.,Ltd. Address before: 518000 Guangdong Shenzhen Longhua New District big wave street Longsheng community Tenglong road gold rush e-commerce incubation base exhibition hall E commercial block 706 Patentee before: Shenzhen Meliao Technology Transfer Center Co.,Ltd. Effective date of registration: 20180522 Address after: 518000 Guangdong Shenzhen Longhua New District big wave street Longsheng community Tenglong road gold rush e-commerce incubation base exhibition hall E commercial block 706 Patentee after: Shenzhen Meliao Technology Transfer Center Co.,Ltd. Address before: 310018 2 street, Xiasha Higher Education Park, Hangzhou, Zhejiang Patentee before: HANGZHOU DIANZI University |