CN103747113A - Method for automatically recognizing MII (Media Independent Interface) address of PHY (Physical Layer) chip of Ethernet controller - Google Patents
Method for automatically recognizing MII (Media Independent Interface) address of PHY (Physical Layer) chip of Ethernet controller Download PDFInfo
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- CN103747113A CN103747113A CN201310740744.2A CN201310740744A CN103747113A CN 103747113 A CN103747113 A CN 103747113A CN 201310740744 A CN201310740744 A CN 201310740744A CN 103747113 A CN103747113 A CN 103747113A
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Abstract
The invention provides a method for automatically recognizing an MII (Media Independent Interface) address of a PHY (Physical Layer) chip of an Ethernet controller. The method comprises the following steps: opening up a storage space capable of storing thirty-two communication addresses; performing communication on the communication addresses one by one so as to acquire Chip ID data; judging the validity of the Chip ID, and writing the effective Chip ID data into an independent address list. Communication is performed on the thirty-two addresses one by one, so that the accuracy rate is improved, a driver can automatically adapt to different PHY hardware addresses, and the production efficiency is improved.
Description
Technical field
The present invention relates to hardware address identification, particularly a kind of ethernet PHY chip MII address is known method for distinguishing automatically.
Background technology
In relating to the pcb board production process of ethernet controller PHY chip, one section of middle production process need to be obtained ethernet controller PHY chip address, just can carry out follow-up operation.Common way is in program, to reserve in advance and ethernet controller PHY chip address corresponding on circuit, or import into driving by manual modification of some system interfaces, to change the address of ethernet controller PHY chip, but this situation tends to cause drive and cannot automatically revise, and reduces manufacturing schedule.
Summary of the invention
For addressing the above problem, the object of the present invention is to provide a kind of ethernet controller PHY chip MII address automatically to know method for distinguishing, automatically identify the mailing address of MII register, improve the production efficiency in production process.
The present invention solves the technical scheme that its problem adopts:
Ethernet controller PHY chip MII knows a method for distinguishing in address automatically, comprising:
Initialization ethernet controller;
Hew out the memory space that can store 32 mailing addresses;
By these 32 mailing addresses, communicate successively, and the Chip ID return address at every turn obtaining is write to corresponding memory space;
From the first address of memory space, automatically read Chip ID address date wherein, and with 0x1ffffffff phase with, if with result and 0x1ffffffff identical, give up these data, otherwise, these data are write in independent address list, afterwards, first address is added to 1 and carry out same operation, until 32 address spaces read complete;
Mailing address using first address in address list as MII.
Described when hewing out the memory space that can store 32 mailing addresses, the first address of described memory space is set to zero.
Described while communicating by this 32 mailing address successively, from the first address of memory space, start to communicate successively.
The invention has the beneficial effects as follows:
The present invention adopts a kind of ethernet controller PHY chip MII address automatically to know method for distinguishing, by hewing out the memory space that can store 32 mailing addresses, automatically identifies the mailing address of MII register, thereby improves follow-up production efficiency.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and example, the invention will be further described.
Fig. 1 is the method for the invention flow chart.
Embodiment
Shown in Fig. 1, the invention provides a kind of ethernet controller PHY chip MII address and automatically know method for distinguishing, comprising:
Initialization ethernet controller;
In the MII of ethernet controller register, hew out the memory space that can store 32 mailing addresses;
By these 32 mailing addresses, communicate successively, and the Chip ID return address at every turn obtaining is write to corresponding memory space;
From the first address of memory space, automatically read Chip ID data wherein, and with 0x1ffffffff phase with, if with result and 0x1ffffffff identical, give up these data, otherwise, these data are write in independent address list, afterwards, first address is added to 1 and carry out same operation, until 32 address spaces read complete;
Mailing address using first address in address list as MII.
When opening up memory space, in order to facilitate the understanding in space and to read, the first address of this memory space is set to 0.
When communicating by these 32 mailing addresses successively, the Chip ID address of returning for fear of it and mailing address inconsistent, the first address that is 0 from memory space starts to detect and communicate successively, returned Chip ID address can be write in corresponding mailing address.
The present invention communicates and attempts obtaining Chip ID one by one to 0 ~ 31 address, judgement validity, promotes accuracy rate, can correctly effectively identify the mailing address of Ethernet phy chip on pcb board, make the PHY hardware address that drives automatic adaptation different, improving production efficiency.
The above, be preferred embodiment of the present invention, and the present invention is not limited to above-mentioned execution mode, as long as it reaches technique effect of the present invention with identical means, all should belong to protection scope of the present invention.
Claims (3)
1. ethernet controller PHY chip MII address is known a method for distinguishing automatically, it is characterized in that, comprising:
Initialization ethernet controller;
Hew out the memory space that can store 32 mailing addresses;
By these 32 mailing addresses, communicate successively, and the Chip ID return address at every turn obtaining is write to corresponding memory space;
From the first address of memory space, automatically read Chip ID data wherein, and with 0x1ffffffff phase with, if with result and 0x1ffffffff identical, give up these data, otherwise, these data are write in independent address list, afterwards, first address is added to 1 and carry out same operation, until 32 address spaces read complete;
Mailing address using first address in address list as MII.
2. method according to claim 1, is characterized in that, described when hewing out the memory space that can store 32 mailing addresses, and the first address of described memory space is set to zero.
3. method according to claim 2, is characterized in that, described while communicating by this 32 mailing address successively, from the first address of memory space, starts to communicate successively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310740744.2A CN103747113B (en) | 2013-12-27 | 2013-12-27 | Method for automatically recognizing MII (Media Independent Interface) address of PHY (Physical Layer) chip of Ethernet controller |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310740744.2A CN103747113B (en) | 2013-12-27 | 2013-12-27 | Method for automatically recognizing MII (Media Independent Interface) address of PHY (Physical Layer) chip of Ethernet controller |
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| Publication Number | Publication Date |
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| CN103747113A true CN103747113A (en) | 2014-04-23 |
| CN103747113B CN103747113B (en) | 2017-05-03 |
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| CN201310740744.2A Active CN103747113B (en) | 2013-12-27 | 2013-12-27 | Method for automatically recognizing MII (Media Independent Interface) address of PHY (Physical Layer) chip of Ethernet controller |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104363043A (en) * | 2014-10-31 | 2015-02-18 | 上海昭赫信息技术有限公司 | Automatic recognition method for pluggable module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6256324B1 (en) * | 1997-09-10 | 2001-07-03 | Cisco Technology, Inc. | Chip address allocation through a serial data ring on a stackable repeater |
| CN102611592A (en) * | 2011-11-25 | 2012-07-25 | 中国西电电气股份有限公司 | Ethernet RMII (reduced medium independent interface) based on FPGA (field programmable gate array) and realization method |
| CN103164368A (en) * | 2013-03-29 | 2013-06-19 | 惠州Tcl移动通信有限公司 | Method and system enabling embedded device to be compatible with different address mapping internal storage chips |
| CN103235767A (en) * | 2013-04-11 | 2013-08-07 | 和记奥普泰通信技术有限公司 | Serial communication method for master-slave MII (Media Independent Interface) management interfaces |
-
2013
- 2013-12-27 CN CN201310740744.2A patent/CN103747113B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6256324B1 (en) * | 1997-09-10 | 2001-07-03 | Cisco Technology, Inc. | Chip address allocation through a serial data ring on a stackable repeater |
| CN102611592A (en) * | 2011-11-25 | 2012-07-25 | 中国西电电气股份有限公司 | Ethernet RMII (reduced medium independent interface) based on FPGA (field programmable gate array) and realization method |
| CN103164368A (en) * | 2013-03-29 | 2013-06-19 | 惠州Tcl移动通信有限公司 | Method and system enabling embedded device to be compatible with different address mapping internal storage chips |
| CN103235767A (en) * | 2013-04-11 | 2013-08-07 | 和记奥普泰通信技术有限公司 | Serial communication method for master-slave MII (Media Independent Interface) management interfaces |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104363043A (en) * | 2014-10-31 | 2015-02-18 | 上海昭赫信息技术有限公司 | Automatic recognition method for pluggable module |
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| CN103747113B (en) | 2017-05-03 |
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