CN103745952A - Preparation method for mixed crystal substrate with insulation buried layer - Google Patents
Preparation method for mixed crystal substrate with insulation buried layer Download PDFInfo
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- CN103745952A CN103745952A CN201310724870.9A CN201310724870A CN103745952A CN 103745952 A CN103745952 A CN 103745952A CN 201310724870 A CN201310724870 A CN 201310724870A CN 103745952 A CN103745952 A CN 103745952A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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Abstract
The invention provides a preparation method for a mixed crystal substrate with an insulation buried layer. The method comprises the following steps: providing a first substrate and a second substrate, wherein the first substrate comprises a first support layer, a first buried layer on the surface of the first support layer, and a first device layer on the surface of the first buried layer, the first device layer is provided with a first crystal orientation, the second substrate comprises a second support layer, the second buried layer on the surface of the second support layer, and a second device layer on the surface of the second buried layer, and the second device layer is provided with a second crystal orientation; forming an isolation layer on the surface of the first device layer and/or the surface of the second device layer; by taking the isolation layer as an intermediate layer, bonding the first substrate and the second substrate; removing the second support layer and the second buried layer; forming a window in the second device layer and the isolation layer to expose the first device layer; and growing a third device layer in the window in an epitaxial manner, the third device layer being provided with a first crystal orientation. The method provided by the invention can improve the mass of two crystals in the mixed crystal substrate.
Description
Technical field
The present invention relates to field of semiconductor materials, relate in particular to a kind of preparation method of the mixed crystal substrate with insulating buried layer.
Background technology
Silicon (SOI) substrate on insulator, as a kind of semi-conducting material with insulating buried layer, is regarded as one of important materials of following microelectric technique development.
In the prior art, the top layer silicon of SOI substrate is all single crystal orientation, and crystallographic orientation novel channel material and Si Platform integration, thereby make full use of ripe silicon microelectronic technique and equipment, become one of trend of current integrated circuit development.We can prepare different components on the material of particular crystal orientation, bring into play separately the advantage of particular crystal orientation.For example: we can make NFET on (100) surface, on (110) surface, prepare PFET.(100) crystal orientation provides and has high performance NFET, and (110) crystal orientation provides and has high performance PFET.But the mode that different components is prepared on the material of different crystal orientations must need a kind of backing material that can comprise multiple crystal orientation, i.e. so-called mixed crystal substrate.But comprise different crystal orientations in a substrate, will certainly influence each other, cause serious lattice adaptation, cause crystal mass to decline.
Therefore, can propose a kind of method of preparing high-quality mixed crystal SOI substrate, be prior art urgent problem.
Summary of the invention
Technical problem to be solved by this invention is, a kind of preparation method of the mixed crystal substrate with insulating buried layer is provided, and can improve two kinds of crystal mass in mixed crystal substrate.
In order to address the above problem, the invention provides a kind of preparation method of the mixed crystal substrate with insulating buried layer, comprise the steps: to provide the first substrate and the second substrate, described the first substrate comprises the first buried regions of the first supporting layer, the first support layer surface and first device layer on the first buried regions surface, described the first device layer has the first crystal orientation, described the second substrate comprises the second buried regions of the second supporting layer, the second support layer surface and second device layer on the second buried regions surface, and described the second device layer has the second crystal orientation; Surface at the first device layer and/or the second device layer forms separator; Take separator as intermediate layer, by the first substrate together with the second substrate bonding; Remove the second supporting layer and the second buried regions; In the second device layer and separator, form window, to expose the first device layer; Epitaxial growth the 3rd device layer in window, described the 3rd device layer has the first crystal orientation.
Optionally, in the second device layer and separator, form after window, the surface that is further included in window sidewall and the second device layer forms the step of protective layer.
Optionally, the material of described protective layer is selected from any one in silica and silicon nitride.
Optionally, after formation the 3rd device layer, further comprise the steps: to form groove in the interface of the 3rd device layer and the second device layer; Fill described groove, form side wall.
Optionally, described the first crystal orientation is (100) crystal orientation, and the second crystal orientation is (110) crystal orientation.
Optionally, described the first crystal orientation is (110) crystal orientation, and the second crystal orientation is (100) crystal orientation.
Optionally, forming the surperficial step that further comprises polishing the second device layer and the 3rd device layer after the 3rd device layer.
The invention has the advantages that, the 3rd device layer in mixed crystal is by coming in the direct epitaxial growth of the first device layer, and the lattice of the second device layer is not affected in whole technological processes, has therefore improved two kinds of crystal mass in mixed crystal substrate.
Accompanying drawing explanation
Accompanying drawing 1 is the implementation step schematic diagram of the specific embodiment of the invention.
Accompanying drawing 2A is to shown in accompanying drawing 2J being the process schematic representation of the specific embodiment of the invention.
Embodiment
The embodiment of preparation method below in conjunction with accompanying drawing to the mixed crystal substrate with insulating buried layer provided by the invention elaborates.
Accompanying drawing 1 is the implementation step schematic diagram of the specific embodiment of the invention, comprise: step S10, the first substrate and the second substrate are provided, described the first substrate comprises the first buried regions of the first supporting layer, the first support layer surface and first device layer on the first buried regions surface, described the first device layer has the first crystal orientation, described the second substrate comprises the second buried regions of the second supporting layer, the second support layer surface and second device layer on the second buried regions surface, and described the second device layer has the second crystal orientation; Step S11, forms separator on the surface of the first device layer and/or the second device layer; Step S12, take separator as intermediate layer, by the first substrate together with the second substrate bonding; Step S13, removes the second supporting layer and the second buried regions; Step S14 forms window in the second device layer and separator, to expose the first device layer; Step S15, forms protective layer on the surface of window sidewall and the second device layer; Step S16, epitaxial growth the 3rd device layer in window, described the 3rd device layer has the first crystal orientation; Step S17, the surface of polishing the second device layer and the 3rd device layer; Step S18, forms groove in the interface of the 3rd device layer and the second device layer; Step S19, fills described groove, forms side wall.
Accompanying drawing 2A is to shown in accompanying drawing 2J being the process schematic representation of the specific embodiment of the invention.
Shown in accompanying drawing 2A, refer step S10, the first substrate 10 and the second substrate 20 are provided, described the first substrate 10 comprises the first supporting layer 11, first buried regions 12 on the first supporting layer 11 surfaces and first device layer 13 on the first buried regions surface 12, described the first device layer 13 has the first crystal orientation, described the second substrate 20 comprises the second supporting layer 21, second buried regions 22 on the second supporting layer 21 surfaces and second device layer 23 on the second buried regions 22 surfaces, and described the second device layer 23 has the second crystal orientation.
Described the first substrate 10 and the second substrate 20 can be to adopt isolation from oxygen to inject SOI material prepared by (SIMOX) technique.
The material of described the first supporting layer 11 can be to comprise any one common semi-conducting materials such as monocrystalline silicon, sapphire and carborundum, and this embodiment is monocrystalline silicon.The material of described the first buried regions 12 can be silica or silicon nitride, and this embodiment is silica.The material of described the first device layer 13 can be any one common semi-conducting materials such as monocrystalline silicon, monocrystalline germanium, germanium silicon, and this embodiment is monocrystalline silicon, and the first crystal orientation is (100) crystal orientation.
The material of described the second supporting layer 21 can be to comprise any one common semi-conducting materials such as monocrystalline silicon, sapphire and carborundum, and this embodiment is monocrystalline silicon.The material of described the second buried regions 22 can be silica or silicon nitride, and this embodiment is silica.The material of described the second device layer 23 can be any one common semi-conducting materials such as monocrystalline silicon, monocrystalline germanium, germanium silicon, and this embodiment is monocrystalline silicon, and the second crystal orientation is (110) crystal orientation.
Shown in accompanying drawing 2B, refer step S11, forms separator 40 on the surface of the first device layer 13 and/or the second device layer 23.The surface that this embodiment is selected at the first device layer 13 forms separator 40, in other embodiment, also can be to form separator 40 on the surface of the second device layer 23, or all form separator on the surface of the first device layer 13 and the second device layer 23.The effect that separator 40 plays is to strengthen bond strength, and isolation has the first device layer 13 and second device layer 23 of different crystal orientations, avoid both in interface because lattice mismatch produces defect.Therefore the material of separator 40 can be silica or silicon nitride etc., this embodiment is silica.
Shown in accompanying drawing 2C, refer step S12, take separator 40 as intermediate layer, is bonded together the first substrate 10 and the second substrate 20.Bonding can adopt electrostatic bonding or plasmaassisted bonding etc.
Shown in accompanying drawing 2D, refer step S13, removes the second supporting layer 21 and the second buried regions 22.Can adopt the method for dry etching or wet etching to remove said structure.Also can first adopt method attenuate second supporting layer 21 of grinding, to reduce the time of subsequent corrosion.
Shown in accompanying drawing 2E, refer step S14 forms window in the second device layer 23 and separator 40, to expose the first device layer 13.Form window and can adopt the method for photoetching to form mask layer (not shown), and adopt the method for dry etching or wet etching to remove the second device layer 23 and the separator 40 at window place, to the surface that exposes the first device layer 13.
Shown in accompanying drawing 2F, refer step S15, forms protective layer 50 at the sidewall of window and the surface of the second device layer 23.This step is optional step.Due to follow-up, need to pass through window grown epitaxial layer, and the crystal orientation of epitaxial loayer and the second device layer 23 are different, therefore the protective layer 50 on sidewall is conducive to prevent between the two because lattice mismatch produces defect.The protective layer on the second device layer 23 surfaces can prevent that the surface of the second device layer 23 from also continuing epitaxial growth and being thickened.
Shown in accompanying drawing 2G, refer step S16, epitaxial growth the 3rd device layer 33 in window, described the 3rd device layer 33 has the first crystal orientation.Because the 3rd device layer 33 grows from the first device layer 13, therefore both should have identical crystal orientation.So far, with the mixed crystal substrate of insulating buried layer with prepared, the first buried regions 12 is described insulating buried layer, and second device layer 23 on its surface has the second crystal orientation, and the 3rd device layer 33 has the first crystal orientation.The 3rd device layer 33 is by coming in the direct epitaxial growth of the first device layer 13, and therefore crystal mass is higher.Follow-up step is optional step, is intended to reduce the defect of above-mentioned mixed crystal substrate or improves its surface smoothness.
Shown in accompanying drawing 2H, refer step S17, the surface of polishing the second device layer 23 and the 3rd device layer 33.Because the very difficult surface of controlling the 3rd device layer 33 and the second device layer 23 of epitaxial growth is in same level, therefore can carry out polishing to its surface.If there is growth protecting layer 50 before, this step can also further play the effect of the protective layer 50 of removing the second device layer 23 surfaces.
Shown in accompanying drawing 2I, step S18, forms groove in the interface of the 3rd device layer 33 and the second device layer 23.Can adopt the mode of photoetching to form mask layer (not shown), and adopt the method for dry etching or wet etching to form groove 60.
Shown in accompanying drawing 2J, step S19, fills described groove, forms side wall 70.The packing material of this step can be silica or silicon nitride.Because protective layer 50 is formed on sidewall, thickness is restricted, and in order to guarantee the isolation effect of the 3rd device layer 33 and the second device layer 23, can select again to form side wall 70 and isolate both.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. with a preparation method for the mixed crystal substrate of insulating buried layer, it is characterized in that, comprise the steps:
The first substrate and the second substrate are provided, described the first substrate comprises the first buried regions of the first supporting layer, the first support layer surface and first device layer on the first buried regions surface, described the first device layer has the first crystal orientation, described the second substrate comprises the second buried regions of the second supporting layer, the second support layer surface and second device layer on the second buried regions surface, and described the second device layer has the second crystal orientation;
Surface at the first device layer and/or the second device layer forms separator;
Take separator as intermediate layer, by the first substrate together with the second substrate bonding;
Remove the second supporting layer and the second buried regions;
In the second device layer and separator, form window, to expose the first device layer;
Epitaxial growth the 3rd device layer in window, described the 3rd device layer has the first crystal orientation.
2. the preparation method of the mixed crystal substrate with insulating buried layer according to claim 1, is characterized in that, in the second device layer and separator, forms after window, and the surface that is further included in window sidewall and the second device layer forms the step of protective layer.
3. the preparation method of the mixed crystal substrate with insulating buried layer according to claim 2, is characterized in that, the material of described protective layer is selected from any one in silica and silicon nitride.
4. the preparation method of the mixed crystal substrate with insulating buried layer according to claim 1, is characterized in that, after formation the 3rd device layer, further comprises the steps:
Interface at the 3rd device layer and the second device layer forms groove;
Fill described groove, form side wall.
5. the preparation method of the mixed crystal substrate with insulating buried layer according to claim 1, is characterized in that, described the first crystal orientation is (100) crystal orientation, and the second crystal orientation is (110) crystal orientation.
6. the preparation method of the mixed crystal substrate with insulating buried layer according to claim 1, is characterized in that, described the first crystal orientation is (110) crystal orientation, and the second crystal orientation is (100) crystal orientation.
7. the preparation method of the mixed crystal substrate with insulating buried layer according to claim 1, is characterized in that, is forming the surperficial step that further comprises polishing the second device layer and the 3rd device layer after the 3rd device layer.
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| CN201310724870.9A CN103745952B (en) | 2013-12-25 | 2013-12-25 | With the preparation method of the mixed crystal substrate of insulating buried layer |
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| CN201310724870.9A CN103745952B (en) | 2013-12-25 | 2013-12-25 | With the preparation method of the mixed crystal substrate of insulating buried layer |
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| CN103745952A true CN103745952A (en) | 2014-04-23 |
| CN103745952B CN103745952B (en) | 2016-04-06 |
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Citations (6)
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| US20050116290A1 (en) * | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
| CN101692440A (en) * | 2009-10-13 | 2010-04-07 | 上海新傲科技股份有限公司 | Mixed crystal orientation strain silicon substrate and method for preparing same |
| CN101692436A (en) * | 2009-10-13 | 2010-04-07 | 上海新傲科技股份有限公司 | Method for preparing mixed crystal orientation strain silicon substrate with insulated buried layer |
| CN102768983A (en) * | 2012-07-12 | 2012-11-07 | 上海新傲科技股份有限公司 | Method for preparing mixed crystal orientation substrate with insulating buried layer |
| CN102790004A (en) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of full-isolation mixed crystal orientation crystal orientation silicon-on-insulator (SOI) |
| CN103295951A (en) * | 2012-02-27 | 2013-09-11 | 中国科学院上海微系统与信息技术研究所 | Device system structure and preparing method based on mixed crystal orientation SOI |
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2013
- 2013-12-25 CN CN201310724870.9A patent/CN103745952B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050116290A1 (en) * | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
| CN101692440A (en) * | 2009-10-13 | 2010-04-07 | 上海新傲科技股份有限公司 | Mixed crystal orientation strain silicon substrate and method for preparing same |
| CN101692436A (en) * | 2009-10-13 | 2010-04-07 | 上海新傲科技股份有限公司 | Method for preparing mixed crystal orientation strain silicon substrate with insulated buried layer |
| CN102790004A (en) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of full-isolation mixed crystal orientation crystal orientation silicon-on-insulator (SOI) |
| CN103295951A (en) * | 2012-02-27 | 2013-09-11 | 中国科学院上海微系统与信息技术研究所 | Device system structure and preparing method based on mixed crystal orientation SOI |
| CN102768983A (en) * | 2012-07-12 | 2012-11-07 | 上海新傲科技股份有限公司 | Method for preparing mixed crystal orientation substrate with insulating buried layer |
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