CN103744352A - FPGA-based cubic B-spline curve hardware interpolator - Google Patents

Abstract

The invention discloses a field programmable gate array (FPGA)-based cubic B-spline curve hardware interpolator. The interpolator comprises: an ARM/FPGA data interaction module, which is used for receiving control point data of spline curve from an ARM and storing the data into a random access memory (RAM); a spline curve parameter calculation module, which is used for reading the control point data from the RAM and calculating the coefficient of the spline curve; a fine interpolation point calculation module, which is used for carrying out precomputation before recursion and then calculating interpolation point data of each fine interpolation period according to the coefficient of the spline curve; a floating point operation module, which is used for completing integer calculating, floating point calculation and data format conversion during the process of interpolation calculation by the fine interpolation point calculation module; and a pulse sending module, which is used for receiving the interpolation point data of each fine interpolation period and outputting an interpolation pulsed quantity of each fine interpolation period according to the interpolation point data. According to the invention, the optimized control point is used for parameter calculation of the B-spline curve; and the calculation with the fast speed can be carried out simply.

Description

A kind of hardware interpolator of the B-spline Curve based on FPGA

Technical field

The invention belongs to numerically-controlled machine processing technique field, more specifically, relate to a kind of hardware interpolator of the B-spline Curve based on FPGA, for the curve interpolating of digital control system.

Background technology

Along with the high speed development of Numeric Control Technology theory, process technology is towards the future development of high speed and super precision, and the part curved surface of processing becomes increasingly complex, and surface accuracy requires more and more higher, and the treatment of surfaces of components mostly is free structure curved surface now, has complicated surface information.Traditional digital control system only possesses straight line and circular interpolation function, (the computer Aided Manufacturing of computer-aided manufacturing like this, CAM) the little line segment that software must be separated into parametric line enormous amount is used for digital control system, but machining information amount is huge like this, and straight line and circular arc can not be true, complete Response calculation machine Computer Aided Design (Computer Aided Design, CAD) the complex-curved information that/CAM system generates, thus the requirement of manufacturing accuracy off-design caused.The profile that therefore, need to use batten parametric line directly to carry out complex curve is described and processing.

Patent documentation 200910055485.3 discloses a kind of based on field programmable gate array (Field-Programmable Gate Array, FPGA) hardware pulse interpolator, mainly comprise the pulse data that buffering bus is inputted First Input First Output (the First Input First Output that certain status information is provided, FIFO) interface module, the FIFO control module of reading data in FIFO and shaking hands with pulse interpolation module, and the pulse interpolation module of gating pulse interpolation direction and output pulse signal.

Patent documentation 201210217490.1 disclose a kind of based on PC-FPGA non-homogeneous B spline curve (Non-Uniform Rational B-Splines, NURBS) Real-time interpolation algorithm of curve, carries out interpolation operation then by downloading FPGA motion controller by Ethernet after the discrete control point set of CAD/CAM Software Create.

Patent documentation 201210510779.2 discloses a kind of nurbs curve real-time interpolation module for embedded system, mainly carried out the segmentation of nurbs curve, then according to the turning point of nurbs curve, plan speed of feed, finally by CPLD (Complex Programmable Logic Device, CPLD), control servomotor interlock and carry out interpolation.

The spline interpolation implementation method of existing fields of numeric control technique is a lot, method based on PC mode implements too complicated, and the interpolation of carrying out NURBS in ARM is calculated, can make the calculation task of system overweight, and algorithm complexity cause FPGA resource consumption too many.Also do not have up till now a kind of mode can both improve the speed that interpolation is calculated, and less consumption fpga logic resource.

Summary of the invention

For above defect or the Improvement requirement of prior art, the invention provides a kind of hardware interpolator of the B-spline Curve based on FPGA, its object is to solve carries out at software view the problem that curve interpolating counting yield is low by ARM, and FPGA carries out the too complicated problem of interpolation computational algorithm, solve thus the high precision in the processing of field of machining complex curve curved surface part, high-speed technical matters.

For achieving the above object, according to one aspect of the present invention, a kind of B-spline Curve hardware interpolator based on FPGA is provided, comprise ARM/FPGA data interaction module, SPL parameter calculating module, smart interpolated point computing module, pulse sending module and floating-point operation module, wherein:

Described ARM/FPGA data interaction module, for receive the reference mark data of B-spline Curve from ARM, and is deposited in random access memory (Random Access Memory, RAM);

Described SPL parameter calculating module, for read the reference mark data of B-spline Curve from described RAM, and calculates the coefficient of B-spline Curve;

Essence interpolated point computing module, for obtain the coefficient of B-spline Curve from SPL parameter calculating module, first carries out the precomputation before recursion, then calculates the interpolated point data of each smart interpolation cycle;

Floating-point operation module, for carrying out interpolation computation process at smart interpolated point computing module, completes integer and calculates, Floating-point Computation and Data Format Transform;

Pulse sending module, for receiving the interpolated point data of each smart interpolation cycle of smart interpolated point computing module output, and according to the interpolation pulsed quantity of the each smart interpolation cycle of described interpolated point data output.

Preferably, described RAM is dual port RAM, carry out ping-pong operation, in ARM/FPGA data interaction module, the reference mark data of B-spline curves are write to a RAM in dual port RAM constantly, the reference mark data that read B-spline curves during another RAM from dual port RAM of SPL parameter calculating module, two block RAMs in dual port RAM carry out read-write operation in turn.

Further preferably, described SPL parameter calculating module comprises coordinate translation module and parameter of curve computing module, wherein:

Described coordinate translation module, for coordinate translation is carried out in the reference mark of B-spline Curve, moves to coordinate system on first reference mark;

Described parameter of curve computing module is for calculating SPL parameter according to the reference mark after balance, and the computing formula of SPL parameter is:

$\left\{\begin{array}{c}{R}_3=\frac{4{Q^{\′}}_i+{Q^{\′}}_{i+1}}{6}\\ R_2=\frac{{Q^{\′}}_{i+1}}{2T}\\ R_1=\frac{{Q^{\′}}_{i+1}-2{Q^{\′}}_i}{{2T}^2}\\ R_0=\frac{{Q^{\′}}_{i+2}+3{Q^{\′}}_i-3{Q^{\′}}_{i+1}}{{6T}^3}\end{array}\right.$

Wherein, 0, Q ' _i, Q ' _i+1, Q ' _i+2for the reference mark after translation, R ₀, R ₁, R ₂, R ₃for equation p (the u)=R of B-spline Curve ₀u ³+ R ₁u ²+ R ₂u+R ₃the coefficient of (0≤u≤1).

Further preferably, described smart interpolated point computing module comprises and recursion interpolation computing module and pre-interpolation computing module, wherein:

The starting condition of described pre-interpolation computing module for calculating according to the interpolation of SPL calculation of parameter, its starting condition is:

$\left\{\begin{array}{c}{p}_0=R_3\\ \mathrm{\Δ}{p}_0=R_0\mathrm{\Δ}{u}^3+R_1\mathrm{\Δ}{u}^2+R_2\mathrm{\Δu}\\ {\mathrm{\Δ}}^2{p}_0=6R_0\mathrm{\Δ}{u}^3+2R_1\mathrm{\Δ}{u}^2\\ {\mathrm{\Δ}}^3{p}_0=6R_0\mathrm{\Δ}{u}^3\end{array}\right.$

Described recursion interpolation computing module is for calculating smart interpolated point according to starting condition recursion, and recursion formula is:

$\left\{\begin{array}{c}{p}_{m+1}=p_m+\mathrm{\Δ}{p}_m\\ \mathrm{\Δ}{p}_m=\mathrm{\Δ}{p}_m-1+{\mathrm{\Δ}}^2{p}_{m-1}\\ {\mathrm{\Δ}}^2{p}_m-1={\mathrm{\Δ}}^2{p}_m-2+{\mathrm{\Δ}}^3{P}_{m-2}\\ {\mathrm{\Δ}}^3{P}_{m-2}=6R_0\mathrm{\Δ}{u}^3\end{array}\right.$

Wherein said Δ u is the step-length that recursion interpolation is calculated.

Further preferably, described floating-point operation module comprises integer calculating sub module, Floating-point Computation submodule and floating-point integer conversion submodule, wherein:

Described integer calculating sub module forms by a multiplication unit and one plus-minus is unit cascaded, for completing once to take advantage of to add or take advantage of according to the computations of input within a clock period, subtract computing, integer calculating sub module is also supported independently multiplication, signed magnitude arithmetic(al) simultaneously;

Described Floating-point Computation submodule is by a single-precision floating point multiplication unit and single-precision floating point plus-minus method unit cascaded composition, also comprise an independently single-precision floating point divider, according to the computations of input, within the corresponding instruction cycle, complete the multiplication of corresponding floating data, addition or multiply-add operation;

Described floating-point integer conversion submodule is responsible for the mutual conversion of floating number and shaping data, when shaping data enter recursion calculating, need to be converted to floating data, to promote data precision; And when the data that calculate need to be sent into pulse sending module, need to be converted to shaping data, so that pulse sending module processing.

Further preferably, during described Floating-point Computation submodule for taking advantage of the disposal route that adds instruction and adopt 3 level production lines, when needs carry out repeatedly the floating point multiplication addition computing of single precision, within first instruction cycle, reading command 1; When entering for the second instruction cycle, read in the instruction 2 of second instruction cycle, meanwhile, the operand in first cycle starts to carry out multiplying according to instruction 1; When the 3rd instruction cycle arrives, repeat step above, now, the operand 1 of first instruction cycle starts to enter additive operation, and the operand 2 of second instruction cycle enters multiplying, the like, multiply-add operation loops.

Preferably,

In general, the above technical scheme of conceiving by the present invention compared with prior art, can obtain following beneficial effect:

The invention has the beneficial effects as follows:

(1) the present invention adopts reference mark after optimization to carry out the calculation of parameter of B-spline curves, calculates simply, and speed is fast;

(2) the present invention adopts recursive operation to calculate smart interpolation data point, and Interpolation Process, except precomputation comprises multiplying, is additive operation, and counting yield is higher;

(3) the present invention adopts two DPRAM to adopt ping-pongs to carry out reading and writing data, avoids waiting for that new interpolation data writes fashionable time delay again;

(4) the present invention adopts stream line operation mode and the conversion of floating-point integer to calculate, and has effectively promoted the speed of calculating.

Accompanying drawing explanation

Fig. 1 is the one-piece construction schematic diagram of the hardware interpolator of the B-spline Curve based on FPGA in the present invention;

Fig. 2 is the Interpolation Process schematic diagram that the present invention is based on the B-spline Curve of FPGA;

Fig. 3 is single shaft SPL essence interpolated point calculation flow chart in one embodiment of the present invention;

Fig. 4 is floating-point operation modular structure schematic diagram in one embodiment of the present invention;

Fig. 5 is 3 level production line schematic diagram in one embodiment of the present invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.In addition,, in each embodiment of described the present invention, involved technical characterictic just can combine mutually as long as do not form each other conflict.

The present invention proposes a kind of hardware interpolator of the B-spline Curve based on FPGA, utilizes the flexible in programming of FPGA to realize the data interaction of FPGA and ARM, the calculating of SPL parameter system, the calculating of SPL interpolated point, and the output of pulse signal.Adopt recursive algorithm simultaneously, only need carry out multiplication calculating in the pre-interpolation stage, greatly accelerate interpolated point computing velocity, and adopt floating-point integer data mutually to change, effectively reduce floating-point operation amount, not only promoted arithmetic speed, and can effectively save logical resource.

Fig. 1 is the one-piece construction schematic diagram of the hardware interpolator of the B-spline Curve based on FPGA in the present invention, described hardware interpolator mainly comprises ARM/FPGA interface module, SPL parameter calculating module, smart interpolated point computing module, pulse sending module, floating-point operation module.ARM/FPGA interface module writes dual port RAM by SPL reference mark data, after interpolation starts, SPL parameter calculating module is read in reference mark data, calculate the coefficient of SPL, then smart interpolation computing module carries out the calculating of each smart interpolated point according to the SPL information calculating, and finally the pick feed amount obtaining is sent into the output of pulse sending module.Data in above-mentioned computation process and instruction meeting are sent into floating-point operation module and are calculated, and then obtain result of calculation.

Fig. 2 is the overall Interpolation Process schematic diagram that the present invention is based on the B-spline Curve of FPGA.After program powers on, carry out the initialization of some initial parameters, after having parameter of curve to write, start to carry out the curve coefficients calculating of each axle, then calculate the smart interpolated point of each axle under the different smart interpolation time, complete after the calculating of each axle under this interpolation cycle, by pick feed amount data write pulse sending module, carry out the output of axle pulse information.

Fig. 3 is the SPL Interpolation Process schematic diagram of single axle.Carry out after interpolation starting, first need to be write by ARM the variable parameter of u, on this section of curve, calculative smart interpolation is counted; After receiving the reference mark of new rough interpolation data, carry out the reference mark coordinate system translation of rough interpolation data, to simplify SPL coefficient calculations process; When carrying out curve coefficients calculating, can first carry out the calculating of integer part, then integer data-switching is become floating number to calculate, obtain the coefficient of last SPL; Finally according to hereinafter listed interpolation recursion formula, complete the calculating of each smart interpolated point on this section of curve; When having calculated after all smart interpolated points, wait until the input at new reference mark, to start the curve calculation of a new round.

Introducing modules concrete function below realizes:

(1) ARM/FPGA interface module

ARM/FPGA interface module mainly completes the transmission of SPL reference mark data, when arriving with the data write time of ARM agreement, FPGA notifies the ARM can data writing by look-at-me, now ARM writes a DPRAM by data and carries out the storage of data, and upper once write data time arrive in, data write second DPRAM, and two DPRAM accept the interpolated point data that ARM sends in turn.When same SPL parameter calculating module reads SPL reference mark data message, be also from two DPRAM, to carry out reading of data in turn successively.

(2) SPL parameter calculating module

The following p of equation (the u)=R of B-spline Curve ₀u ³+ R ₁u ²+ R ₂u+R ₃(0≤u≤1).R in formula ₀, R ₁, R ₂, R ₃be without guiding principle amount constant.

Suppose that the rough interpolation point sequence in the B-spline Curve of certain section of unknown parameter of an axle is P _i(i=1,2,3..n), this section of curve is Q according to the Control point of rough interpolation dot generation _i(i=0,1,2,3..n, n+1).Get with P _iand P _i+1for head and the tail point, by reference mark Q _i-1, Q _i, Q _i+1and Q _i+2the segment of curve of controlling is calculated curve.

Due to P _iand P _i+1t is relevant to interpolation time parameter, and SPL is represented by local parameter u, need to join transformation of variable.Make t=uT (0≤u≤1, T is the rough interpolation cycle), by splines matrix of coefficients, the matrix expression of the smart interpolated point on can this section of curve is:

$p_m\left(t\right)=\frac{1}{6}\×\left[\begin{array}{cccc}{\left(\frac{t}{T}\right)}^3& {\left(\frac{t}{T}\right)}^2& \left(\frac{t}{T}\right)& 1\end{array}\right]\left[\begin{array}{cccc}-1& 3& -3& 1\\ 3& -6& 3& 0\\ -3& 0& 3& 0\\ 1& 4& 1& 0\end{array}\right]\left[\begin{array}{c}{Q}_{i-1}\\ Q_i\\ Q_{i+1}\\ Q_{i+2}\end{array}\right](0\≤t\≤T)$

Wherein, the smart interpolation m that counts is relevant with the value interval of time parameter t.Carry out after coordinate transform, curve variable is become to integer data t from floating-point decimal u, can reduce like this floating-point operation amount, speed-up computation process.

SPL parameter calculating module can comprise coordinate translation module and parameter of curve computing module, and wherein coordinate translation module is carried out coordinate translation by reference mark, makes Q _i-1move to initial point place, the reference mark after translation is 0, Q ' _i, Q ' _i+1, Q ' _i+2and the SPL shape that it is controlled can't change, because pulse sending module is to carry out pulse transmission according to the difference of adjacent two smart interpolated points, can't affect like this processing of SPL, and the parameter calculation procedure of curve after translation is simpler, computation process is more quick, can improve the precision of calculating simultaneously, also can more save the logical resource of FPGA.

Parameter of curve computing module is for calculating the coefficient of the SPL after translation according to the reference mark after translation, accounting equation is as follows:

$\left\{\begin{array}{c}{R}_3=\frac{4{Q^{\′}}_i+{Q^{\′}}_{i+1}}{6}\\ R_2=\frac{{Q^{\′}}_{i+1}}{2T}\\ R_1=\frac{{Q^{\′}}_{i+1}-2{Q^{\′}}_i}{{2T}^2}\\ R_0=\frac{{Q^{\′}}_{i+2}+3{Q^{\′}}_i-3{Q^{\′}}_{i+1}}{{6T}^3}\end{array}\right.$

(3) smart interpolated point computing module

After the parameter of SPL is determined, data are stored among inner register, open inner timer simultaneously, and timer produces timing signal according to the smart interpolation cycle arranging; Complete after calculation of parameter, interpolation process control module can calculate respectively the pick feed amount of each axle after timing signal arrives, and has all calculated in the rear pulse generating module simultaneously each axis data being sent; Interpolation process control module has calculated the data point that will wait for next section of SPL after all smart interpolated point in the rough interpolation cycle.The state transition graph of INTERPOLATION CONTROL OF PULSE module is illustrated in fig. 3 shown below.

By the parametric equation of SPL, can obtain the recursion formula that interpolation is calculated, known p (u)=R ₀u ³+ R ₁u ²+ R ₂u+R ₃(0≤u≤1),

?

Δp(u)＝p(u+Δu)-p(u)

＝3R ₀Δuu ²+(3R ₀Δu ²+2R ₁Δu)u+(R ₀Δu ³+R ₁Δu ²+R ₂Δu)

Δ ²p(u)＝Δp(u+Δu)-Δp(u)＝6R ₀Δu ²u+6R ₀Δu ³+2R ₁Δu ²

Δ ³p(u)＝Δp ²(u+Δu)-Δp ²(u)＝6R ₀Δu ³

Make p _m=P (u _m), u _m=m Δ u, can obtain recursion formula

$\left\{\begin{array}{c}{p}_{m+1}=p_m+\mathrm{\Δ}{p}_m\\ \mathrm{\Δ}{p}_m=\mathrm{\Δ}{p}_m-1+{\mathrm{\Δ}}^2{p}_{m-1}\\ {\mathrm{\Δ}}^2{p}_m-1={\mathrm{\Δ}}^2{p}_m-2+{\mathrm{\Δ}}^3{P}_{m-2}\\ {\mathrm{\Δ}}^3{P}_{m-2}=6R_0\mathrm{\Δ}{u}^3\end{array}\right.$

The calculating of each single shaft is according to interpolation the recursive calculative formula, and wherein pre-interpolation computing formula is

The starting condition that interpolation is calculated is (m=0),

$\left\{\begin{array}{c}{p}_0=R_3\\ \mathrm{\Δ}{p}_0=R_0\mathrm{\Δ}{u}^3+R_1\mathrm{\Δ}{u}^2+R_2\mathrm{\Δu}\\ {\mathrm{\Δ}}^2{p}_0=6R_0\mathrm{\Δ}{u}^3+2R_1\mathrm{\Δ}{u}^2\\ {\mathrm{\Δ}}^3{p}_0=6R_0\mathrm{\Δ}{u}^3\end{array}\right.$

From smart interpolated point the recursive calculative formula above, when the coefficient calculations essence interpolated point according to SPL, be divided into two steps.In smart interpolated point computing module, need to be designed with so pre-interpolation computing module and recursion and calculate interpolation module, the starting condition that completes interpolation by pre-interpolation computing module is calculated, and recursion computing module completes the recursion of smart interpolated point and calculates.

Carry out after the conversion of parameter of curve, recursion formula calculates according to time parameter t, after the every calculating once of smart interpolated point of single shaft, the value of t can increase accordingly, when the value of t reaches rough interpolation periodic quantity T, u also reaches 1, and the now interpolation of this section of curve has been calculated, and then waits for that new curve control point data carry out the smart interpolation of next section of curve and calculate.

(4) the core calculations module that floating-point operation module is system, it has been responsible for various integer calculating, Floating-point Computation and Data Format Transform in Interpolation Process.As Fig. 4, floating-point operation module comprises integer calculating sub module, Floating-point Computation submodule and floating-point integer conversion submodule.In floating-point operation module, integer calculating sub module and Floating-point Computation submodule have independently order set, and what they can walk abreast operates, and convenient stream line operation in Interpolation Process improves arithmetic speed.

Integer calculating sub module adopts a 32bit multiplication unit and a 32bit to add and subtract unit cascaded, can be within a clock period according to the computations of input, completing taking advantage of of integer data adds or takes advantage of and subtract computing, integer calculating sub module is also supported independently multiplication, signed magnitude arithmetic(al) simultaneously.

Floating-point Computation submodule adopt a single-precision floating point multiplication unit and a single-precision floating point plus-minus method unit cascaded, single-precision floating point divider is for independently.According to the computations of input, within the corresponding instruction cycle, complete multiplication, addition or the multiply-add operation of corresponding floating data.

According to the difference of computations, operand is admitted to different arithmetic elements and calculates, and then exports result of calculation.

Floating-point integer conversion submodule is responsible for the mutual conversion of floating number and shaping data, when shaping data enter recursion calculating, need to be converted to floating data, to promote data precision; And when the data that calculate need to be sent into pulse sending module, need to be converted to shaping data, so that pulse sending module processing.

The floating point multiplication addition computing of single precision is the maximum calculating of frequency of utilization in cubic spline interpolation algorithm, therefore when design floating-point operation submodule for taking advantage of the disposal route that adds instruction and adopt 3 level production lines, adopt the design of streamline to improve the efficiency of multiply-add operation, take advantage of and add instruction pipelining schematic diagram as shown in Figure 5.

When needs carry out repeatedly the floating point multiplication addition computing of single precision, within first instruction cycle, reading command 1; When entering for the second instruction cycle, read in the instruction 2 of second instruction cycle, meanwhile, the operand in first cycle starts to carry out multiplying according to instruction 1; When the 3rd instruction cycle arrives, repeat step above, and now, the operand 1 of first instruction cycle starts to enter additive operation, the operand 2 of second instruction cycle enters multiplying ..., according to such beat, multiply-add operation loops.In an instruction, multiply-add operation is that order is carried out, but macroscopical comultiplication and addition can be regarded parallel computation as, like this can more effective raising counting yield.

Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.

Claims (6)

1. one kind based on field programmable gate array (Field-Programmable Gate Array, FPGA) B-spline Curve hardware interpolator, it is characterized in that, comprise ARM/FPGA data interaction module, SPL parameter calculating module, smart interpolated point computing module, pulse sending module and floating-point operation module, wherein:

Described ARM/FPGA data interaction module, for receive the reference mark data of B-spline Curve from ARM, and is deposited in random access memory (Random Access Memory, RAM);

Described SPL parameter calculating module, for read the reference mark data of B-spline Curve from described RAM, and calculates the coefficient of B-spline Curve;

Described smart interpolated point computing module, for obtain the coefficient of B-spline Curve from SPL parameter calculating module, first carries out the precomputation before recursion, then calculates the interpolated point data of each smart interpolation cycle;

Described floating-point operation module, for carrying out interpolation computation process at smart interpolated point computing module, completes integer and calculates, Floating-point Computation and Data Format Transform;

Described pulse sending module, for receiving the interpolated point data of each smart interpolation cycle of smart interpolated point computing module output, and according to the interpolation pulsed quantity of the each smart interpolation cycle of described interpolated point data output.

2. hardware interpolator according to claim 1, it is characterized in that, described RAM is dual port RAM, carry out ping-pong operation, in ARM/FPGA data interaction module, the reference mark data of B-spline curves are write to a RAM in dual port RAM constantly, the reference mark data that read B-spline curves during another RAM from dual port RAM of SPL parameter calculating module, two block RAMs in dual port RAM carry out read-write operation in turn.

3. hardware interpolator according to claim 1 and 2, is characterized in that, described SPL parameter calculating module comprises coordinate translation module and parameter of curve computing module, wherein:

Described coordinate translation module, for coordinate translation is carried out in the reference mark of B-spline Curve, moves to coordinate system on first reference mark;

Described parameter of curve computing module is for calculating SPL parameter according to the reference mark after balance, and the computing formula of SPL parameter is:

$\left\{\begin{array}{c}{R}_3=\frac{4{Q^{\′}}_i+{Q^{\′}}_{i+1}}{6}\\ R_2=\frac{{Q^{\′}}_{i+1}}{2T}\\ R_1=\frac{{Q^{\′}}_{i+1}-2{Q^{\′}}_i}{{2T}^2}\\ R_0=\frac{{Q^{\′}}_{i+2}+3{Q^{\′}}_i-3{Q^{\′}}_{i+1}}{{6T}^3}\end{array}\right.$

Wherein, 0, Q ' _i, Q ' _i+1, Q ' _i+2for the reference mark after translation, R ₀, R ₁, R ₂, R ₃for equation p (the u)=R of B-spline Curve ₀u ³+ R ₁u ²+ R ₂u+R ₃the coefficient of (0≤u≤1).

4. according to the hardware interpolator described in claim 1-3 any one, it is characterized in that, smart interpolated point computing module comprises and recursion interpolation computing module and pre-interpolation computing module, wherein:

The starting condition of described pre-interpolation computing module for calculating according to the interpolation of SPL calculation of parameter, its starting condition is:

$\left\{\begin{array}{c}{p}_0=R_3\\ \mathrm{\Δ}{p}_0=R_0\mathrm{\Δ}{u}^3+R_1\mathrm{\Δ}{u}^2+R_2\mathrm{\Δu}\\ {\mathrm{\Δ}}^2{p}_0=6R_0\mathrm{\Δ}{u}^3+2R_1\mathrm{\Δ}{u}^2\\ {\mathrm{\Δ}}^3{p}_0=6R_0\mathrm{\Δ}{u}^3\end{array}\right.$

Described recursion interpolation computing module is for calculating smart interpolated point according to starting condition recursion, and recursion formula is:

$\left\{\begin{array}{c}{p}_{m+1}=p_m+\mathrm{\Δ}{p}_m\\ \mathrm{\Δ}{p}_m=\mathrm{\Δ}{p}_m-1+{\mathrm{\Δ}}^2{p}_{m-1}\\ {\mathrm{\Δ}}^2{p}_m-1={\mathrm{\Δ}}^2{p}_m-2+{\mathrm{\Δ}}^3{P}_{m-2}\\ {\mathrm{\Δ}}^3{P}_{m-2}=6R_0\mathrm{\Δ}{u}^3\end{array}\right.$

Wherein said Δ u is the step-length that recursion interpolation is calculated.

5. according to the hardware interpolator described in claim 1-4 any one, it is characterized in that, described floating-point operation module comprises integer calculating sub module, Floating-point Computation submodule and floating-point integer conversion submodule, wherein:

Described integer calculating sub module forms by a multiplication unit and one plus-minus is unit cascaded, for completing once to take advantage of to add or take advantage of according to the computations of input within a clock period, subtract computing, integer calculating sub module is also supported independently multiplication, signed magnitude arithmetic(al) simultaneously;

Described Floating-point Computation submodule is by a single-precision floating point multiplication unit and single-precision floating point plus-minus method unit cascaded composition, also comprise an independently single-precision floating point divider, according to the computations of input, within the corresponding instruction cycle, complete the multiplication of corresponding floating data, addition or multiply-add operation;

Described floating-point integer conversion submodule is responsible for the mutual conversion of floating number and shaping data, when shaping data enter recursion calculating, need to be converted to floating data, to promote data precision; And when the data that calculate need to be sent into pulse sending module, need to be converted to shaping data, so that pulse sending module processing.

6. according to the hardware interpolator described in claim 1-5 any one, it is characterized in that, during described Floating-point Computation submodule for taking advantage of the disposal route that adds instruction and adopt 3 level production lines, when needs carry out repeatedly the floating point multiplication addition computing of single precision, within first instruction cycle, reading command 1; When entering for the second instruction cycle, read in the instruction 2 of second instruction cycle, meanwhile, the operand in first cycle starts to carry out multiplying according to instruction 1; When the 3rd instruction cycle arrives, repeat step above, now, the operand 1 of first instruction cycle starts to enter additive operation, and the operand 2 of second instruction cycle enters multiplying, the like, multiply-add operation loops.

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