CN103730881A - Power supply isolation circuit and method - Google Patents
Power supply isolation circuit and method Download PDFInfo
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- CN103730881A CN103730881A CN201310754106.6A CN201310754106A CN103730881A CN 103730881 A CN103730881 A CN 103730881A CN 201310754106 A CN201310754106 A CN 201310754106A CN 103730881 A CN103730881 A CN 103730881A
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Abstract
The embodiment of the invention provides a power supply isolation circuit and method, and relates to the field of power supplies. The complexity degree of the circuit can be lowered, a multiplexed output power supply can be effectively isolated under the abnormal conditions that short circuits happen to the inner portion of the power supply in the circuit, and the circuit is reliably protected. The method comprises the steps that when the abnormal condition that the short circuits happen to the inner portion of the power supply in the circuit happens, and the internal voltage of the circuit is lower than the external voltage of the circuit, a field-effect tube in the isolation circuit is cut off, and therefore the power supply and an output bus are blocked. The power supply isolation circuit and method are used for isolating the power supply.
Description
Technical field
The present invention relates to field of power supplies, relate in particular to a kind of power isolation circuit and method.
Background technology
The way of outputs that adopt multiple power module concurrent workings in current power-supply system more, for fear of the normal work that affects other modules of power-supply system due to one of them module output abnormality, oring mosfet(or the door field effect transistor of adopting in circuit more) each power module is isolated.
In prior art, adopt isolated with comparator more between power supply and output bus, or employing is isolated with the circuit of other field effect transistor.
State in realization in the process of each power module isolation, inventor finds that in prior art, at least there are the following problems:
At employing comparator, carry out in the process of isolated from power, the control logic relative complex that its whole circuit need to be used, and there is the situation of mistake upset in comparator than being easier to be interfered, and adopt with other of field effect transistor compared with the scheme of complicated circuit in, due to the different size of power supply, the feeder ear of the buffer circuit that each power supply connects can not share, and need to increase extra winding, thereby increased the coiling difficulty of circuit cost and transformer for the power supply of multichannel output.
Summary of the invention
Embodiments of the invention provide a kind of power isolation circuit and method, can reduce the complexity of circuit, and at circuit, occur the effective power supply that must isolate multichannel output under the abnormal conditions such as power supply internal short-circuit, to circuit, provide reliably protecting.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, a kind of power isolation circuit is provided, comprise the first resistance, the second resistance, the first diode, the second diode, mirror current source and field effect transistor, it is characterized in that, described the first diode is connected with the source electrode of described field effect transistor, and the second diode is connected with the drain electrode of described field effect transistor;
Described the first diode is connected with the first emitter of described mirror current source, and described the second diode is connected with the second emitter of described mirror current source;
Described the first resistance is connected with the first collector electrode of described mirror current source, and described the second resistance is connected with the second collector electrode of described mirror current source.
In conjunction with first aspect, in the possible implementation of the first, described circuit also comprises:
At least two described field effect transistor are carried out to parallel connection to meet power requirement.
In conjunction with first aspect, in the possible implementation of the second, described mirror current source comprises:
Described mirror current source is connected and is formed by the base stage of NPN type triode; Or
Described mirror current source is connected and is formed by the base stage of positive-negative-positive triode.
In conjunction with first aspect, in the third possible implementation, described circuit is built in power module.
Second aspect, provides a kind of isolated from power method, is applied to circuit described in first aspect, and the source electrode of the field effect transistor of described circuit is connected with power supply, and the drain electrode of described field effect transistor is connected with output bus, and described method comprises:
When builtin voltage is during higher than external voltage, the first triode conducting of described mirror current source, the second triode cut-off of described mirror current source, described field effect transistor conducting, described power supply outputs to electric current on described output bus, the source voltage of wherein said field effect transistor is builtin voltage, and the drain voltage of described field effect transistor is external voltage;
When builtin voltage is during lower than external voltage, the first triode cut-off of described mirror current source, the second triode conducting of described mirror current source, described field effect transistor cut-off, described power supply and the disconnection of described output bus.
The embodiment of the present invention provides a kind of power isolation circuit and method; if while there is the unusual conditions such as short circuit in power supply inside; when inside circuit voltage is during lower than external voltage; field effect transistor cut-off in this buffer circuit; thereby blocking-up power supply and output bus; this circuit can reduce the complexity of circuit, and under the abnormal conditions such as short circuit the effective power supply that must isolate multichannel output, to circuit, provide reliably protecting.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
A kind of power isolation circuit structural representation one that Fig. 1 provides for the embodiment of the present invention;
The schematic flow sheet of a kind of isolated from power method that Fig. 2 provides for the embodiment of the present invention;
A kind of power isolation circuit structural representation two that Fig. 3 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of power isolation circuit 01, as shown in Figure 1, this circuit 01 comprises the first resistance 011, the second resistance 012, the first diode 013, the second diode 014, mirror current source 015 and a field effect transistor 016, it is characterized in that, the first diode 013 is connected with the source electrode of field effect transistor 016, and the second diode 014 is connected with the drain electrode of field effect transistor 016;
The first diode 013 is connected with the first emitter e 1 of mirror current source 015, and the second diode 014 is connected with the second emitter e 2 of mirror current source;
The first resistance 011 is connected with the first collector electrode c1 of mirror current source 015, and the second resistance 012 is connected with the second collector electrode c2 of mirror current source 015.
Wherein, as shown in Figure 1, diode in this circuit can be two integrated diodes, first diode 013 one end is connected with the source electrode utmost point of field effect transistor 016, and be connected with the power supply in circuit, and the second diode 014 is connected with the drain electrode of field effect transistor 016, and be connected with the output bus in circuit;
Can be described as builtin voltage with the voltage of the source electrode of the field effect transistor in circuit, and the voltage of the drain electrode of field effect transistor in circuit can be referred to as external voltage;
Mirror current source in foregoing circuit can be connected and be formed by the base stage of two NPN type triodes, or is connected and is formed by the base stage of two positive-negative-positive triodes;
When in the circuit at multiple power works, can suitably increase the number in parallel of above-mentioned field effect transistor to adapt to the power needs of multiple power supply concurrent workings;
Foregoing circuit can be placed between power supply and output bus, foregoing circuit can also be built in to power module inside.
The embodiment of the present invention provides a kind of power isolation circuit; if while there is the unusual conditions such as short circuit in power supply inside; when inside circuit voltage is during lower than external voltage; field effect transistor cut-off in this buffer circuit; thereby blocking-up power supply and output bus; this circuit can reduce the complexity of circuit, and under the abnormal conditions such as short circuit the effective power supply that must isolate multichannel output, to circuit, provide reliably protecting.
The embodiment of the present invention provides a kind of isolated from power method, and the method is applied to a kind of power isolation circuit in Fig. 1 that the embodiment of the present invention provides, and as shown in Figure 2, the method comprises:
S101, when builtin voltage is during higher than external voltage, the first triode conducting of mirror current source, the second triode cut-off of mirror current source, field effect transistor conducting, power supply outputs to electric current on output bus, wherein the source voltage of field effect transistor is builtin voltage, and the drain voltage of field effect transistor is external voltage.
Exemplary, in circuit as shown in Figure 1, can realize by the following method:
By ORING MOSFET(Q1 field effect transistor relatively) builtin voltage (DC terminal voltage) control opening of Q1 or disconnect with the height of the base voltage of external voltage (DC BUS terminal voltage) and the middle triode of mirror current source (Q2 mirror current source);
Concrete, can realize by following workflow:
As shown in Figure 1 in circuit, b1 end is identical with b2 end points position, when DC terminal voltage is greater than DC BUS terminal voltage, e1 in Q2 and b1 end will be switched on, e2 in Q2 and b2 end will be cut off simultaneously, and now in figure, ORING_DR end is low level, and in figure, ORING_VCC end is high level, in figure, Q1 will be switched on, thereby power supply is rectified and often outputed on output bus by DCBUS.
S102, when builtin voltage is during lower than external voltage, the first triode cut-off of mirror current source, the second triode conducting of mirror current source, field effect transistor cut-off, power supply and output bus disconnection.
Exemplary, circuit as shown in Figure 1, can realize by following flow process:
When DC terminal voltage is less than DC BUS terminal voltage, e1 in Q2 and b1 end will be cut off, e2 in Q2 and b2 end will be switched on simultaneously, now in figure, ORING_DR end is high level, and ORING_VCC end is high level in figure, in figure, Q1 will be cut off, thereby by the output of power supply and output bus isolation.
Wherein, when power supply exists that output voltage is counter fills with, for example, under multiple power module parallel operation conditions of work, there is internal short circuit fault in one of them power supply, causes occurring pressure reduction inside and outside ORING MOS.During high voltage output, the anti-voltage of filling with is also higher.And the first diode and the second diode can blocking voltage is counter be filled with, thereby protected triode Q2, therefore this circuit is not only suitable for low pressure output and is also applicable to high voltage output simultaneously.
When Power Management Design is multichannel output, as shown in Figure 3, for example there is the output of 12V/5V two-way, access respectively above-mentioned buffer circuit can to each power supply, now because this ORING drive circuit is reference take ground, each buffer circuit is simultaneously common uses an above-mentioned ORING_VCC, has avoided the power supply of different size need to use the problem of the control complexity that the buffer circuit of different size brings, thereby has not only guaranteed the reliable control of ORING_MOSFET but also reduced the complexity of circuit.
In addition, when circuit needs high power requirement, can adopt and use multiple above-mentioned field effect transistor to carry out parallel connection, thereby meet the more high-power requirement of circuit.
The embodiment of the present invention provides a kind of isolated from power method; if while there is the unusual conditions such as short circuit in power supply inside; when inside circuit voltage is during lower than external voltage; field effect transistor cut-off in this buffer circuit; thereby blocking-up power supply and output bus; this circuit can reduce the complexity of circuit, and under the abnormal conditions such as short circuit the effective power supply that must isolate multichannel output, to circuit, provide reliably protecting.
Through the above description of the embodiments, those skilled in the art can be well understood to, for convenience and simplicity of description, only with the division of above-mentioned each functional module, be illustrated, in practical application, can above-mentioned functions be distributed and by different functional modules, completed as required, the internal structure that is about to device be divided into different functional modules, to complete all or part of function described above.The system of foregoing description, the specific works process of device and unit, can, with reference to the corresponding process in preceding method embodiment, not repeat them here.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (5)
1. a power isolation circuit, comprise the first resistance, the second resistance, the first diode, the second diode, mirror current source and field effect transistor, it is characterized in that, described the first diode is connected with the source electrode of described field effect transistor, and the second diode is connected with the drain electrode of described field effect transistor;
Described the first diode is connected with the first emitter of described mirror current source, and described the second diode is connected with the second emitter of described mirror current source;
Described the first resistance is connected with the first collector electrode of described mirror current source, and described the second resistance is connected with the second collector electrode of described mirror current source.
2. circuit according to claim 1, is characterized in that, described circuit also comprises:
At least two described field effect transistor are carried out to parallel connection to meet power requirement.
3. circuit according to claim 1, is characterized in that, described mirror current source comprises:
Described mirror current source is connected and is formed by the base stage of NPN type triode; Or
Described mirror current source is connected and is formed by the base stage of positive-negative-positive triode.
4. circuit according to claim 1, is characterized in that, described circuit is built in power module.
5. an isolated from power method, is characterized in that, is applied to circuit described in claim 1, and the source electrode of the field effect transistor of described circuit is connected with power supply, and the drain electrode of described field effect transistor is connected with output bus, and described method comprises:
When builtin voltage is during higher than external voltage, the first triode conducting of described mirror current source, the second triode cut-off of described mirror current source, described field effect transistor conducting, described power supply outputs to electric current on described output bus, the source voltage of wherein said field effect transistor is builtin voltage, and the drain voltage of described field effect transistor is external voltage;
When builtin voltage is during lower than external voltage, the first triode cut-off of described mirror current source, the second triode conducting of described mirror current source, described field effect transistor cut-off, described power supply and the disconnection of described output bus.
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| CN201310754106.6A CN103730881B (en) | 2013-12-31 | 2013-12-31 | A kind of power isolation circuit and method |
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| CN201310754106.6A CN103730881B (en) | 2013-12-31 | 2013-12-31 | A kind of power isolation circuit and method |
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| CN103730881A true CN103730881A (en) | 2014-04-16 |
| CN103730881B CN103730881B (en) | 2016-09-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001309203A (en) * | 2000-04-24 | 2001-11-02 | New Japan Radio Co Ltd | Synchronizing separator circuit |
| CN101682261A (en) * | 2007-05-22 | 2010-03-24 | 松下电器产业株式会社 | Switching power supply device |
| US20120248864A1 (en) * | 2011-02-28 | 2012-10-04 | General Electric Company, A New York Corporation | System and Method for Operating Inverters |
| CN102970800A (en) * | 2012-11-20 | 2013-03-13 | 顺德职业技术学院 | LED (Light Emitting Diode) driving circuit |
-
2013
- 2013-12-31 CN CN201310754106.6A patent/CN103730881B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001309203A (en) * | 2000-04-24 | 2001-11-02 | New Japan Radio Co Ltd | Synchronizing separator circuit |
| CN101682261A (en) * | 2007-05-22 | 2010-03-24 | 松下电器产业株式会社 | Switching power supply device |
| US20120248864A1 (en) * | 2011-02-28 | 2012-10-04 | General Electric Company, A New York Corporation | System and Method for Operating Inverters |
| CN102970800A (en) * | 2012-11-20 | 2013-03-13 | 顺德职业技术学院 | LED (Light Emitting Diode) driving circuit |
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| CN103730881B (en) | 2016-09-28 |
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Effective date of registration: 20211111 Address after: 518043 No. 01, 39th floor, building a, antuoshan headquarters building, No. 33, antuoshan Sixth Road, Xiang'an community, Xiangmihu street, Futian District, Shenzhen, Guangdong Province Patentee after: Huawei Digital Energy Technology Co., Ltd Address before: 518129 Huawei headquarters office building, Bantian, Longgang District, Shenzhen, Guangdong Patentee before: Huawei Technology Co., Ltd |
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