CN103701325B - A kind of capacitance voltage control circuit for half-bridge three-level direct current converter - Google Patents

Abstract

The invention discloses a kind of capacitance voltage control circuit for half-bridge three-level direct current converter, comprise output voltage regulator, capacitance voltage regulator, derided capacitors voltage regulator, capacitance voltage control circuit and derided capacitors voltage-equalizing control circuit, the first rest-set flip-flop and the second rest-set flip-flop；Output voltage regulator and capacitance voltage regulator are connected with derided capacitors voltage-equalizing control circuit through capacitance voltage control circuit respectively, derided capacitors voltage regulator connects derided capacitors voltage-equalizing control circuit, four outfans of derided capacitors voltage-equalizing control circuit are corresponding with four inputs of above-mentioned 2 rest-set flip-flops respectively to be connected, and the outfan output switch pipe of 2 triggers drives signal.The present invention corrects the bias-pressure phenomenon that half-bridge three-level direct current converter causes due to parameter unbalance.

Description

A kind of capacitance voltage control circuit for half-bridge three-level direct current converter

Technical field

The present invention relates to a kind of capacitance voltage control circuit for half-bridge three-level direct current converter, belong to power Electronics conversion field.

Background technology

It is low that three level (Three level, TL) DC converter has main power tube voltage stress, inputs and exports filter The advantages such as ripple device is little, are therefore highly suitable to be applied for the high voltage inputs such as subway rail car accessory power supply, ship power supply Power conversion occasion.Wherein, half-bridge TL DC converter is possible not only to realize the isolation of former secondary, the most easily In realizing the Sofe Switch of primary side switch pipe, reduce the switching loss of changer, improve conversion efficiency, so half-bridge TL DC converter is the most all widely studied.

Half-bridge TL DC converter replaces a switching tube with two switching tube series connection, thus by every switch The voltage stress of pipe reduces to input voltage V_inHalf.But the characteristic of be serially connected two switching tubes and driving Dynamic circuit characteristic can not be completely the same, and when two switching tubes turn off, the voltage that they are undertaken may not wait. Half-bridge three-level direct current converter with clamp diode can ensure that the voltage stress that two switching tubes bear is equal For V_in/ 2, but changer normally works is that two switching tubes of outside must be prior to two corresponding, the inside Switching tube turns off.Half-bridge three-level direct current converter with striding capacitance has decoupled the switch of two switching tubes Journey, two switching tubes of outside and two switching tubes of the inside complementation conducting, the switching tube of outside and the inside respectively The switching sequence of switching tube do not limit.But, when input derided capacitors and striding capacitance voltage not etc. time, There is switching capacity mode, loop produces the biggest transient current and forces clamp diode conducting equilibrium electric capacity electricity Pressure, easily causes clamp diode and damages.

The four switch half-bridge TL DC converters without clamp diode and striding capacitance are substantially two brachium pontis strings Connection, derided capacitors can clamp primary side switch pipe, and switching tube can realize Sofe Switch, and circuit structure is simple, can By property high, reduce the conduction loss that clamp diode brings, it is to avoid the reliability that diode is likely to occur is asked Topic.But in real work, owing to the time delay of driving circuits and the characteristic of main power tube are inconsistent Etc. factor cause positive and negative half period dutycycle not wait and time of afterflow, cause changer derided capacitors and Capacitance voltage differs and is set to V_in/ 2, i.e. there is biasing problem.If but input derided capacitors voltage is not Equal and capacitance voltage is not equal to V_in/ 2, then primary side switch pipe and the voltage of secondary commutation diode Stress increases, and affects the reliably working of circuit.It is thus desirable to searching control strategy, realize inputting derided capacitors All pressure and capacitance voltage is equal to the purpose of input voltage half, it is ensured that the reliably working of changer.

Summary of the invention

In order to solve the problem that above-mentioned background technology exists, it is desirable to provide one is straight for half-bridge three-level The capacitance voltage control circuit of current converter, it is achieved input derided capacitors is all pressed with capacitance voltage equal to input The purpose of voltage half, it is ensured that the reliably working of changer.

In order to realize above-mentioned technical purpose, the technical scheme is that

A kind of capacitance voltage control circuit for half-bridge three-level direct current converter, comprises output voltage regulation Device, capacitance voltage regulator, derided capacitors voltage regulator, capacitance voltage control circuit and dividing potential drop Capacitor voltage equalizing control circuit, the first rest-set flip-flop and the second rest-set flip-flop；Described capacitance Control of Voltage Circuit comprises two inputs and two outfans, and one of them input connects the output of output voltage regulator End, another input connects the outfan of capacitance voltage regulator；Described derided capacitors Pressure and Control electricity Road comprises two Pressure and Control unit, and the input of each Pressure and Control unit connects capacitance Control of Voltage electricity The outfan on road and the outfan of derided capacitors voltage regulator, the outfan of the first Pressure and Control unit connects the The input of one rest-set flip-flop, the second Pressure and Control unit connects the input of the second rest-set flip-flop, and first The outfan of rest-set flip-flop and the second rest-set flip-flop output switch pipe respectively drives signal.

Above-mentioned output voltage regulator uses the first anti-phase comparator, and capacitance voltage regulator uses second Anti-phase comparator, derided capacitors voltage regulator uses the 3rd anti-phase comparator, the first anti-phase comparator anti-phase The output sampled voltage of termination half-bridge three-level direct current converter, its homophase termination half-bridge three-level DC converting The output reference voltage of device；The anti-phase termination half-bridge three-level direct current converter of the second anti-phase comparator every straight electricity Hold sampled voltage, the capacitance reference voltage of its homophase termination half-bridge three-level direct current converter；3rd is anti- The derided capacitors sampled voltage of the anti-phase termination half-bridge three-level direct current converter of phase comparator, its homophase termination The derided capacitors reference voltage of half-bridge three-level direct current converter.

Above-mentioned capacitance voltage control circuit comprises first adder and first subtractor, first adder In-phase end connect outfan and the outfan of capacitance voltage regulator of output voltage regulator respectively, it End of oppisite phase ground connection；The outfan of the anti-phase termination capacitance voltage regulator of the first subtractor, its homophase End connects the outfan of output voltage regulator, and this in-phase end ground connection.

The first above-mentioned Pressure and Control unit comprise second adder, the second subtractor, the 3rd subtractor, first Rising edge capture pulse generator, the first trailing edge capture pulse generator, the first comparator and the second comparator； The in-phase end of second adder connects the outfan of first adder, its end of oppisite phase ground connection；Second subtractor End of oppisite phase connects the in-phase end of second adder, and the in-phase end of the second subtractor connects the output of first adder End, and this in-phase end ground connection；The end of oppisite phase of the first comparator connects the outfan of second adder, and first compares The R end that the outfan of device captures pulse generator and the first rest-set flip-flop through the first trailing edge connects, the second ratio The in-phase end of relatively device connects the in-phase end of the first comparator, and this in-phase end also accesses the first triangle carrier signal, The outfan of the second comparator captures the S end of pulse generator and the first rest-set flip-flop even through the first rising edge Connecing, the Q end output switch pipe of the first rest-set flip-flop drives signal.

The second above-mentioned Pressure and Control unit comprises the 3rd adder, the 3rd subtractor, the second rising edge capture arteries and veins Rush generator, the second trailing edge capture pulse generator, the 3rd comparator and the 4th comparator；3rd adder In-phase end connect end of oppisite phase and the outfan of derided capacitors voltage regulator of the second subtractor respectively, it anti- Hold ground connection mutually；The end of oppisite phase of the 3rd subtractor connects in-phase end and the derided capacitors voltage tune of the 3rd adder respectively The outfan of joint device；The end of oppisite phase of the 3rd comparator connects the outfan of the 3rd adder, the 3rd comparator defeated Go out end and capture the S end connection of pulse generator and the second rest-set flip-flop through the second rising edge；4th comparator End of oppisite phase connects the outfan of the 3rd subtractor, and the in-phase end of the 4th comparator connects the homophase of the 3rd comparator Holding, and this in-phase end accesses the second triangle carrier signal, the outfan of the 4th comparator captures through the second trailing edge The R end of pulse generator and the second rest-set flip-flop connects, and the Q end output switch pipe of the second rest-set flip-flop drives Dynamic signal.

Above-mentioned technical scheme is used to have the benefit that

The present invention proposes a kind of capacitance voltage control circuit for half-bridge three-level direct current converter, corrects Due to the time delay of driving circuits and main circuit and the asymmetric input dividing potential drop electricity caused of parasitic parameter thereof Appearance voltage un-balance, capacitance voltage are not equal to the bias-pressure phenomenon of input voltage half.

Accompanying drawing explanation

Fig. 1 is the circuit topology figure of the targeted half-bridge three-level direct current converter of the present invention.

Fig. 2 is circuit diagram and the oscillogram of normal work of half-bridge three-level direct current converter based on Fig. 1. Fig. 2 includes 2-1,2-2.

Fig. 3 .1～3.4 is four kinds of operation mode figures of the half-bridge three-level direct current converter shown in Fig. 2-1.

Fig. 4 is that the positive-negative half-cycle dutycycle of the half-bridge three-level direct current converter shown in Fig. 2-1 does not wait work wave Figure.

Fig. 5 is that the positive-negative half-cycle phase contrast of the half-bridge three-level direct current converter shown in Fig. 2-1 is not equal to 180 ° Working waveform figure.

Fig. 6 is a kind of capacitance voltage control circuit figure for half-bridge three-level direct current converter of the present invention.

Fig. 7 is the work of a kind of capacitance voltage control circuit for half-bridge three-level direct current converter of the present invention Make oscillogram.

Fig. 8 is that the positive-negative half-cycle dutycycle of the half-bridge three-level direct current converter shown in Fig. 2-1 does not wait experimental waveform Figure.

Fig. 9 is that the positive-negative half-cycle phase contrast of the half-bridge three-level direct current converter shown in Fig. 2-1 is not equal to 180 ° Experimental waveform figure.

Figure 10 is that the half-bridge three-level direct current converter shown in Fig. 2-1 is after the capacitance voltage of the present invention controls Experimental waveform figure.Figure 10 includes 10-1；10-2.

Primary symbols title in above-mentioned accompanying drawing:

C_d1、C_d2It is respectively first, second derided capacitors, C_bFor capacitance, Q₁～Q₄Be respectively first～ 4th switching tube, D₁～D₄It is respectively first～the 4th parasitic diode, C₁～C₄It is respectively first～the 4th to post Raw electric capacity, T_RIt is main power transformer, L_fFor output inductor, C_fFor output filter capacitor, R_LFor defeated Go out load resistance.V_inIt is the input voltage of four switch half-bridge three-level direct current converters, V_CbFor capacitance C_bVoltage, V_Cd1、V_Cd2It is respectively derided capacitors C_d1、C_d2Voltage, V_{o_f}For exporting sampled voltage, V_{o_ref}For output reference voltage, V_{EA_Vo}For voltage regulator output signal, V_{Cb_f}For capacitance sampled voltage, V_{cin_f}/ 2 is capacitance reference voltage, V_{EA_Cb}For capacitance voltage regulator output signal, V_{Cd1_f}For Derided capacitors sampled voltage, V_{cin_f}/ 2 is derided capacitors reference voltage, V_{EA_Cd}Export for derided capacitors actuator Signal, V_EA1For first adder output signal, V_EA2It is the first subtracter output signal, V_EA3It is second to add Musical instruments used in a Buddhist or Taoist mass output signal, V_EA4It it is the second subtracter output signal；V_EA5It is the 3rd adder output signal, V_EA6 It is the 3rd subtracter output signal, V_TRI1、V_TRI2It is first, second triangle carrier signal, A₁、A₂、A₃ And A₄For pulse signal, Clock₁、Clock₂、Clock₃And Clock₄For clock signal, Q_{2_dri}It is second to open Close pipe Q₂Driving signal, Q_{4_dri}It is the 4th switching tube Q₄Driving signal.

Detailed description of the invention

Below with reference to accompanying drawing, technical scheme is described in detail.

The circuit topology figure of the half-bridge three-level direct current converter that the present invention as shown in Figure 1 is targeted, comprises defeated Enter partial pressure unit, four switch half-bridge unit, main power transformer T_RWith secondary load unit；Described input Partial pressure unit comprises input voltage source, the first derided capacitors C_d1With the second derided capacitors C_d2, the first dividing potential drop electricity Hold C_d1Positive pole connect input voltage source positive pole, the first derided capacitors C_d1Negative pole connect second dividing potential drop electricity Hold C_d2Positive pole, the second derided capacitors C_d2Negative pole connect input voltage source negative pole；Four described switches Half-bridge cells comprises capacitance C_b, the first switching tube Q₁, second switch pipe Q₂, the 3rd switching tube Q₃With 4th switching tube Q₄And the most one to one first～the 4th parasitic diode and first～the 4th parasitic electricity Hold, the first switching tube Q₁Source electrode connect second switch pipe Q₂Drain electrode, second switch pipe Q₂Source electrode even Meet the 3rd switching tube Q₃Drain electrode, the 3rd switching tube Q₃Source electrode connect the 4th switching tube Q₄Drain electrode, The drain electrode of the one～the 4th switching tube connect respectively first～the 4th the negative electrode and first～the 4th of parasitic diode post One end of raw electric capacity, first～the 4th the source electrode of switching tube connect first～the 4th anode of parasitic diode respectively With first～the 4th other end of parasitic capacitance, the first switching tube Q₁Drain electrode be also connected with the first derided capacitors C_d1 Positive pole, second switch pipe Q₂With the 3rd switching tube Q₃Junction point and the first derided capacitors C_d1With second point Voltage capacitance C_d2Junction point connect, the first switching tube Q₁With second switch pipe Q₂Junction point and main power become Depressor T_RFormer limit connect, the 3rd switching tube Q₃With the 4th switching tube Q₄Junction point through capacitance C_bEven Receive main power transformer T_RFormer limit；Described secondary load unit comprises rectification circuit, output filtered electrical Hold C_fWith output load resistance R_L, main power transformer T_RSecondary connect after rectification circuit successively with output filter Ripple electric capacity C_fWith output load resistance R_LIn parallel.

The circuit diagram of half-bridge three-level direct current converter based on Fig. 1 as shown in Fig. 2-1, it is simply that shown in Fig. 1 Rectification circuit in circuit topology is specially full-wave rectifying circuit.Fig. 2-2 show half-bridge three based on Fig. 1 electricity The normal working waveform figure of straight flow changer, the abscissa of oscillogram is time t, and vertical coordinate depends on from top to bottom Secondary is dutycycle D of switching tube, AB point voltage v_AB, primary current i_p, output inductor electric current i_Lf, Commutation diode D_R1、D_R2Electric current i_DR1、i_DR2.It may be seen that ideally, drive full symmetric, Primary current i_pSymmetry, brachium pontis mid-point voltage V_ABSymmetrical.During changer work, input derided capacitors voltage is equal Pressure, capacitance voltage is equal to the half of input voltage, primary side switch pipe and the equilibrium of secondary rectifier tube voltage stress.

Fig. 3 is the operation mode figure of the half-bridge three-level direct current converter shown in Fig. 2-1, and Fig. 3-1 divides to 3-4 Do not illustrate the operation mode of four mode.

Fig. 4 is that the positive-negative half-cycle dutycycle of the half-bridge three-level direct current converter shown in Fig. 2-1 does not wait work wave Figure.The abscissa of oscillogram is time t, and vertical coordinate is dutycycle D of switching tube the most successively, AB Point voltage v_AB, primary current i_p, output inductor electric current i_Lf.Positive-negative half-cycle dutycycle etc. can not cause every Straight capacitance voltage is not equal to V_in/ 2, input derided capacitors voltage is uneven, makes a concrete analysis of as follows.

Assume D_pFor the dutycycle of positive half cycle, D_nFor the dutycycle of negative half period, T_pfFor positive half cycle time of afterflow, T_nfFor negative half period time of afterflow, T_sFor switch periods.When changer steady operation, according to transformator T_RMagnetic Logical conservation can obtain following formula:

(V_in-V_Cb)·D_p·T_s=V_Cb·D_n·T_s

When positive-negative half-cycle dutycycle does not waits, D_p≠D_n, capacitance voltage V can be obtained_Cb:

$V_{\mathrm{Cb}}=\frac{D_p\·V_{\mathrm{in}}}{D_p+D_n}$

Work as D_p>D_nTime, capacitance voltage V_CbHigher than V_in/2；Otherwise, D_p<D_nTime, V_CbLess than V_in/2.Every There is biasing problem in straight electric capacity.

Assume D_p>D_n, now V_CbHigher than V_in/2.Ignore the process of Sofe Switch, during steady-state operation, due to every Straight electric capacity C_bAmassing ampere-second within the whole cycle is zero, derided capacitors C_d1At freewheeling period T_pf、T_nfAmpere-second amass It is zero, so capacitance is at D_pT_s、D_nT_sInterior ampere-second is long-pending is also zero, therefore at D_pT_s、D_nT_sIn Current average I_P1、I_N1Meet:

$\frac{I_{P1}}{I_{N1}}=\frac{D_n}{D_p}<1$

D_pT_s、D_nT_sInterior current change quantity Δ I_P、ΔI_NFor

${\mathrm{\&Delta;I}}_P=\frac{D_p{D}_n{T}_s\&CenterDot;V_{\mathrm{in}}}{L(D_p+D_n)}-\frac{D_p{T}_s\&CenterDot;V_o}{\mathrm{KL}},{\mathrm{\&Delta;I}}_N=\frac{D_p{D}_n{T}_s\&CenterDot;V_{\mathrm{in}}}{L(D_p+D_n)}-\frac{D_n{T}_s\&CenterDot;V_o}{\mathrm{KL}}$

L is filter inductance size, V_oFor output voltage, I_oFor output electric current, K is transformer primary secondary no-load voltage ratio.By Above formula can obtain, the half period D that dutycycle is little_nInductive current ripple is big, and meansigma methods is big, and therefore positive-negative half-cycle continues Stream stage T_pf、T_nfInitial current I_p<I_n, there is voltage un-balance phenomenon in input derided capacitors.

By the equal T of positive-negative half-cycle time of afterflow_pf=T_nf, according in positive-negative half-cycle afterflow period during stable state, C_d1's Ampere-second is amassed equal:

I_P2·T_pf=I_N2·T_nf

I can be obtained_P2=I_N2。I_P2For T_pfInterior average current, I_N2For T_nfInterior average current.So during stable state, input point Voltage capacitance C_d1Voltage necessarily be greater than capacitance C_bVoltage so that primary current is less than at positive half cycle rate of descent Negative half period, final I_P2=I_N2。

Fig. 5 is that the positive-negative half-cycle phase contrast of the half-bridge three-level direct current converter shown in Fig. 2-1 is not equal to 180 ° Working waveform figure.The abscissa of oscillogram is time t, and vertical coordinate is the dutycycle of switching tube the most successively D, AB point voltage v_AB, primary current i_p, output inductor electric current i_Lf.Positive-negative half-cycle phase contrast is not equal to 180 ° do not interfere with capacitance voltage, but can cause input derided capacitors voltage un-balance, make a concrete analysis of as follows.

If drive positive-negative half-cycle phase contrast to be not equal to 180 °, but the equal (D of dutycycle_p=D_n=D) time, can obtain To capacitance voltage V_Cb:

$V_{\mathrm{Cb}}=\frac{D_p\&CenterDot;V_{\mathrm{in}}}{D_p+D_n}=\frac{V_{\mathrm{in}}}{2}$

If positive-negative half-cycle phase contrast is not equal to 180 °, then the positive-negative half-cycle freewheeling period time.Assume to drive Dynamic 180 ° of-θ of signal positive-negative half-cycle phase contrast (θ > 0), time of afterflow T_pf、T_nfIt is respectively as follows:

$T_{\mathrm{pf}}=(\frac{1}{2}-D)T_s-\frac{\mathrm{\&theta;}}{180}{T}_s,T_{\mathrm{nf}}=(\frac{1}{2}-D)T_s+\frac{\mathrm{\&theta;}}{180}{T}_s$

That is, T_pf<T_nf.Meanwhile, the equal I of the initial current of positive-negative half-cycle freewheeling period_p=I_n.According to during stable state positive and negative half In the Zhou Xuliu period, derided capacitors C_d1Amassing ampere-second is zero, obtains I_P2>I_N2, therefore input derided capacitors C_d1Electricity Pressure have to be larger than capacitance C_bVoltage so that at T_pfIn stage, electric current rises, at T_nfIn stage under electric current Fall, thus average current I_P2>I_N2, so V_Cd1More than V_in/2。

Fig. 6 is a kind of capacitance voltage control circuit figure for half-bridge three-level direct current converter of the present invention.Should Circuit comprise output voltage regulator, capacitance voltage regulator, derided capacitors voltage regulator, every straight electricity Hold voltage control circuit and derided capacitors voltage-equalizing control circuit, the first rest-set flip-flop and the second rest-set flip-flop； Described capacitance voltage control circuit comprises two inputs and two outfans, and one of them input connects The outfan of output voltage regulator, another input connects the outfan of capacitance voltage regulator；Institute Stating derided capacitors voltage-equalizing control circuit and comprise two Pressure and Control unit, the input of each Pressure and Control unit is even Connecing outfan and the outfan of derided capacitors voltage regulator of capacitance voltage control circuit, first is the most voltage-controlled The outfan of unit processed connects the input of the first rest-set flip-flop, and the second Pressure and Control unit connects the 2nd RS The input of trigger, the outfan of the first rest-set flip-flop and the second rest-set flip-flop output switch pipe respectively drives Dynamic signal.

Above-mentioned output voltage regulator uses the first anti-phase comparator, and capacitance voltage regulator uses second Anti-phase comparator, derided capacitors voltage regulator uses the 3rd anti-phase comparator, the first anti-phase comparator anti-phase The output sampled voltage V of termination half-bridge three-level direct current converter_{o_f}, its homophase termination half-bridge three-level direct current The output reference voltage V of changer_{o_ref}；The anti-phase termination half-bridge three-level DC converting of the second anti-phase comparator The capacitance sampled voltage V of device_{Cb_f}, the capacitance of its homophase termination half-bridge three-level direct current converter Reference voltage V_{cin_f}/2；The derided capacitors of the anti-phase termination half-bridge three-level direct current converter of the 3rd anti-phase comparator Sampled voltage V_{Cd1_f}, the derided capacitors reference voltage of its homophase termination half-bridge three-level direct current converter V_{cin_f}/2。

Above-mentioned capacitance voltage control circuit comprises first adder and first subtractor, first adder In-phase end connect outfan and the outfan of capacitance voltage regulator of output voltage regulator respectively, it End of oppisite phase ground connection；The outfan of the anti-phase termination capacitance voltage regulator of the first subtractor, its homophase End connects the outfan of output voltage regulator, and this in-phase end ground connection.

The first above-mentioned Pressure and Control unit comprise second adder, the second subtractor, the 3rd subtractor, first Rising edge capture pulse generator, the first trailing edge capture pulse generator, the first comparator and the second comparator； The in-phase end of second adder connects the outfan of first adder, its end of oppisite phase ground connection；Second subtractor End of oppisite phase connects the in-phase end of second adder, and the in-phase end of the second subtractor connects the output of first adder End, and this in-phase end ground connection；The end of oppisite phase of the first comparator connects the outfan of second adder, and first compares The R end that the outfan of device captures pulse generator and the first rest-set flip-flop through the first trailing edge connects, the second ratio The in-phase end of relatively device connects the in-phase end of the first comparator, and this in-phase end also accesses the first triangle carrier signal V_TRI1, the outfan of the second comparator captures pulse generator and the S of the first rest-set flip-flop through the first rising edge End connects, and the Q end output switch pipe of the first rest-set flip-flop drives signal Q_{2_dri}。

The second above-mentioned Pressure and Control unit comprises the 3rd adder, the 3rd subtractor, the second rising edge capture arteries and veins Rush generator, the second trailing edge capture pulse generator, the 3rd comparator and the 4th comparator；3rd adder In-phase end connect end of oppisite phase and the outfan of derided capacitors voltage regulator of the second subtractor respectively, it anti- Hold ground connection mutually；The end of oppisite phase of the 3rd subtractor connects in-phase end and the derided capacitors voltage tune of the 3rd adder respectively The outfan of joint device；The end of oppisite phase of the 3rd comparator connects the outfan of the 3rd adder, the 3rd comparator defeated Go out end and capture the S end connection of pulse generator and the second rest-set flip-flop through the second rising edge；4th comparator End of oppisite phase connects the outfan of the 3rd subtractor, and the in-phase end of the 4th comparator connects the homophase of the 3rd comparator Hold, and this in-phase end accesses the second triangle carrier signal V_TRI2, the outfan of the 4th comparator declines through second R end along capture pulse generator and the second rest-set flip-flop connects, and the Q end output of the second rest-set flip-flop is opened Close pipe and drive signal Q_{4_dri}。

The specific works principle of above-mentioned control circuit is as follows:

The output sampled voltage V that the output voltage of changer obtains through over-sampling_{o_f}With output reference voltage V_{o_ref} Compare and enlarge and obtain voltage regulator output signal V_{EA_Vo}.Capacitance voltage V_CbObtain through over-sampling Capacitance sampled voltage V_{Cb_f}With capacitance reference voltage V_{cin_f}/ 2 compare and enlarge and obtain every straight electricity Hold voltage regulator output signal V_{EA_Cb}.Derided capacitors voltage V_Cd1Through the derided capacitors sampling that over-sampling obtains Voltage V_{Cd1_f}With derided capacitors reference voltage V_{cin_f}/ 2 compare and enlarge obtain derided capacitors actuator output letter Number V_{EA_Cd}。V_{EA_Vo}And V_{EA_Cb}Output signal V is obtained through first adder_EA1, through the first subtractor Obtain output signal V_EA2；V_EA1And V_{EA_Cd}Output signal V is obtained through second adder_EA3, Jing Guo Two subtractors obtain output signal V_EA4；V_EA2And V_{EA_Cd}Output signal V is obtained through the 3rd adder_EA5, Output signal V is obtained through the 3rd subtractor_EA6。V_EA3And V_EA4Respectively with the first triangle carrier signal V_TRI1 Hand over to cut and generate pulse signal A₁And A₂, V_EA5And V_EA6Respectively with the second triangle carrier signal V_TRI2Hand over and cut life Become pulse signal A₃And A₄.Trailing edge capture pulse generator captures A respectively₁And A₄Trailing edge obtains clock Signal Clock₁And Clock₄, rising edge capture pulse generator captures A respectively₂And A₃Trailing edge obtains clock Signal Clock₂And Clock₃。Clock₁And Clock₂Second switch pipe Q is generated by rest-set flip-flop₂Drive Dynamic signal Q_{2_dri}, Clock₃And Clock₄The 4th switching tube Q is generated by rest-set flip-flop₄Driving signal Q_{4_dri}。

Fig. 7 is the work of a kind of capacitance voltage control circuit for half-bridge three-level direct current converter of the present invention Make oscillogram.The abscissa of oscillogram is time t, and vertical coordinate is V the most successively_TRI1、V_TRI2、Drive₁、 Drive₂、Clock₁、Clock₂、Drive₃, Drive₁It is correction front wheel driving waveform, positive-negative half-cycle dutycycle Equal, phase contrast is equal to 180 °；Drive₂Rear drive waveform, positive-negative half-cycle is corrected for capacitance Control of Voltage Dutycycle, phase contrast is equal to 180 °；Drive₃Rear drive waveform is corrected, just for derided capacitors Control of Voltage Negative half period dutycycle, phase contrast is not equal to 180 °.Therefore this control circuit can be by correction driving Signal realizes what capacitance voltage controlled.

Fig. 8 is that the positive-negative half-cycle dutycycle of the half-bridge three-level direct current converter shown in Fig. 2-1 does not wait experimental waveform Figure.In figure, abscissa is time t, and vertical coordinate from top to bottom, is brachium pontis mid-point voltage v respectively_AB, former limit electricity Stream i_p, derided capacitors C_d1Voltage V_Cd1, capacitance voltage V_Cb, input voltage V_in, switching tube Q₁Drain-source Pole tension v_DS1, switching tube Q₃Drain-source voltage v_DS3.By accompanying drawing 8 it can be seen that brachium pontis mid-point voltage and Primary current is asymmetric, and capacitance voltage is higher than V_in/ 2, derided capacitors C_d1Voltage is higher than capacitance voltage, Switching tube Q₁、Q₃Voltage stress is uneven.

Fig. 9 is that the positive-negative half-cycle phase contrast of the half-bridge three-level direct current converter shown in Fig. 2-1 is not equal to 180 ° Experimental waveform figure.In figure, abscissa is angle ω t, and vertical coordinate from top to bottom, is brachium pontis mid-point voltage respectively v_AB, primary current i_p, derided capacitors C_d1Voltage V_Cd1, capacitance voltage V_Cb, input voltage V_in, open Close pipe Q₁Drain-source voltage v_DS1, switching tube Q₃Drain-source voltage v_DS3.By accompanying drawing 9 it can be seen that brachium pontis Mid-point voltage and primary current are asymmetric, and capacitance voltage is equal to V_in/ 2, derided capacitors C_d1Voltage is higher than V_in/ 2, switching tube Q₁、Q₃Voltage stress is uneven.

Figure 10 is that the half-bridge three-level direct current converter shown in Fig. 2-1 is after the capacitance voltage of the present invention controls Experimental waveform figure.The abscissa of Figure 10-1 is time (Time), and vertical coordinate from top to bottom, is in brachium pontis respectively Point voltage v_AB, primary current i_p, derided capacitors C_d1Voltage V_Cd1, capacitance voltage V_Cb, input voltage V_in, switching tube Q₁Drain-source voltage v_DS1, switching tube Q₃Drain-source voltage v_DS3.Can be seen by Figure 10-1 Going out, brachium pontis mid-point voltage and primary current are symmetrical, capacitance and derided capacitors C_d1Voltage is equal to V_in/ 2, Switching tube Q₁、Q₃Voltage stress is equal.The abscissa of Figure 10-2 is time (Time), and vertical coordinate is by up to Under, it is brachium pontis mid-point voltage v respectively_AB, primary current i_p, secondary rectifier tube D_R1、D_R2Anode and cathode voltage v_DR1、 v_DR2.By Figure 10-2 it can be seen that secondary rectifier tube voltage stress is equal.

Half-bridge three-level direct current converter shown in Fig. 2-1 after the capacitance voltage control circuit that the present invention proposes, Specific performance parameter is as follows:

(1) four switch half-bridge three-level direct current converter input voltage V_in=800V

(2) changer output voltage V_o=28V

(3) changer output P_o=2KW

(4) converter transformer T_RFormer secondary no-load voltage ratio 22:2

(5) capacitance C_b=4.7_μF/700V

(6) input derided capacitors C_d1=C_d2=470×2μF/450V

Seen from the above description, the capacitance voltage control strategy that the present invention proposes can correct owing to controlling and driving The time delay of circuit and main circuit and parasitic parameter asymmetric cause input derided capacitors voltage un-balance, every straight electricity Hold voltage and be not equal to the bias-pressure phenomenon of input voltage half.

Above example is only the technological thought that the present invention is described, it is impossible to limit protection scope of the present invention with this, Every technological thought proposed according to the present invention, any change done on the basis of technical scheme, each fall within this Within invention protection domain.

Claims (4)

1. the capacitance voltage control circuit for half-bridge three-level direct current converter, it is characterised in that: this circuit Comprise output voltage regulator, capacitance voltage regulator, derided capacitors voltage regulator, capacitance electricity Pressure control circuit and derided capacitors voltage-equalizing control circuit, the first rest-set flip-flop and the second rest-set flip-flop；Described Capacitance voltage control circuit comprises two inputs and two outfans, and one of them input connects output The outfan of voltage regulator, another input connects the outfan of capacitance voltage regulator；Described point Voltage capacitance voltage-equalizing control circuit comprises the first Pressure and Control unit and the second Pressure and Control unit, each Pressure and Control The input of unit is all connected with the outfan of capacitance voltage control circuit and derided capacitors voltage regulator Outfan, the outfan of the first Pressure and Control unit connects the input of the first rest-set flip-flop, and second is the most voltage-controlled Unit processed connects the input of the second rest-set flip-flop, the first rest-set flip-flop and the output of the second rest-set flip-flop End output switch pipe respectively drives signal；Described capacitance voltage control circuit comprises first adder and One subtractor, the in-phase end of first adder connects outfan and the capacitance electricity of output voltage regulator respectively The outfan of pressure actuator, its end of oppisite phase ground connection；The anti-phase termination capacitance voltage-regulation of the first subtractor The outfan of device, its in-phase end connects the outfan of output voltage regulator, and this in-phase end ground connection.

A kind of capacitance voltage control circuit for half-bridge three-level direct current converter the most according to claim 1, It is characterized in that: described output voltage regulator uses the first anti-phase comparator, capacitance voltage regulator Using the second anti-phase comparator, derided capacitors voltage regulator uses the 3rd anti-phase comparator, the first anti-phase comparison The output sampled voltage of the anti-phase termination half-bridge three-level direct current converter of device, its homophase termination half-bridge three-level The output reference voltage of DC converter；The anti-phase termination half-bridge three-level direct current converter of the second anti-phase comparator Capacitance sampled voltage, it homophase termination half-bridge three-level direct current converter capacitance benchmark electricity Pressure；The derided capacitors sampled voltage of the anti-phase termination half-bridge three-level direct current converter of the 3rd anti-phase comparator, it Homophase termination half-bridge three-level direct current converter derided capacitors reference voltage.

A kind of capacitance voltage control circuit for half-bridge three-level direct current converter the most according to claim 1, It is characterized in that: the first described Pressure and Control unit comprises second adder, the second subtractor, the first rising Along capture pulse generator, the first trailing edge capture pulse generator, the first comparator and the second comparator；The The in-phase end of two adders connects the outfan of first adder, its end of oppisite phase ground connection；Second subtractor anti- End connects the in-phase end of second adder mutually, and the in-phase end of the second subtractor connects the outfan of first adder, And this in-phase end ground connection；The end of oppisite phase of the first comparator connects the outfan of second adder, the first comparator The R end that outfan captures pulse generator and the first rest-set flip-flop through the first trailing edge connects, the second comparator In-phase end connect the in-phase end of the first comparator, and this in-phase end also accesses the first triangle carrier signal, second The S end that the outfan of comparator captures pulse generator and the first rest-set flip-flop through the first rising edge connects, the The Q end output switch pipe of one rest-set flip-flop drives signal.

A kind of capacitance voltage control circuit for half-bridge three-level direct current converter the most according to claim 3, It is characterized in that: the second described Pressure and Control unit comprises the 3rd adder, the 3rd subtractor, the second rising Along capture pulse generator, the second trailing edge capture pulse generator, the 3rd comparator and the 4th comparator；The The in-phase end of three adders connects end of oppisite phase and the output of derided capacitors voltage regulator of the second subtractor respectively End, its end of oppisite phase ground connection；The end of oppisite phase of the 3rd subtractor connects in-phase end and the dividing potential drop of the 3rd adder respectively The outfan of capacitance voltage actuator；The outfan of end of oppisite phase connection the 3rd adder of the 3rd comparator, the 3rd The S end that the outfan of comparator captures pulse generator and the second rest-set flip-flop through the second rising edge connects；The The end of oppisite phase of four comparators connects the outfan of the 3rd subtractor, and the in-phase end of the 4th comparator connects the 3rd and compares The in-phase end of device, and this in-phase end accesses the second triangle carrier signal, the outfan of the 4th comparator is through second time Fall connects along the R end of capture pulse generator and the second rest-set flip-flop, the Q end output of the second rest-set flip-flop Switching tube drives signal.