CN103699357B - A kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square - Google Patents
A kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square Download PDFInfo
- Publication number
- CN103699357B CN103699357B CN201310655820.XA CN201310655820A CN103699357B CN 103699357 B CN103699357 B CN 103699357B CN 201310655820 A CN201310655820 A CN 201310655820A CN 103699357 B CN103699357 B CN 103699357B
- Authority
- CN
- China
- Prior art keywords
- input
- gate array
- multiplication
- outfan
- modular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Complex Calculations (AREA)
Abstract
The invention discloses a kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square, this circuit structure include multiplication or square partial product produce circuit, 2 m+1 positions two input and gate array, m+1 two-stage CSA adder units, m+2 FA unit of full adder, and m+3 sweep trigger.The present invention is directed to m position Big prime P can take from a high position to the method for low level yojan, while multiplication and square operation, its result can be carried out yojan, thus avoid the process that multiplication and squared results are individually carried out yojan, decrease the time of modular multiplication and mould square；Meanwhile, eliminate special mould yojan circuit module, reduce circuit area.
Description
Technical field
The present invention relates to IC design field, be specifically related to a kind of quick for modular multiplication and mould square
Mould Algorithm for Reduction circuit.
Background technology
Taking advantage of the mould yojan process with mould square currently for big digital-to-analogue, the scheme generally used is first to calculate
Going out the result of multiplication peace side, then use special mould yojan circuit to carry out yojan, the program needs to expend
Special mould yojan module and mould yojan time.In view of this, it is necessary to a kind of New-type mould yojan of design is calculated
Method, carries out yojan while multiplication and square operation to its result, solves the problems referred to above.
Summary of the invention
It is an object of the invention to provide a kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square,
This circuit can be for m position Big prime P from a high position to low level yojan, while multiplication and square operation
Its result is carried out yojan, thus avoids the process that multiplication and squared results are individually carried out yojan, subtract
Lack the time of modular multiplication and mould square；Meanwhile, eliminate special mould yojan circuit module, reduce electricity
Road surface is amassed.
In order to achieve the above object, the technical solution adopted in the present invention is: include multiplication or square portion
Point long-pending produce circuit, two inputs and the gate array of 2 m+1 positions, the unit of full adder FA of m+2 position and
The sweep trigger of m+3 position；Two inputs of 2 m+1 positions have for inciting somebody to action with being connected on the outfan of gate array
4 multidigit addends are compressed into the 4-2 compressor of the m+1 position of 2 addends；Two input with gate array
Input is connected with the m+1 position of sweep trigger and the outfan of m+2 position respectively, another input
It is connected with complement code Pb of the Big prime P of m position；Two inputs of 2 m+1 positions and the outfan of gate array,
Before the outfan of partial product generation circuit and sweep trigger, the outfan of m+1 position is all connected to 4-2 compression
On the input of device；The outfan of 4-2 compressor is connected with the input of unit of full adder FA, full adder
The result outfan of unit F A is connected with the input of sweep trigger；Wherein, 160≤m≤15360.
The described two-stage adder unit CSA that 4-2 compressor is m+1 position.
4 multidigit addends of described two-stage adder unit CSA are respectively from: partial product produces circuit
The front m+1 position of the cumulative sum of partial product, sweep trigger and 2 two outputs inputted with gate array.
Described two inputs and gate array include the one or two input of m+1 position and gate array, the of m+1 position
Two or two input and gate arrays；The output of the m+1 position of sweep trigger is connected to the one or two input and gate array
An input on, the 0th of complement code Pb of the Big prime P of m position is connected respectively to m-1 position
One or two input with on the 0th of gate array to another input of m-1 position, the one or two input and door
Another input termination " 0 " of the m position of array；The output of the m+2 position of sweep trigger is connected to
Two or two inputs with on an input of gate array, the 0th of complement code Pb of the Big prime P of m position to the
M-1 position be connected respectively to the two or two input with on the 1st of gate array to another input of m position,
Two or two input another input termination " 0 " with the 0th of gate array.
Compared with prior art, the method have the advantages that
In the present invention, this circuit often just can add up a line partial product through a clock cycle, simultaneously
The highest order of the cumulative sum of last partial product is fallen in yojan, and output result moves to left.The present invention is directed to m position the most plain
Number P takes from a high position to the method for low level yojan, can be to its result while multiplication and square operation
Carry out yojan, thus avoid the process that multiplication and squared results are individually carried out yojan, decrease modular multiplication
Time with mould square；Meanwhile, eliminate special mould yojan circuit module, reduce circuit area.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the present invention；
Fig. 2 is the physical circuit figure of the present invention.
Detailed description of the invention
The present invention is further detailed explanation below in conjunction with the accompanying drawings:
See Fig. 1 and Fig. 2, the present invention include multiplication or square partial product produce circuit, 2 m+1 positions
Two inputs and gate array, the unit of full adder FA of m+2 position and the sweep trigger of m+3 position；2
Two inputs of m+1 position add for 4 multidigit addends are compressed into 2 with being connected on the outfan of gate array to have
The 4-2 compressor of the m+1 position of number, 4-2 compressor is the two-stage adder unit CSA of m+1 position.Two-stage adds
4 multidigit addends of method unit CSA are respectively from: partial product produces the partial product of circuit, scanning is touched
Send out the outputs of the front m+1 position of the cumulative sum of device and 2 two inputs and gate array.Two inputs and gate array
One input is connected with the m+1 position of sweep trigger and the outfan of m+2 position respectively, and another is defeated
Enter end to be connected with complement code Pb of the Big prime P of m position；Two inputs of 2 m+1 positions and the output of gate array
Before the outfan of end, partial product generation circuit and sweep trigger, the outfan of m+1 position is all connected to 4-2
On the input of compressor；Two inputs and gate array include the one or two input and gate array, the m+1 of m+1 position
Two or two input and gate array of position；The output of the m+1 position of sweep trigger be connected to the one or two input with
On one input of gate array, the 0th of complement code Pb of the Big prime P of m position to m-1 position is respectively
Being connected to the one or two input with on the 0th of gate array to another input of m-1 position, the one or two is defeated
Another input entering the m position with gate array terminates " 0 "；The output of the m+2 position of sweep trigger is even
Receive on an input of the two or two input and gate array, the 0th of complement code Pb of the Big prime P of m position
Position is connected respectively to the 1st another input to m position of the two or two input and gate array to m-1 position
On end, the two or two input another input termination " 0 " with the 0th of gate array.The output of 4-2 compressor
End is connected with the input of unit of full adder FA, the result outfan of unit of full adder FA and sweep trigger
Input be connected；Wherein, 160≤m≤15360.
In the present invention, this circuit often just can add up a line partial product through a clock cycle, simultaneously
The highest order of the cumulative sum of last partial product is fallen in yojan, and output result moves to left.
See Fig. 2, RS=0 during initialization, m+3 bit register is all set to 0；Output
Q [m+2:0]=000 ... 00 ... 000.During work, RS=1, SE=1, Q [m+2] and Q [m+1] are zero,
First efficient clock along time, be 0 from the addend with gate array, need not yojan i.e. for the first time,
Partial product adds up and moves to left and is stored in depositor；Behind second efficient clock edge, by the output of the highest two
Q [m+2] and Q [m+1] controls whether two export 2Pb or Pb with gate array, thus carries out yojan.Directly
To m-th clock edge, last column multiplication or square partial added.The m+2 clock
Along arrive before, SE is set to 0, the most again through two clock edges, multiplication or square operation result
By yojan to m position.
Claims (4)
1. one kind is used for modular multiplication and the Fast Modular Algorithm for Reduction circuit of mould square, it is characterised in that: include taking advantage of
Method or square partial product produce circuit, 2 m+1 positions two input with gate array, the full adders of m+2 position
Unit F A and the sweep trigger of m+3 position；In two inputs of 2 m+1 positions and the outfan of gate array
Connect the 4-2 compressor having the m+1 position for 4 multidigit addends being compressed into 2 addends；Two inputs
With an input of gate array respectively with m+1 position and the outfan phase of m+2 position of sweep trigger
Even, another input is connected with complement code Pb of the Big prime P of m position；2 m+1 positions two input with
The outfan of m+1 position before the outfan of the outfan of gate array, partial product generation circuit and sweep trigger
It is all connected on the input of 4-2 compressor；The outfan of 4-2 compressor is defeated with unit of full adder FA's
Entering end to be connected, the result outfan of unit of full adder FA is connected with the input of sweep trigger；Wherein,
160≤m≤15360。
Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square the most according to claim 1, its
It is characterised by: the described two-stage adder unit CSA that 4-2 compressor is m+1 position.
Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square the most according to claim 2, its
It is characterised by: 4 multidigit addends of described two-stage adder unit CSA are respectively from: partial product produces
The front m+1 position of the cumulative sum of the partial product of circuit, sweep trigger and 2 two inputs are defeated with gate array
Go out.
Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square the most according to claim 1, its
It is characterised by: two described inputs and gate array include the one or two input and gate array, the m+1 of m+1 position
Two or two input and gate array of position；The output of the m+1 position of sweep trigger be connected to the one or two input with
On one input of gate array, the 0th of complement code Pb of the Big prime P of m position to m-1 position is respectively
Being connected to the one or two input with on the 0th of gate array to another input of m-1 position, the one or two is defeated
Another input entering the m position with gate array terminates " 0 "；The output of the m+2 position of sweep trigger is even
Receive on an input of the two or two input and gate array, the 0th of complement code Pb of the Big prime P of m position
Position is connected respectively to the 1st another input to m position of the two or two input and gate array to m-1 position
On end, the two or two input another input termination " 0 " with the 0th of gate array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310655820.XA CN103699357B (en) | 2013-12-05 | 2013-12-05 | A kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310655820.XA CN103699357B (en) | 2013-12-05 | 2013-12-05 | A kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103699357A CN103699357A (en) | 2014-04-02 |
| CN103699357B true CN103699357B (en) | 2016-11-23 |
Family
ID=50360898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310655820.XA Expired - Fee Related CN103699357B (en) | 2013-12-05 | 2013-12-05 | A kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103699357B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106873941B (en) * | 2017-01-19 | 2019-05-21 | 西安交通大学 | A kind of Fast Modular Multiplication and mould squaring circuit and its implementation |
| CN114879934B (en) * | 2021-12-14 | 2023-01-10 | 中国科学院深圳先进技术研究院 | Efficient zero-knowledge proof accelerator and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426743A (en) * | 1991-03-29 | 1995-06-20 | International Business Machines Corporation | 3-1 Arithmetic logic unit for simultaneous execution of an independent or dependent add/logic instruction pair |
| US5436574A (en) * | 1993-11-12 | 1995-07-25 | Altera Corporation | Universal logic module with arithmetic capabilities |
| CN1449519A (en) * | 2000-05-15 | 2003-10-15 | 艾蒙系统股份有限公司 | Extending the range of computational fields of integers |
| CN1883155A (en) * | 2003-11-18 | 2006-12-20 | 爱特梅尔股份有限公司 | Randomized modular reduction method and hardware therefor |
| CN101000538A (en) * | 2007-01-05 | 2007-07-18 | 东南大学 | Implement method of elliptic curve cipher system coprocessor |
| CN101194457A (en) * | 2005-05-12 | 2008-06-04 | 爱特梅尔公司 | Randomized modular polynomial reduction method and hardware therefor |
-
2013
- 2013-12-05 CN CN201310655820.XA patent/CN103699357B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426743A (en) * | 1991-03-29 | 1995-06-20 | International Business Machines Corporation | 3-1 Arithmetic logic unit for simultaneous execution of an independent or dependent add/logic instruction pair |
| US5436574A (en) * | 1993-11-12 | 1995-07-25 | Altera Corporation | Universal logic module with arithmetic capabilities |
| CN1449519A (en) * | 2000-05-15 | 2003-10-15 | 艾蒙系统股份有限公司 | Extending the range of computational fields of integers |
| CN1883155A (en) * | 2003-11-18 | 2006-12-20 | 爱特梅尔股份有限公司 | Randomized modular reduction method and hardware therefor |
| CN101194457A (en) * | 2005-05-12 | 2008-06-04 | 爱特梅尔公司 | Randomized modular polynomial reduction method and hardware therefor |
| CN101000538A (en) * | 2007-01-05 | 2007-07-18 | 东南大学 | Implement method of elliptic curve cipher system coprocessor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103699357A (en) | 2014-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102403988B (en) | Power on reset circuit | |
| CN103176767B (en) | The implementation method of the floating number multiply-accumulate unit that a kind of low-power consumption height is handled up | |
| CN103699357B (en) | A kind of Fast Modular Algorithm for Reduction circuit for modular multiplication and mould square | |
| WO2014175915A1 (en) | Hardware de-convolution block for multi-phase scanning | |
| Low et al. | A new approach to the design of efficient residue generators for arbitrary moduli | |
| CN104112051A (en) | Element shape function based reflector antenna electromechanical integration design method | |
| CN106462310B (en) | The method of the touch point of touch chip and touch chip detection touch screen | |
| CN105278789A (en) | Large-sized capacitive touch panel and processing method | |
| CN103020014A (en) | Method for realizing FFT (Fast Fourier Transform) with high point number | |
| CN103888246A (en) | Low-energy-consumption small-area data processing method and data processing device thereof | |
| CN104049816A (en) | Plate electrode for capacitive touch screen, touch screen and touch display device | |
| Buddhe et al. | Design and verification of dadda algorithm based binary floating point multiplier | |
| CN104484084A (en) | Driving method of touch screen, touch screen and display device | |
| CN102156597B (en) | Touch detection system and method | |
| CN203217535U (en) | Electrode board of capacitive type touch screen, touch screen and touch display device | |
| CN104485131B (en) | Voltage generation circuit and memory | |
| CN104768350B (en) | Waterproof construction | |
| CN203101466U (en) | Electric energy measuring creeping control circuit | |
| Praveena | Enhanced portable lut multiplier with gated power optimization for biomedical therapeutic devices | |
| Tang et al. | A high-performance 32-bit parallel multiplier using modified Booth's algorithm and sign-deduction algorithm | |
| CN204256714U (en) | A kind of touch-screen and display device | |
| Galybin | On the modification of the method of mechanical quadrature for SIE in crack problems under step-like loads | |
| JP6284330B2 (en) | Touch sensor device and touch sensitive method | |
| Padmapriya et al. | Design of a power optimal reversible FIR filter for speech signal processing | |
| RU2654137C1 (en) | Solving systems of logical equations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161123 Termination date: 20201205 |