CN103698945B - Array base palte and preparation method thereof, display panel - Google Patents
Array base palte and preparation method thereof, display panel Download PDFInfo
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- CN103698945B CN103698945B CN201310690031.XA CN201310690031A CN103698945B CN 103698945 B CN103698945 B CN 103698945B CN 201310690031 A CN201310690031 A CN 201310690031A CN 103698945 B CN103698945 B CN 103698945B
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- base palte
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Abstract
The present invention relates to technical field of liquid crystal display, a kind of array base palte and preparation method thereof, display panel are provided.By the chock insulator matter supporting zone on array base palte, electric charge transmitting layer is set, and the static discharge unit be electrically connected with described electric charge transmitting layer is set, thus chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be discharged, overcome the liquid crystal molecular orientation of this electrostatic to chock insulator matter periphery to have an impact, the problems such as the light leak caused.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of array base palte and preparation method thereof, display panel.
Background technology
Thin Film Transistor-LCD (ThinFilmTransistor-LiquidCrystalDisplay, be called for short TFT-LCD) feature such as to have volume little, low in energy consumption, radiationless, developed rapidly in recent years, dominate in current flat panel display market.
The agent structure of TFT-LCD comprises array base palte to box and color membrane substrates, the liquid crystal molecule of filling between array base palte and color membrane substrates.Array base palte is formed with data line, grid line and common signal line, and the pixel cell limited by data line and grid line, each pixel cell comprises thin film transistor (TFT) (ThinFilmTransistor is called for short TFT) and transparent pixels electrode.Wherein, common signal line and grid line are formed, for array base palte provides reference voltage by same layer metal.Color membrane substrates is formed with colored filter, black matrix and chock insulator matter, black matrix limits sub-pixel unit, and sub-pixel unit is corresponding with the pixel cell position on array base palte.Chock insulator matter is positioned at the region at black matrix place, plays a supporting role, for forming certain space between array base palte and color membrane substrates, and filling liquid crystal molecule.Correspondingly, position corresponding with chock insulator matter on array base palte is provided with chock insulator matter supporting zone, and it is made up of TFT active layer and source and drain metal level.TFT-LCD also comprises public electrode, forms the electric field driving liquid crystal deflecting element between transparent pixels electrode and public electrode, realizes picture display.
In the course of the work, the phenomenons such as if the chock insulator matter supporting zone on chock insulator matter and array base palte produces friction, can produce electrostatic, electrostatic can exist chock insulator matter periphery, and then affect the orientation of chock insulator matter periphery liquid crystal molecule, generation light leak.
Summary of the invention
The invention provides a kind of array base palte and preparation method thereof, produce friction in order to the chock insulator matter supporting zone solved on chock insulator matter and array base palte, fricative electrostatic can affect the orientation of chock insulator matter periphery liquid crystal molecule, the problems such as the light leak caused.
The present invention is also by a kind of display panel, and it comprises above-mentioned array base palte, for ensureing the display quality of display panel.
For solving the problems of the technologies described above; the invention provides a kind of array base palte; the top of described array base palte has a protective seam; described protective seam has a chock insulator matter supporting zone; wherein, described protective seam is provided with an electric charge transmitting layer, described electric charge transmitting layer be positioned at described chock insulator matter supporting zone at least partially; described array base palte is also provided with a static discharge unit, and described electric charge transmitting layer is electrically connected with described static discharge unit.
The present invention also provides a kind of display panel, it comprise to box arrange array base palte and color membrane substrates, described color membrane substrates is formed with chock insulator matter, and described array base palte adopts above-mentioned array base palte, and described chock insulator matter contacts with described electric charge transmitting layer and arranges.
Meanwhile, the present invention also provides a kind of method for making of array base palte, comprising:
Form an electric charge transmitting layer be electrically connected with static discharge unit on the protection layer, the chock insulator matter supporting zone be positioned at least partially on protective seam of described electric charge transmitting layer.
The beneficial effect of technique scheme of the present invention is as follows:
In technique scheme, by the chock insulator matter supporting zone on array base palte, electric charge transmitting layer is set, and the static discharge unit be electrically connected with described electric charge transmitting layer is set, thus chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be discharged, overcome the liquid crystal molecular orientation of this electrostatic to chock insulator matter periphery to have an impact, the problems such as the light leak caused.
Accompanying drawing explanation
Fig. 1 represents the structural representation of array base palte in the embodiment of the present invention;
Fig. 2 represents that in the embodiment of the present invention, display panels is along the partial sectional view in A-A direction in Fig. 1.
Embodiment
For embodiments of the invention will be solved technical matters, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Shown in composition graphs 1 and Fig. 2, for display panels, it comprises the array base palte 100 and color membrane substrates 200 that arrange box, and is filled in the liquid crystal molecule 8 between array base palte 100 and color membrane substrates 200.In order to form certain space between array base palte 100 and color membrane substrates 200, color membrane substrates 200 is formed chock insulator matter 5, position corresponding with chock insulator matter 5 on array base palte 100 is formed with chock insulator matter supporting zone, after array base palte 100 and color membrane substrates 200 pairs of boxes, chock insulator matter 5 is played a supporting role, and forms certain space.Wherein, chock insulator matter supporting zone is usually located at above grid line 20; formed by the active layer and source and drain metal level that form TFT, include active layer supporting zone 11 and source and drain metal level supporting zone 12, above source and drain metal level supporting zone 12, be formed with protective seam 103(is isolation material).
But in the course of the work, the phenomenons such as if the chock insulator matter supporting zone on chock insulator matter 5 and array base palte 100 produces friction, fricative electrostatic exists chock insulator matter 5 periphery, and then affect the orientation of chock insulator matter 5 periphery liquid crystal molecule 8, generation light leak.
Embodiment one
In order to solve the problems of the technologies described above; a kind of array base palte is provided in the embodiment of the present invention; the top of described array base palte has a protective seam; described protective seam has a chock insulator matter supporting zone; described protective seam is provided with an electric charge transmitting layer; described electric charge transmitting layer be positioned at described chock insulator matter supporting zone at least partially, described array base palte is also provided with a static discharge unit, and described electric charge transmitting layer is electrically connected with described static discharge unit.Thus chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be passed to static discharge unit through electric charge transmitting layer is discharged, can not have an impact to the orientation of the liquid crystal molecule of chock insulator matter periphery, ensure that the display quality of display panel.
Preferably, described electric charge transmitting layer covers described chock insulator matter supporting zone completely.
Further, in order to increase the surfaceness of chock insulator matter supporting zone, reduce the generation of friction, form the first via hole at the corresponding described chock insulator matter supporting zone of described protective seam in the present embodiment, described electric charge transmitting layer fills described first via hole.
In technique scheme, by the chock insulator matter supporting zone on array base palte, electric charge transmitting layer is set, and the static discharge unit be electrically connected with described electric charge transmitting layer is set, thus chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be discharged, overcome the liquid crystal molecular orientation of this electrostatic to chock insulator matter periphery to have an impact, the problems such as the light leak caused.
Due to array base palte being formed with common signal line, for providing reference voltage for array base palte.In order to reduce the manufacture craft of array base palte, can arrange described static discharge unit is described common signal line.Concrete, described protective seam is formed with the second via hole above described common signal line, exposes described common signal line, and described electric charge transmitting layer is electrically connected with described common signal line by described second via hole.
Further, the pixel electrode of described electric charge transmitting layer and described array base palte is formed by a patterning processes, thus does not need to form described electric charge transmitting layer by independent patterning processes, without the need to additionally increasing the manufacture craft of array base palte.
According to drive the direction of electric field TFT-LCD is divided into using transverse electric field as drive the TFT-LCD(of electric field as: IPS type TFT-LCD and ADS type TFT-LCD), using longitudinal electric field as drive the TFT-LCD(of electric field as: TN type TFT-LCD and ITN type TFT-LCD).
Array base palte in the present embodiment can be the array base palte of lateral electric-field type TFT-LCD, also can be the array base palte of longitudinal electric field type TFT-LCD.
The structure of array base palte in the embodiment of the present invention is illustrated below for the array base palte of ADS type TFT-LCD.
Shown in composition graphs 1 and Fig. 2, in the present embodiment, the array base palte 100 of ADS type TFT-LCD comprises underlay substrate 101, and the common signal line 10, grid line 20 and the data line 30 that are formed on underlay substrate 101, and the pixel cell limited by grid line 20 and data line 30.Pixel cell comprises TFT2, slit pixel electrode 7 and public electrode 6, public electrode 6(can be plate electrode, also can for gap electrode) be positioned at the below of pixel electrode 7, there is insulation course, and both form between the two by transparency conducting layer (as: tin indium oxide, indium zinc oxide).For bottom gate type TFT2, it comprises gate electrode (not shown), raceway groove (not shown), source electrode 3 and drain electrode 4 from top to bottom successively, source electrode 3 and drain electrode 4 are formed by source and drain metal level, raceway groove is formed by active layer, gate electrode is formed by grid metal level, is formed with gate insulation layer 102 between gate electrode and raceway groove.Wherein, common signal line 10 and grid line 20 are formed by grid metal level, specifically can (this patterning processes comprises the technique such as coating, exposure, development, etching of photoresist, and the patterning processes in following content includes above-mentioned technological process unless specified or limited otherwise by a patterning processes.) form the gate electrode of common signal line 10, grid line 20 and TFT simultaneously.Data line 30 is formed by source and drain metal level with source electrode 3 and drain electrode 4, specifically can form data line 30, source electrode 3 and drain electrode 4 by a patterning processes simultaneously.
Chock insulator matter supporting zone on array base palte 100 specifically includes active layer supporting zone 11 and source and drain metal level supporting zone 12; above source and drain metal level supporting zone 12, be formed with protective seam 103, between active layer supporting zone 11 and grid line 20, be formed with gate insulation layer 102.Wherein, active layer supporting zone 11 is formed by active layer, specifically can be formed with the raceway groove of active layer supporting zone 11 and TFT by a patterning processes simultaneously.Source and drain metal level supporting zone 12 is formed by source and drain metal level, specifically can form source and drain metal level supporting zone 12, the source electrode 3 of TFT2 and drain electrode 4 by a patterning processes simultaneously.
After formation protective seam 103, offer the first via hole 13 in the position of corresponding chock insulator matter supporting zone, expose source and drain metal level supporting zone 12.Above common signal line 10, offer the second via hole 14, expose common signal line 10.Then on protective seam 103, electrically conducting transparent layer film is formed; the pattern comprising pixel electrode 7 and electric charge transmitting layer 1 is formed by a patterning processes; electric charge transmitting layer 1 fills described first via hole 13 and the second via hole 14, and chock insulator matter supporting zone is electrically connected with common signal line 10 by electric charge transmitting layer 1 and the second via hole 14.Wherein, when there is defective workmanship in protective seam 103; arranging of first via hole 13 can also prevent chock insulator matter 5 and the excessive breakdown protection layer 103 of the fricative electrostatic of chock insulator matter supporting zone, and by problem that the signal of coupling capacitance to grid line 20 between source and drain metal level supporting zone 12 and grid line 20 has an impact.
Embodiment two
As shown in Figure 2, in the present embodiment, provide a kind of display panel, it comprise to box arrange array base palte 100 and color membrane substrates 200, wherein, array base palte 100 adopts the array base palte in embodiment one.Color membrane substrates 200 is formed with chock insulator matter 5, and chock insulator matter 5 contacts with the electric charge transmitting layer 1 on array base palte 100 and arranges, thus the fricative electrostatic of chock insulator matter supporting zone on chock insulator matter and array base palte can be passed to static discharge unit 10 through electric charge transmitting layer 1 is discharged, can not have an impact to the orientation of the liquid crystal molecule 8 of chock insulator matter 5 periphery, ensure that the display quality of display panel.
Embodiment three
Based on same inventive concept, a kind of method for making of array base palte is provided in the present embodiment, comprises:
Form an electric charge transmitting layer be electrically connected with static discharge unit on the protection layer, the chock insulator matter supporting zone be positioned at least partially on protective seam of described electric charge transmitting layer.
The static discharge unit formed by above-mentioned steps and electric charge transmitting layer, make chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be passed to static discharge unit through electric charge transmitting layer to be discharged, can not have an impact to the orientation of the liquid crystal molecule of chock insulator matter periphery, ensure that the display quality of display panel.
Preferably, described electric charge transmitting layer covers described chock insulator matter supporting zone completely.
Further, in order to increase the surfaceness of chock insulator matter supporting zone, reduce the generation of friction, the method for making in the present embodiment also comprises:
On described protective seam, corresponding described chock insulator matter supporting zone forms the first via hole, and described electric charge transmitting layer fills described first via hole.
In technique scheme, by the chock insulator matter supporting zone on array base palte, electric charge transmitting layer is set, and the static discharge unit be electrically connected with described electric charge transmitting layer is set, thus chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be discharged, overcome the liquid crystal molecular orientation of this electrostatic to chock insulator matter periphery to have an impact, the problems such as the light leak caused.
Owing to array base palte being formed with the common signal line covered by described protective seam, for providing reference voltage for array base palte.In order to additionally not increase the manufacture craft of array base palte, arranging described static discharge unit is described common signal line.Correspondingly, described method for making also comprises:
Before formation electric charge transmitting layer, described protective seam is formed the second via hole be positioned at above described common signal line, exposes described common signal line, described electric charge transmitting layer fills described second via hole.
Pass through above-mentioned steps, described electric charge transmitting layer is electrically connected with described common signal line by described second via hole, then chock insulator matter and the fricative electrostatic of chock insulator matter supporting zone can be passed to common signal line by described electric charge transmitting layer and the second via hole and discharged.
Further, the pixel electrode of described electric charge transmitting layer and described array base palte can be formed by a patterning processes, thus do not need to form described electric charge transmitting layer by independent patterning processes, without the need to additionally increasing the manufacture craft of array base palte.
Array base palte in the present embodiment can be horizontal electric field type array base palte (as: array base palte of IPS type TFT-LCD and ADS type TFT-LCD), also can be vertical electric field type array base palte (as: TN type TFT-LCD and ITN type TFT-LCD).
Shown in composition graphs 1 and Fig. 2, illustrate the manufacturing process of array base palte in the present invention below for the array base palte of ADS type TFT-LCD.
One underlay substrate 101 is provided;
Underlay substrate 101 is formed the first electrically conducting transparent layer film, and forms the public electrode 6 of array base palte 100 by first time patterning processes;
The underlay substrate 101 being formed with public electrode 6 forms grid metal layer thin film, and forms the gate electrode (not shown) of array base palte 100, common signal line 10 and grid line 20 by second time patterning processes;
The underlay substrate 101 being formed with gate electrode, common signal line 10 and grid line 20 forms gate insulation layer film 102;
The underlay substrate 101 being formed with gate insulation layer 102 is formed with active layer film, and forms raceway groove (not shown) and the active layer supporting zone 11 of TFT2 by third time patterning processes;
The underlay substrate 101 of the raceway groove and active layer supporting zone 11 that are formed with TFT2 forms source and drain metal layer thin film, and forms source electrode 3, drain electrode 4, data line 30 and source and drain metal level supporting zone 12 by the 4th patterning processes;
The underlay substrate 101 being formed with source electrode 3, drain electrode 4, data line 30 and source and drain metal level supporting zone 12 forms protective seam 103, and forms the first via hole 13 and the second via hole 14 by the 5th patterning processes;
The underlay substrate 101 being formed with protective seam 103 is formed the second electrically conducting transparent layer film, and forms pixel electrode 7 and electric charge transmitting layer 1 by the 6th patterning processes.
It should be noted that, in above-mentioned manufacturing process, the making of each pattern is not limited to above-mentioned a kind of patterning processes, such as: third time patterning processes and the 4th patterning processes can merge into a patterning processes and complete.
Below for third time patterning processes and the 4th patterning processes merge into a patterning processes and complete, the pattern how simultaneously being formed at least double-layer films by patterning processes is described.
Shown in composition graphs 2, the underlay substrate 101 being formed with gate insulation layer 102 is formed with active layer film and source and drain metal layer thin film successively;
At source and drain metal layer thin film coating photoresist;
By gray tone mask plate or half gray level mask plate, photoresist is exposed, development, form photoresist half reserve area, the complete reserve area of photoresist and photoresist not reserve area, wherein, the at least corresponding channel region of photoresist half reserve area and active layer supporting zone 11, the region at least corresponding source electrode 3 of the complete reserve area of photoresist, drain electrode 4 and data line 30 place, and source and drain metal level supporting zone 12, photoresist is reserve area other regions corresponding not;
The photoresist not active layer of reserve area and source and drain metal level is etched away by first time etching technics;
Removed the photoresist of photoresist half reserve area by cineration technics, and a thinning process is played to the photoresist of the complete reserve area of photoresist;
Etched away the source and drain metal level of photoresist half reserve area with the first thickness by second time etching technics, expose active layer, form raceway groove and the active layer supporting zone 11 of TFT;
Peel off remaining photoresist, form source electrode 3, drain electrode 4, data line 30 and source and drain metal level supporting zone 12.
In each embodiment of the method for the present invention; the sequence number of described each step can not be used for the sequencing limiting each step; for those of ordinary skill in the art, under the prerequisite not paying creative work, the priority of each step is changed also within protection scope of the present invention.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (12)
1. an array base palte, the top of described array base palte has a protective seam, described protective seam has a chock insulator matter supporting zone, it is characterized in that, described protective seam is provided with an electric charge transmitting layer, described electric charge transmitting layer be positioned at described chock insulator matter supporting zone at least partially, described array base palte is also provided with a static discharge unit, and described electric charge transmitting layer is electrically connected with described static discharge unit; Described array base palte has common signal line, and described static discharge unit is described common signal line.
2. array base palte according to claim 1, is characterized in that, described electric charge transmitting layer covers described chock insulator matter supporting zone completely.
3. array base palte according to claim 1, is characterized in that, the corresponding described chock insulator matter supporting zone of described protective seam has one first via hole, and described electric charge transmitting layer fills described first via hole.
4. the array base palte according to any one of claim 1-3, is characterized in that, described protective seam is formed with one second via hole above described common signal line, and described electric charge transmitting layer is electrically connected with described common signal line by described second via hole.
5. the array base palte according to any one of claim 1-3, is characterized in that, the pixel electrode of described electric charge transmitting layer and described array base palte is formed by a patterning processes.
6. the array base palte according to any one of claim 1-3, is characterized in that, described array base palte is horizontal electric field type array base palte.
7. a display panel, comprise the array base palte to box setting and color membrane substrates, described color membrane substrates is formed with chock insulator matter, it is characterized in that, described array base palte adopts the array base palte described in any one of claim 1-6, and described chock insulator matter contacts with described electric charge transmitting layer and arranges.
8. a method for making for array base palte, is characterized in that, comprising:
Form an electric charge transmitting layer be electrically connected with static discharge unit on the protection layer, the chock insulator matter supporting zone be positioned at least partially on protective seam of described electric charge transmitting layer; Described array base palte has common signal line, and described static discharge unit is described common signal line.
9. the method for making of array base palte according to claim 8, is characterized in that, described electric charge transmitting layer covers described chock insulator matter supporting zone completely.
10. the method for making of array base palte according to claim 8, is characterized in that, also comprises:
Corresponding described chock insulator matter supporting zone forms the first via hole on the protection layer, and described electric charge transmitting layer fills described first via hole.
The method for making of 11. array base paltes according to Claim 8 described in-10 any one, it is characterized in that, described protective seam covers described common signal line;
Described method for making also comprises:
Before formation electric charge transmitting layer, described protective seam forms the second via hole be positioned at above described common signal line;
In the step of the electric charge transmitting layer that described formation one is on the protection layer electrically connected with static discharge unit, described electric charge transmitting layer is electrically connected with described common signal line by described second via hole.
The method for making of 12. array base paltes according to Claim 8 described in-10 any one, is characterized in that, comprising:
The pixel electrode of described electric charge transmitting layer and described array base palte is formed by patterning processes.
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| CN104330925A (en) * | 2014-12-01 | 2015-02-04 | 合肥鑫晟光电科技有限公司 | Display panel and preparation method thereof as well as display device |
| CN107918220A (en) * | 2017-11-16 | 2018-04-17 | 京东方科技集团股份有限公司 | Display panel and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1727975A (en) * | 2004-07-30 | 2006-02-01 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and manufacturing method thereof |
| KR20070025153A (en) * | 2005-08-31 | 2007-03-08 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and the fabrication method |
| CN101201514A (en) * | 2006-12-11 | 2008-06-18 | Lg.菲利浦Lcd株式会社 | Electrostatic discharge protection element, liquid crystal display device having the same, and manufacturing method thereof |
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| JP4723283B2 (en) * | 2005-05-19 | 2011-07-13 | シチズンホールディングス株式会社 | Manufacturing method of liquid crystal panel |
| JP5093724B2 (en) * | 2007-10-29 | 2012-12-12 | Ｎｌｔテクノロジー株式会社 | Liquid crystal display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1727975A (en) * | 2004-07-30 | 2006-02-01 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and manufacturing method thereof |
| KR20070025153A (en) * | 2005-08-31 | 2007-03-08 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and the fabrication method |
| CN101201514A (en) * | 2006-12-11 | 2008-06-18 | Lg.菲利浦Lcd株式会社 | Electrostatic discharge protection element, liquid crystal display device having the same, and manufacturing method thereof |
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