CN103698911A - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- CN103698911A CN103698911A CN201310662062.4A CN201310662062A CN103698911A CN 103698911 A CN103698911 A CN 103698911A CN 201310662062 A CN201310662062 A CN 201310662062A CN 103698911 A CN103698911 A CN 103698911A
- Authority
- CN
- China
- Prior art keywords
- data line
- line
- grid
- line test
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses an array substrate and a display device, which aims at improving the reliability of the detection and analysis of a poor phenomenon of the array substrate. The array substrate comprises a plurality of grid line groups, a plurality of grid driving circuits, a plurality of grid line test control lines and a plurality of thin film transistors for grid line testing, wherein each grid line group links to each other with each grid driving circuit one-to-one, the grid line test control lines are in one-to-one correspondence with the grid driving circuits, each thin film transistor and each grid line of each grid line group is connected one to one correspondence, each grid line is connected with a drain of the corresponding thin film transistor for grid line testing, and a grid of the thin film transistor for grid line testing, connected with the grid line of each grid line group, is connected with one end of each grid line test control line.
Description
Technical field
The present invention relates to display technique field, relate in particular to a kind of array base palte and display device.
Background technology
In display technique field, panel display apparatus, as liquid crystal display (Liquid Crystal Display, LCD) and display of organic electroluminescence (Organic Light Emitting Display, OLED) because it has light, thin, low-power consumption, high brightness, and the advantage such as high image quality, in technical field of flat panel display, occupy consequence.
Display device at least comprises the array base palte that is provided with pel array, usually, the viewing area of array base palte is provided with grid line, data line, and is positioned at pixel electrode of pixel region etc., also comprises the gate driver circuit and the source electrode drive circuit that are positioned on outer peripheral areas or circuit board.
Prior art, along with the continuous increase of function and the size of display device, conventionally by a plurality of gate driver circuits are set, and/or arranges a plurality of source electrode drive circuits and meets the requirement that high quality image shows.
In array base palte production run, when the functional module on array base palte exists defect, in procedure for displaying, there will be various relevant with array base palte bad.For example, the demonstration that grid line and/or broken data wire cause is bad, and the demonstration of gate driver circuit and/or source electrode drive circuit defect lead-in wire is bad.
Therefore, the array base palte completing bad carried out accurately detecting extremely important, the reliability of bad determination and analysis is extremely important.
Bad for fear of the demonstration relevant with array base palte, carry out next step operation after having made array base palte before, pair array substrate carries out a screen test (Cell Test), and detection arrays substrate causes bad reason.
If gate driver circuit and source electrode drive circuit are realized by chip (IC).Wherein, for test, whether a certain IC there is defect, and existing way is: test exists IC and removes in two kinds of situations of IC, and whether the image of display panel corresponding region shows consistent.
Existingly need to test a certain IC and whether have defect, by removing IC, the mode of adscititious DC current is tested, particularly, remove a certain IC, the region of exposing grid line or data line at this IC of removal applies elargol, be that elargol is all connected the grid line being connected with described IC or data line, external lead wire on elargol, by grid line or the data line input signal of this lead-in wire for being connected with elargol, whether test shows normal without the situation hypograph of IC.
There is following defect in the method for above-mentioned test I C, first the use of elargol causes testing cost to increase, and the homogeneity that elargol applies on grid line and data line can affect test effect, is unfavorable for accurately judging the defect of IC.
Prior art, a kind of improved array base palte is, testing film transistor is set on array base palte, be called for short test TFT, the source electrode of test TFT is connected with tested grid line or data line with calibrating terminal respectively with drain electrode, by controlling the level signal of the test control line being connected with the grid of test TFT, control opening and shutting off of test TFT.Opening and shutting off by a test control line of the test TFT that all grid lines existing and on array base palte are corresponding controlled, during the corresponding a plurality of grid drive IC of all grid lines.If when wanting to test a certain IC and whether having defect, when test control line starts test TFT corresponding to the IC tested with this, start the test TFT corresponding with other IC simultaneously, viewing area on the array base palte that other IC are controlled has impact, determine and the reliability of the bad phenomenon that parses lower.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and display device, in order to improve the reliability of the determination and analysis of pair array substrate bad phenomenon.
The array base palte that the embodiment of the present invention provides comprises: comprise a plurality of grid line groups and a plurality of gate driver circuit, each grid line group is corresponding connected one by one with each gate driver circuit, also comprises:
Many and described gate driver circuit grid line test one to one control line;
Each grid line in a plurality of and described each grid line group is corresponding connected grid line test thin film transistor (TFT) one by one;
Wherein, each grid line is connected with the drain electrode of thin film transistor (TFT) with corresponding grid line test; The grid line test being connected with grid line in each grid line group is connected with one end of each grid line test control line with the grid of thin film transistor (TFT).
Preferably, also comprise grid line test control end being connected with the other end of described each grid line test control line respectively.
Preferably, each grid line test control line is connected with grid line test control end of one of them setting simultaneously.
Preferably, also comprise: many with thin film transistor (TFT) corresponding connected grid line test signal line one by one for described each grid line test, with grid line test signal line corresponding connected grid line calibrating terminal one by one;
One end of described grid line test signal line is connected with the source electrode of thin film transistor (TFT) with grid line test, and the other end is connected with described grid line calibrating terminal.
Preferably, described gate driver circuit is grid drive chip IC or the capable driving of array base palte GOA circuit.
Preferably, also comprise: a plurality of data line group and a plurality of source electrode drive circuit, each data line group is corresponding connected one by one with each source electrode drive circuit, also comprises:
Many and described source electrode drive circuit data line test one to one control line;
A plurality of each data lines with each data line group are corresponding connected data line test thin film transistor (TFT) one by one;
Wherein, each data line is connected with the drain electrode of thin film transistor (TFT) with corresponding data line test; The data line test being connected with data line in each data line group is connected with one end of each data line test control line with the source electrode of thin film transistor (TFT).
Preferably, also comprise data line test control end being connected with the other end of described each data line test control line respectively.
Preferably, pieces of data line test control line is also connected with data line test control end of one of them setting simultaneously.
Preferably, also comprise: many with thin film transistor (TFT) corresponding connected data line test signal line one by one for described each data line test, with data line test signal line corresponding connected data line calibrating terminal one by one;
One end of described data line test signal line is connected with the source electrode of thin film transistor (TFT) with data line test, and the other end is connected with described data line calibrating terminal.
The embodiment of the present invention provides a kind of display device, comprises the array base palte of above-mentioned either type.
The embodiment of the present invention provides another kind of array base palte, comprising: a plurality of data line group and a plurality of source electrode drive circuit, and each data line group is corresponding connected one by one with each source electrode drive circuit, also comprises:
Many and described source electrode drive circuit data line test one to one control line;
A plurality of each data lines with each data line group are corresponding connected data line test thin film transistor (TFT) one by one;
Wherein, each data line is connected with the drain electrode of thin film transistor (TFT) with corresponding data line test; The data line test being connected with data line in each data line group is connected with one end of each data line test control line with the source electrode of thin film transistor (TFT).
Preferably, also comprise data line test control end being connected with the other end of described each data line test control line respectively.
Preferably, pieces of data line test control line is also connected with data line test control end of one of them setting simultaneously.
Preferably, also comprise: many with thin film transistor (TFT) corresponding connected data line test signal line one by one for described each data line test, with data line test signal line corresponding connected data line calibrating terminal one by one;
One end of described data line test signal line is connected with the source electrode of thin film transistor (TFT) with data line test, and the other end is connected with described data line calibrating terminal.
The embodiment of the present invention provides another kind of display device, comprises described another kind of array base palte.
The embodiment of the present invention is by providing a kind of grid line test control line and data line test control line of testing grid line or data line.The grid line test quantity of control line and the quantity of gate driver circuit are consistent, the corresponding grid line test of a gate driver circuit control line; Each grid line test control line is controlled when needed respectively corresponding grid line test and is opened with thin film transistor (TFT).In like manner, the data line test quantity of control line and the quantity of source electrode drive circuit are consistent, the corresponding data line test of a source electrode drive circuit control line; Each data line test control line is controlled when needed respectively corresponding data line test and is opened with thin film transistor (TFT).Avoided prior art by elargol and external lead wire test grid line or data line, and can only be for data line provides GTG signal while having avoided prior art test data line, the lower problem of reliability of the failure analysis that rgb signal causes cannot be provided.
Accompanying drawing explanation
One of array base-plate structure schematic diagram that Fig. 1 provides for the embodiment of the present invention one;
Two of the array base-plate structure schematic diagram that Fig. 2 provides for the embodiment of the present invention one:
Fig. 3 is the structure partial enlarged diagram in the a-quadrant shown in Fig. 2;
The grid line that Fig. 4 provides for the embodiment of the present invention one is tested the structural representation of control line;
Three of the array base-plate structure schematic diagram that Fig. 5 provides for the embodiment of the present invention one;
One of array base-plate structure schematic diagram that Fig. 6 provides for the embodiment of the present invention two;
Two of the array base-plate structure schematic diagram that Fig. 7 provides for the embodiment of the present invention two:
Three of the array base-plate structure schematic diagram that Fig. 8 provides for the embodiment of the present invention two;
The data line that Fig. 9 provides for the embodiment of the present invention two is tested the structural representation of control line.
Embodiment
The embodiment of the present invention provides a kind of array base palte and display device, in order to improve the reliability of the determination and analysis of pair array substrate bad phenomenon.
The present invention is by being array base palte setting and each driving circuit (at least comprising gate driver circuit and source electrode drive circuit) many test control lines one to one, this test control line is used for controlling test opening and shutting off with thin film transistor (TFT) (TFT), realize some driving circuits of test separately or test grid that certain one drive circuit is corresponding or data line and do not affect other driving circuits or the grid line being connected with other driving circuits or the object of data line, thereby improve the reliability of the determination and analysis of pair array substrate bad phenomenon.
The array base palte that the embodiment of the present invention provides can be realized the detection to grid line or gate driver circuit, and/or realizes the detection to data line or source electrode drive circuit.
To for test grid line and data line, the array base palte that the embodiment of the present invention provides be described respectively below.
Embodiment mono-:
Referring to Fig. 1, the array base palte that the embodiment of the present invention provides, comprising:
A plurality of grid line groups 1, each grid line group 1 comprises many grid lines 11;
A plurality of gate driver circuits 2; Each grid line group 1 is corresponding connected one by one with each gate driver circuit 2, and gate driver circuit 2 is for driving the grid line 11 being attached thereto;
Also comprise: many and gate driver circuit 2 grid line test one to one control line 3;
A plurality of each grid lines 11 with each grid line group 1 are corresponding connected grid line thin film transistor (TFT) 12 for test one by one;
Wherein, each grid line 11 is connected with the drain electrode of thin film transistor (TFT) 12 with corresponding grid line test; The grid line test being connected with grid line 1 in each grid line group is connected with one end of each grid line test control line 3 with the grid of thin film transistor (TFT) 12.
It should be noted that, the array base palte shown in Fig. 1, grid line 11, gate driver circuit 2, grid line test are all positioned at the region outside array base palte viewing area with thin film transistor (TFT) 12 and grid line test control line 3, and this region also claims outer peripheral areas.
Fig. 1 schematically demonstrates three gate driver circuits 2, every three grid lines 11 form a grid line group 1, each grid line test control line 3 is only connected with the grid line 11 in a grid line group 1, controls the unlatching of the TFT12 being connected with this grid line group or closes; The grid line test connected with grid line group 1 is corresponding with a gate driver circuit 2 with thin film transistor (TFT) 12.
That is to say, grid line test control line 3 is corresponding one by one with grid line group 1, and grid line test control line 3 is corresponding one by one with gate driver circuit 2.
The array base palte that the above embodiment of the present invention provides, thin film transistor (TFT) 12 and many grid lines test control lines 3 for the grid line connecting one to one with the grid line test of outer peripheral areas setting, each grid line test control line 3 is only controlled the grid line corresponding with gate driver circuit 2 and is tested and use thin film transistor (TFT) 12.
In specific implementation process, array base palte is after completing, after box technique, need pair array substrate to carry out a screen test (Cell Test), viewing area corresponding to each gate driver circuit that is pair array substrate tested, when there is bad phenomenon in a certain region demonstration of test result embodiment viewing area, need to test for wherein one or more gate driver circuits, verify whether described bad phenomenon causes because gate driver circuit exists defect.Each gate driver circuit needs successively checking one by one.
The present invention is when needing a certain gate driver circuit 2 shown in proof diagram 1 whether to have defect, this gate driver circuit 2 is got rid of, by the grid line test control line 3 corresponding with this gate driver circuit 2, controlling the grid line test being connected with this grid line test control line 3 opens with thin film transistor (TFT) 12, from the grid line test being opened, with the source electrode of thin film transistor (TFT) 12, input corresponding test signal, whether test display screen there is above-mentioned bad phenomenon, if there is bad phenomenon identical while testing with some screen, gate driver circuit 2 zero defects that explanation is got rid of.From the above, the grid line test not corresponding with the gate driver circuit 2 of getting rid of is not opened with thin film transistor (TFT) 12, and the viewing area image on corresponding array base palte shows unaffected.
Describedly from the grid line test being opened, with the source electrode of thin film transistor (TFT) 12, input corresponding test signal, this test signal can be the driving signal of driven grid line.
Further, referring to Fig. 2, array base palte shown in Fig. 1 also comprises: grid line test control end 31 being connected with the other end of each grid line test control line 3 respectively, this grid line test control end 31 is used to the grid line test control line 3 being attached thereto that control signal is provided, and this control signal can be controlled grid line test with the unlatching of thin film transistor (TFT) 12 or close.
Above-mentionedly be mentioned to, before whether a certain gate driver circuit 2 of test exists defect, need pair array substrate to carry out a screen test (Cell Test).Need to open the grid line test thin film transistor (TFT) 12 of grid line 11 correspondences in each grid line group 1 simultaneously, to the grid line test of having opened, with thin film transistor (TFT) 12 input data signals, realize a screen test simultaneously.Realize the grid line test during with thin film transistor (TFT) 12 simultaneously open grid line 11 correspondences in each grid line group 1, need to open grid line test control end 31 work connected with each grid line test control line 3 simultaneously and with thin film transistor (TFT) 12, provide cut-in voltage for corresponding grid line test.
Because each grid line test can be identical with the cut-in voltage of thin film transistor (TFT) 12, therefore, the present invention is on the array base palte shown in Fig. 2, further, referring to Fig. 2, each grid line test control line 3 is connected with grid line test control end 31 of one of them setting simultaneously.When thin film transistor (TFT) 12 is used in the grid line test of grid line 11 correspondences in need to simultaneously opening each grid line group 1, only need to open grid line test control end 31 of setting, this set-up mode can reduce the power consumption of array base palte, reduces the serviceable life of other grid line test control end 31.
Fig. 3 is the local enlarged diagram of the a-quadrant shown in Fig. 2, and as shown in Figure 3, each grid line test control line 3 is the SW shown in Fig. 3 with the sub-31(of grid line test control end of one of them setting simultaneously) be connected.
When carrying out some screen test, by the grid line test control end son 31 of setting, all grid line tests to be opened with thin film transistor (TFT) 12, the image of realizing whole viewing area shows.After carrying out a screen test, each grid line test control line 3 and grid line test control end 31 of setting are disconnected, specifically can grid line be tested to control line 3 by laser cuts open with grid line test control end 31 parts that are connected of setting, by grid line, test control line 3 and control thin film transistor (TFT) 12 unlatchings for corresponding with it grid line test, all the other grid line tests are closed with thin film transistor (TFT) 12, to improve the reliability of failure analysis.
Each shown in Fig. 3 grid line test control line 3 and grid line test control end 31 are only a kind of examples, and are not used in the concrete structure of each grid line test control line 3 of explanation and grid line test control end 31.
In specific implementation process, each grid line test control line 3 and grid line test control end 31 can be set to the structure shown in Fig. 4.Referring to Fig. 4, a wire can be set between each gate driver circuit and grid line, this wire is divided into multistage wire, each section lead is as a grid line test control line 3; One end of each section lead 3 32 is connected to grid line test control end 31 by going between.
Each grid line test control line 3 is by the SW in sub-31(Fig. 4 of grid line test control end of lead-in wire 32 and setting) be connected.
Referring to Fig. 5, the array base palte that the embodiment of the present invention provides, on the basis of the array base palte shown in the array base palte shown in Fig. 1 or Fig. 2, also further comprises:
Many with thin film transistor (TFT) 12 corresponding connected grid line test signal line 4 one by one for the test of each grid line, with grid line test signal line 4 corresponding connected grid line calibrating terminal 41 one by one;
One end of grid line test signal line 4 is connected with the source electrode of thin film transistor (TFT) 12 with grid line test, and the other end is connected with grid line calibrating terminal 41.
Grid line calibrating terminal 41 is tested and is provided test signal with the source electrode of thin film transistor (TFT) 12 for grid line by grid line test signal line 4.
The gate driver circuit that the above embodiment of the present invention provides can be grid drive chip IC or array base palte horizontal drive circuit (Gate On Array circuit is called for short GOA circuit).
Array base palte shown in Fig. 5, can only arrange a grid line test signal line 4 and be connected with the source electrode of thin film transistor (TFT) 12 with all grid line tests.At a screen test phase, when the test of all grid line is opened with thin film transistor (TFT) 12, by a grid line test signal line 4, just can drive in viewing area each pixel to realize image and show.
Embodiment bis-:
Referring to Fig. 6, the array base palte that the embodiment of the present invention two provides, comprising:
A plurality of data line group 5 and a plurality of source electrode drive circuit 6, the data line 5 in each data line group comprises many data lines 51, each data line group 5 is corresponding connected one by one with each source electrode drive circuit 6, also comprises:
Many and source electrode drive circuit 6 data line test one to one control line 7;
A plurality of each data lines 51 with each data line group 5 are corresponding connected data line thin film transistor (TFT) 52 for test one by one;
Wherein, each data line 51 is connected with the drain electrode of thin film transistor (TFT) 52 with corresponding data line test; The data line test being connected with data line 51 in each data line group 1 is connected with one end of each data line test control line 7 with the source electrode of thin film transistor (TFT) 52.
The present invention is when needing a certain source electrode drive circuit 6 shown in proof diagram 6 whether to have defect, this source electrode drive circuit 6 is got rid of, by the data line test control line 7 corresponding with this source electrode drive circuit 6, controlling the data line test being connected with this data line test control line 7 opens with thin film transistor (TFT) 52, from the data line test being opened, with the source electrode of thin film transistor (TFT) 52, input corresponding test signal, whether test display screen there is above-mentioned bad phenomenon, if there is bad phenomenon identical while testing with some screen, source electrode drive circuit 6 zero defects that explanation is got rid of.From the above, the data line test not corresponding with the source electrode drive circuit 6 of getting rid of is not opened with thin film transistor (TFT) 52, and the image on corresponding array base palte shows unaffected.
Describedly from the data line test being opened, with the source electrode of thin film transistor (TFT) 52, input corresponding test signal, this test signal can be source drive signal, for example this test signal can be GTG signal, can be also signal corresponding to rgb pixels (being rgb signal); When test signal is signal corresponding to rgb pixels, the input of the signal data of the data line (being called for short DB) that the data line (being called for short DR) that independently control red pixel is corresponding, the data line (being called for short DG) that green pixel is corresponding and blue pixel are corresponding, the reliability of raising failure analysis.
Further, referring to Fig. 7, on the basis of the array base palte shown in Fig. 6, also comprise:
Data line test control end 71 being connected with the other end of each data line test control line 7 respectively.Data line test control end 71 is used to data line test control line 7 that signal is provided, and this control signal can be controlled data line test with the unlatching of thin film transistor (TFT) 52 or close.
During concrete enforcement, before whether a certain source electrode drive circuit 6 of test exists defect, need pair array substrate to carry out a screen test (Cell Test).Need to open the data line test thin film transistor (TFT) 52 of data line 51 correspondences in each data line group 5 simultaneously.
In order to realize the thin film transistor (TFT) 52 of turn-on data line test simultaneously, referring to Fig. 7, pieces of data line test control line 7 is also connected with data line test control end 71 of one of them setting simultaneously, as data line test control end 71 of the SW in Fig. 7 for setting.
When carrying out some screen test, by the data line test control end son 71 of setting, all data line tests to be opened with thin film transistor (TFT) 52, the image of realizing whole viewing area shows.After carrying out a screen test, each data line test control line 7 and data line test control end 71 of setting are disconnected, specifically can data line be tested to control line 7 by laser cuts open with data line test control end 71 parts that are connected of setting, by data line, test control line 7 and control thin film transistor (TFT) 52 unlatchings for corresponding with it data line test, the test of remainder data line is closed with thin film transistor (TFT) 52, to improve the reliability of failure analysis.
Referring to Fig. 8, on the basis of the array base palte shown in Fig. 6 or Fig. 7, also comprise:
Many with thin film transistor (TFT) 52 corresponding connected data line test signal line 8 one by one for the test of each data line, with data line test signal line 8 corresponding connected data line calibrating terminal 81 one by one;
One end of data line test signal line 8 is connected with the source electrode of thin film transistor (TFT) 52 with data line test, and the other end is connected with data line calibrating terminal 81.
Array base palte shown in Fig. 8, can only arrange a data line test signal line 8 and be connected with the source electrode of thin film transistor (TFT) 52 with all data line tests.At a screen test phase, when the test of all data line is opened with thin film transistor (TFT) 52, by a data line test signal line 8, just can drive in viewing area each pixel to realize image and show.
Array base palte shown in Fig. 6 to Fig. 8, data line is tested control line 7 and can be set to as shown in Figure 9 according to line test control end 71.
Embodiment tri-:
Comprise the array base palte of above-described embodiment one either type and the array base palte of embodiment bis-either types.Be that grid line, data line, gate driver circuit and source electrode drive circuit are set on array base palte simultaneously, be also provided with for testing thin film transistor (TFT) and data line test thin film transistor (TFT), grid line test control line and grid line test signal line, data line test control line and the data line test signal line etc. for grid line test of grid line and data line simultaneously.
The embodiment of the present invention is by providing a kind of grid line test control line and data line test control line of testing grid line or data line.The grid line test quantity of control line and the quantity of gate driver circuit are consistent, the corresponding grid line test of a gate driver circuit control line; Each grid line test control line is controlled when needed respectively corresponding grid line test and is opened with thin film transistor (TFT).In like manner, the data line test quantity of control line and the quantity of source electrode drive circuit are consistent, the corresponding data line test of a source electrode drive circuit control line; Each data line test control line is controlled when needed respectively corresponding data line test and is opened with thin film transistor (TFT).Avoided prior art by elargol and external lead wire test grid line or data line, and can only be for data line provides GTG signal while having avoided prior art test data line, the lower problem of reliability of the failure analysis that rgb signal causes cannot be provided.
The embodiment of the present invention also provides a kind of display device, comprises the array base palte that above-described embodiment three provides.
The embodiment of the present invention also provides another kind of display device, comprises the array base palte that above-described embodiment one provides; Or comprise the array base palte that above-described embodiment two provides.
Obviously, those skilled in the art can carry out various changes and distortion and not depart from the spirit and scope of the present invention the present invention.Like this, if within these modifications of the present invention and distortion belong to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and distortion interior.
Claims (15)
1. an array base palte, comprises a plurality of grid line groups and a plurality of gate driver circuit, and each grid line group is corresponding connected one by one with each gate driver circuit, it is characterized in that, also comprises:
Many and described gate driver circuit grid line test one to one control line;
Each grid line in a plurality of and described each grid line group is corresponding connected grid line test thin film transistor (TFT) one by one;
Wherein, each grid line is connected with the drain electrode of thin film transistor (TFT) with corresponding grid line test; The grid line test being connected with grid line in each grid line group is connected with one end of each grid line test control line with the grid of thin film transistor (TFT).
2. array base palte according to claim 1, is characterized in that, also comprises grid line test control end being connected with the other end of described each grid line test control line respectively.
3. array base palte according to claim 2, is characterized in that, each grid line test control line is connected with grid line test control end of one of them setting simultaneously.
4. array base palte according to claim 3, is characterized in that, also comprises: many with thin film transistor (TFT) corresponding connected grid line test signal line one by one for described each grid line test, with grid line test signal line corresponding connected grid line calibrating terminal one by one;
One end of described grid line test signal line is connected with the source electrode of thin film transistor (TFT) with grid line test, and the other end is connected with described grid line calibrating terminal.
5. array base palte according to claim 4, is characterized in that, described gate driver circuit is grid drive chip IC or the capable driving of array base palte GOA circuit.
6. according to the arbitrary described array base palte of claim 1-5, also comprise: a plurality of data line group and a plurality of source electrode drive circuit, each data line group is corresponding connected one by one with each source electrode drive circuit, it is characterized in that, also comprises:
Many and described source electrode drive circuit data line test one to one control line;
A plurality of each data lines with each data line group are corresponding connected data line test thin film transistor (TFT) one by one;
Wherein, each data line is connected with the drain electrode of thin film transistor (TFT) with corresponding data line test; The data line test being connected with data line in each data line group is connected with one end of each data line test control line with the source electrode of thin film transistor (TFT).
7. array base palte according to claim 6, is characterized in that, also comprises data line test control end being connected with the other end of described each data line test control line respectively.
8. array base palte according to claim 7, is characterized in that, pieces of data line test control line is also connected with data line test control end of one of them setting simultaneously.
9. array base palte according to claim 8, it is characterized in that, also comprise: many with thin film transistor (TFT) corresponding connected data line test signal line one by one for described each data line test, with data line test signal line corresponding connected data line calibrating terminal one by one;
One end of described data line test signal line is connected with the source electrode of thin film transistor (TFT) with data line test, and the other end is connected with described data line calibrating terminal.
10. an array base palte, comprising: a plurality of data line group and a plurality of source electrode drive circuit, and each data line group and each source electrode drive circuit be corresponding being connected one by one, it is characterized in that, also comprises:
Many and described source electrode drive circuit data line test one to one control line;
A plurality of each data lines with each data line group are corresponding connected data line test thin film transistor (TFT) one by one;
Wherein, each data line is connected with the drain electrode of thin film transistor (TFT) with corresponding data line test; The data line test being connected with data line in each data line group is connected with one end of each data line test control line with the source electrode of thin film transistor (TFT).
11. array base paltes according to claim 10, is characterized in that, also comprise data line test control end being connected with the other end of described each data line test control line respectively.
12. array base paltes according to claim 11, is characterized in that, pieces of data line test control line is also connected with data line test control end of one of them setting simultaneously.
13. array base paltes according to claim 12, it is characterized in that, also comprise: many with thin film transistor (TFT) corresponding connected data line test signal line one by one for described each data line test, with data line test signal line corresponding connected data line calibrating terminal one by one;
One end of described data line test signal line is connected with the source electrode of thin film transistor (TFT) with data line test, and the other end is connected with described data line calibrating terminal.
14. 1 kinds of display device, is characterized in that, comprise the array base palte described in the arbitrary claim of claim 1-9.
15. 1 kinds of display device, is characterized in that, comprise the array base palte described in the arbitrary claim of claim 10-13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310662062.4A CN103698911A (en) | 2013-12-09 | 2013-12-09 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310662062.4A CN103698911A (en) | 2013-12-09 | 2013-12-09 | Array substrate and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103698911A true CN103698911A (en) | 2014-04-02 |
Family
ID=50360495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310662062.4A Pending CN103698911A (en) | 2013-12-09 | 2013-12-09 | Array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103698911A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995407A (en) * | 2014-05-08 | 2014-08-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN105590607A (en) * | 2016-03-10 | 2016-05-18 | 京东方科技集团股份有限公司 | Gate driving circuit, testing method thereof, array substrate comprising gate driving circuit, and display device comprising array substrate |
| CN105590572A (en) * | 2015-12-21 | 2016-05-18 | 上海中航光电子有限公司 | Display device and display-testing method |
| CN106601174A (en) * | 2017-01-03 | 2017-04-26 | 京东方科技集团股份有限公司 | Shift register, driving method, GOA circuit and display device |
| CN109147633A (en) * | 2018-10-18 | 2019-01-04 | 合肥鑫晟光电科技有限公司 | Display panel detection circuit and detection method, array substrate |
| CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
| CN111445834A (en) * | 2020-05-12 | 2020-07-24 | 京东方科技集团股份有限公司 | Display substrate, display panel and test method of display panel |
| CN112103199A (en) * | 2019-06-17 | 2020-12-18 | 京东方科技集团股份有限公司 | Display substrate, display device and performance test method of transistor |
| CN113763850A (en) * | 2021-09-14 | 2021-12-07 | 深圳创维－Rgb电子有限公司 | Bad vertical line positioning circuit and method, display module and television |
| WO2022061543A1 (en) * | 2020-09-22 | 2022-03-31 | 京东方科技集团股份有限公司 | Display substrate and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412735A (en) * | 2001-10-11 | 2003-04-23 | 三星电子株式会社 | Film transistor array panel with visual checking device and its checking method |
| US20050146349A1 (en) * | 2004-01-02 | 2005-07-07 | Ming-Sheng Lai | [testing apparatus for flat-panel display] |
| KR20050087233A (en) * | 2004-02-26 | 2005-08-31 | 삼성전자주식회사 | Thin film transistor substrate and method of manufacturing the same |
| CN102540595A (en) * | 2010-12-31 | 2012-07-04 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal panel |
| CN103345080A (en) * | 2013-07-10 | 2013-10-09 | 深圳市华星光电技术有限公司 | Rapid test switching device and corresponding TFT-LCD array substrate |
-
2013
- 2013-12-09 CN CN201310662062.4A patent/CN103698911A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412735A (en) * | 2001-10-11 | 2003-04-23 | 三星电子株式会社 | Film transistor array panel with visual checking device and its checking method |
| US20050146349A1 (en) * | 2004-01-02 | 2005-07-07 | Ming-Sheng Lai | [testing apparatus for flat-panel display] |
| KR20050087233A (en) * | 2004-02-26 | 2005-08-31 | 삼성전자주식회사 | Thin film transistor substrate and method of manufacturing the same |
| CN102540595A (en) * | 2010-12-31 | 2012-07-04 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal panel |
| CN103345080A (en) * | 2013-07-10 | 2013-10-09 | 深圳市华星光电技术有限公司 | Rapid test switching device and corresponding TFT-LCD array substrate |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995407B (en) * | 2014-05-08 | 2016-08-24 | 京东方科技集团股份有限公司 | Array base palte and display floater |
| US9720297B2 (en) | 2014-05-08 | 2017-08-01 | Boe Technology Group Co., Ltd. | Array substrate for improving the speed of discharge of storage capacitance corresponding to a pixel electrode, and display panel having the same |
| CN103995407A (en) * | 2014-05-08 | 2014-08-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN105590572A (en) * | 2015-12-21 | 2016-05-18 | 上海中航光电子有限公司 | Display device and display-testing method |
| CN105590607A (en) * | 2016-03-10 | 2016-05-18 | 京东方科技集团股份有限公司 | Gate driving circuit, testing method thereof, array substrate comprising gate driving circuit, and display device comprising array substrate |
| CN105590607B (en) * | 2016-03-10 | 2018-09-14 | 京东方科技集团股份有限公司 | Gate driving circuit and its detection method, array substrate, display device |
| US10241145B2 (en) | 2016-03-10 | 2019-03-26 | Boe Technology Group Co., Ltd. | Gate driving circuit and method for detecting same, array substrate and display apparatus |
| CN106601174A (en) * | 2017-01-03 | 2017-04-26 | 京东方科技集团股份有限公司 | Shift register, driving method, GOA circuit and display device |
| CN106601174B (en) * | 2017-01-03 | 2019-12-17 | 京东方科技集团股份有限公司 | Shift register, driving method, GOA circuit and display device |
| CN109147633B (en) * | 2018-10-18 | 2022-05-20 | 合肥鑫晟光电科技有限公司 | Display panel detection circuit and detection method and array substrate |
| CN109147633A (en) * | 2018-10-18 | 2019-01-04 | 合肥鑫晟光电科技有限公司 | Display panel detection circuit and detection method, array substrate |
| CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
| CN112103199A (en) * | 2019-06-17 | 2020-12-18 | 京东方科技集团股份有限公司 | Display substrate, display device and performance test method of transistor |
| CN112103199B (en) * | 2019-06-17 | 2024-02-23 | 京东方科技集团股份有限公司 | Display substrate, display device and performance test method of transistor |
| CN111445834A (en) * | 2020-05-12 | 2020-07-24 | 京东方科技集团股份有限公司 | Display substrate, display panel and test method of display panel |
| WO2022061543A1 (en) * | 2020-09-22 | 2022-03-31 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US11917891B2 (en) | 2020-09-22 | 2024-02-27 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display apparatus |
| CN113763850A (en) * | 2021-09-14 | 2021-12-07 | 深圳创维－Rgb电子有限公司 | Bad vertical line positioning circuit and method, display module and television |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103698911A (en) | Array substrate and display device | |
| US9990873B2 (en) | Display apparatus and method of testing the same | |
| US9898944B2 (en) | Detecting circuit, detecting method and display device | |
| JP5624743B2 (en) | Switch control unit, liquid crystal cell post-assembly inspection apparatus and method | |
| CN107942547B (en) | Lighting and back lighting fixture and method for detecting panel | |
| JP5709457B2 (en) | Liquid crystal display device and method for inspecting liquid crystal display device | |
| US11017699B2 (en) | Display panel and display device including lighting test circuit | |
| US20160140896A1 (en) | Display device | |
| US11145231B2 (en) | Test circuit and display device | |
| US10643514B2 (en) | Display device with inspection transistor and method for inspecting display device | |
| CN102621721A (en) | Liquid crystal panel, liquid crystal module and method for clarifying reasons resulting in poor screen images thereof | |
| JP2007108754A (en) | Display device and testing method for the same | |
| KR102462070B1 (en) | Display panel and the method for inspecting therof | |
| KR20160102518A (en) | Wiring structure of array substrate | |
| WO2019184351A1 (en) | Test apparatus and test method | |
| CN101344650A (en) | Test device of display device, test method and substrate with test device | |
| US9395564B2 (en) | Liquid crystal display device and method for repairing the same | |
| US11538430B2 (en) | Display device and inspection method therefor | |
| US20180090041A1 (en) | Panel testing unit, array substrate and liquid crystal display device | |
| KR101746860B1 (en) | Liquid Crystal Display device and Inspection Method thereof | |
| KR101649220B1 (en) | Inspection device of Liquid Crystal Display device | |
| KR20070046238A (en) | Liquid crystal display device | |
| US10885820B2 (en) | Pixel inspection method, pixel inspection device, and display device | |
| KR20120046972A (en) | Testing apparatus and method for timming controller of liquid crystal display device | |
| CN107064773A (en) | ATE voltage testing systems and ATE voltage test methods |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140402 |