CN103697874B - A kind of quartz digital tuning fork gyroscope drives loop control circuit - Google Patents
A kind of quartz digital tuning fork gyroscope drives loop control circuit Download PDFInfo
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- CN103697874B CN103697874B CN201310741034.1A CN201310741034A CN103697874B CN 103697874 B CN103697874 B CN 103697874B CN 201310741034 A CN201310741034 A CN 201310741034A CN 103697874 B CN103697874 B CN 103697874B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
- G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
- G01C19/5607—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using vibrating tuning forks
Abstract
A kind of quartz digital tuning fork gyroscope drives loop control circuit, relates to micro electronmechanical field.It comprises FPGA module, D/A chip, low-pass filter, the driving of quartz tuning-fork gyro tuning fork, amplifilter, A/D chip, power module; FPGA module exports digital sine and controls signal to D/ bis-A chip, low-pass filter, makes quartz tuning-fork gyro drive tuning fork vibration; After quartz tuning-fork gyro drives tuning fork to vibrate amplification filtering, be converted to digital feedback signal by A/D chip and be sent to FPGA module, FPGA module carries out Frequency And Amplitude Modulation to digital feedback signal, realizes controlling the loop of quartz tuning-fork gyro.The present invention drives that the frequency control precision of loop is higher, amplitude control accuracy is good, improves gyro performance.
Description
Technical field
The present invention relates to the quartz tuning-fork gyro in micro electronmechanical field, particularly quartz tuning-fork gyro drives loop control circuit.
Background technology
Quartz tuning-fork gyro belongs to the one of micromechanical gyro, has the advantages such as volume is little, low in energy consumption, cost is low, applicable batch production, is widely used in the fields such as spacecraft, platform stance control, guided missile.The signal processing circuit of quartz tuning-fork gyro has mimic channel and digital circuit two kinds, and relative to mimic channel, digital circuit has signal transacting flexible, the advantages such as noise is little, is not affected by the external environment, reproducible.
Existing quartz tuning-fork gyro digitizer, on hardware, which employs the bi-processor architecture of DSP+CPLD, DSP completes digital signal processing algorithm, and CPLD realizes digital to analog converter, the control of analog to digital converter and communication interface.On algorithm, its digital signal processing algorithm is the order execution algorithm based on C language, the mode of 4 frequency multiplication sparse samplings is adopted to carry out collection computing to drive singal, for the drive singal of 10KHz, require that the algorithm performance period is 25us, add in algorithm and relate to a large amount of trigonometric function operations, so it has very high requirement to the calculated performance of dsp processor.Improve the sampling number that sampling rate increases each sinusoidal cycles, can arithmetic accuracy be improved, thus improve gyro performance, but this just requires select more high performance dsp processor or improve dsp operation dominant frequency, thus add system cost and power consumption.So prior art is limited by the computing power of processor, the algorithm performance period can not be very fast, affects the precision of algorithm and the performance of gyro.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provides a kind of quartz digital tuning fork gyroscope and drives loop control circuit, and the frequency control precision of driving loop is higher, amplitude control accuracy is good, improves gyro performance.
Technical solution of the present invention is: a kind of quartz digital tuning fork gyroscope drives loop control circuit, comprises FPGA module, D/A chip, low-pass filter, the driving of quartz tuning-fork gyro tuning fork, amplifilter, A/D chip, power module; Described FPGA module exports digital sine and controls signal to D/A chip, digital sine control signal is converted to analog control signal and is sent to low-pass filter by described D/A chip, high-frequency signal in described low-pass filter elimination analog control signal is also sent to quartz tuning-fork gyro driving tuning fork, makes quartz tuning-fork gyro drive tuning fork vibration; After quartz tuning-fork gyro drives tuning fork that vibration passing to amplifilter is carried out amplification filtering, obtain analog feedback signal and be sent to A/D chip, analog feedback signal is converted to digital feedback signal and is sent to FPGA module by A/D chip, FPGA module carries out Frequency And Amplitude Modulation to digital feedback signal, and send new digital sine and control signal to D/A chip, after low-pass filter, be sent to quartz tuning-fork gyro again drive tuning fork, realize controlling the loop of quartz tuning-fork gyro; Described power module is used for powering to loop control circuit.
Described FPGA module comprises instruction module, frequency controller, sinusoidal signal generator, amplitude controller, multiplier, totalizer; Instruction module sends given frequency values to frequency controller, sends to tentering value to amplitude controller simultaneously; Described frequency control module receives given frequency values and after carrying out frequency modulation, is sent to sinusoidal signal generator, and it is the sine wave of 1 that forcing function generator produces amplitude unit; Amplitude controller receives given amplitude and exports target amplitude after carrying out amplitude modulation; Described unit be 1 sine wave after multiplier is multiplied, be sent to totalizer with described target amplitude, totalizer produce biased after obtain digital sine control signal, be sent to D/A chip; Instruction module receives digital feedback signal, and given frequency values, given amplitude and digital feedback signal are sent to totalizer, and the practical frequency in digital feedback signal and given frequency are subtracted each other by totalizer by totalizer, obtain frequency modulation input value e
1k () is also sent to frequency controller and carries out frequency modulation; The frequency modulation result of sinusoidal signal generator receive frequency controller also produces the sine wave that new unit is 1; Actual measurement amplitude in digital feedback signal and given amplitude are subtracted each other by totalizer by totalizer, obtain phase modulation input amplitude e
2k () is also sent to amplitude controller and carries out phase modulation, obtain new target amplitude; New unit be 1 sine wave after multiplier is multiplied, be sent to totalizer with new target amplitude, totalizer produce biased after obtain new digital sine control signal and send, be sent to D/A chip.
Described FPGA module is communicated by RS422 interface with host computer, and described FPGA module is also connected with EPCS chip, for storing data.The present invention compared with prior art beneficial effect is:
(1) the present invention is based on FPGA technology, drive loop to carry out Design of digital to quartz tuning-fork gyro, breach speed restriction during traditional C language design, improve the quality of gyro drive singal and drive frequency and the amplitude control accuracy of loop.
(2) the present invention is based on FPGA technology, adopt hardware description language to realize the control of A/D, D/A, the generation, frequency control algorithm, amplitude control algolithm etc. of sinusoidal signal, convenient and easy, simple and reliable.Relative to the quartz digital tuning fork gyroscope system of traditional DSP+CPLD dual processor, invention can reduce system bulk, reduces system power dissipation.
Accompanying drawing explanation
Fig. 1 circuit diagram of the present invention;
The algorithm principle figure of FPGA module in Fig. 2 the present invention;
Sinusoidal signal generator theory diagram in Fig. 3 the present invention;
In Fig. 4 the present invention, during open loop resonant condition, quartz tuning-fork gyro drives the input and output signal schematic diagram of tuning fork;
The full temperature control curve of Fig. 5 frequency loop of the present invention.
Embodiment
As shown in Figure 1, the present invention includes FPGA module, D/A chip, low-pass filter, the driving of quartz tuning-fork gyro tuning fork, amplifilter, A/D chip, power module, described FPGA module exports digital sine and controls signal to D/A chip, digital sine control signal is converted to analog control signal and is sent to low-pass filter by described D/A chip, high-frequency signal in described low-pass filter elimination analog control signal is also sent to quartz tuning-fork gyro driving tuning fork, makes quartz tuning-fork gyro drive tuning fork vibration, after quartz tuning-fork gyro drives tuning fork that vibration passing to amplifilter is carried out amplification filtering, obtain analog feedback signal and be sent to A/D chip, analog feedback signal is converted to digital feedback signal and is sent to FPGA module by A/D chip, FPGA module carries out Frequency And Amplitude Modulation to digital feedback signal, and send new digital sine and control signal to D/A chip, after low-pass filter, be sent to quartz tuning-fork gyro again drive tuning fork, realize controlling the loop of quartz tuning-fork gyro, ensure that the driving tuning fork of gyro does the vibration of constant amplitude all the time with series resonance frequency.
Power module is used for powering to loop control circuit.FPGA module is also communicated by RS422 interface with host computer, and FPGA module is also connected with EPCS chip, and EPCS is FPGA specialized configuration chip, for storing the routine data of FPGA module.
As shown in Figure 2, FPGA module comprises instruction module, frequency controller, sinusoidal signal generator, amplitude controller, multiplier, totalizer; Instruction module sends given frequency values to frequency controller, sends to tentering value to amplitude controller simultaneously; Described frequency control module receives given frequency values and after carrying out frequency modulation, is sent to sinusoidal signal generator, and forcing function generator produces the sinusoidal wave sinx that amplitude unit is 1; Amplitude controller receives given amplitude and exports target amplitude A after carrying out amplitude modulation; Described unit be 1 sine wave after multiplier is multiplied, obtain Asinx with described target amplitude and be sent to totalizer, totalizer produces biased b, obtain digital sine control signal Asinx+b, be sent to D/A chip, obtain analog sine control signal Asinx+b, after low-pass filtering, add the input end that quartz tuning-fork gyro drives tuning fork; Instruction module receives digital feedback signal, and given frequency values, given amplitude and digital feedback signal are sent to totalizer, and the practical frequency in digital feedback signal and given frequency are subtracted each other by totalizer by totalizer, obtain frequency modulation input value e
1k () is also sent to frequency controller and carries out frequency modulation; The frequency modulation result of sinusoidal signal generator receive frequency controller also produces the sine wave that new unit is 1; Actual measurement amplitude in digital feedback signal and given amplitude are subtracted each other by totalizer by totalizer, obtain phase modulation input amplitude e
2k () is also sent to amplitude controller and carries out phase modulation, obtain new target amplitude; New unit be 1 sine wave after multiplier is multiplied, be sent to totalizer with new target amplitude, totalizer produce biased after obtain new digital sine control signal and send, be sent to D/A chip.Wherein, FPGA module selects altera corp Cyclone III Series FPGA chip, A/D and D/A chip adopts high speed 16 A/D and D/A chips of TI company.
As shown in Figure 3, sinusoidal signal generator comprises phase accumulator and sinusoidal wave searching meter.The RAM resources making in FPGA is utilized to complete a sinusoidal signal look-up table, the output offset of sinusoidal signal look-up table of phase accumulator is adopted to carry out addressing, complete digital-to-analog conversion through D/A chip, then after carrying out low-pass filtering by low-pass filter, produce the sine wave signal of frequency-adjustable.Because the starting point in the starting point of each cycle period of phase accumulator and output sinusoidal signal each cycle is corresponding, so, accurately can catch in FPGA inside the initial time exporting sinusoidal signal each cycle.Under phase accumulator is operated in the clock of 100MHz, the acquisition accuracy of corresponding sinusoidal signal initial time is 10ns.
As shown in Figure 2, quartz tuning-fork gyro can be equivalent to a resistance when driving tuning fork to be operated in resonant condition, analog sine control signal Asinx+b can not produce phase shift through tuning fork, that is under resonant condition, quartz tuning-fork gyro drives the phase shift of tuning fork to be determined by the circuit of FPGA module inside, suppose that the circuit parameter of FPGA module inside does not change, this phase shift is exactly certain value, so frequency control just can be converted to the control of phase shift.Be 0 according to the amplitude of phase shift point, just Phaseshift controlling can be converted to Control of Voltage.Because the initial time of sinusoidal signal accurately can be caught in FPGA module inside, final based on FPGA design philosophy, convert frequency control to Control of Voltage, the amplitude of loop output signal phase shift place is driven by the collection of A/D chip, compare with 0, adopt the PI controller that increment type integration is separated, regulate the output frequency of sinusoidal signal generator, make this amplitude all-the-time stable 0, thus ensure that gyro is operated in series resonance frequency.
As shown in Figure 2, through the adjustment of frequency controller, the phase shift of loop is certain, the phase place driving loop to export sinusoidal signal crest value can accurately be measured, loop is driven to export the crest value of sinusoidal signal by the collection of A/D chip, compare with setting value, adopt increment type PI controller, control this crest value and be stabilized in setting value.
Sinusoidal signal generator, utilizes formula (1) to calculate the sine value of 16384 points in 0-2 ∏,
Use 16 DA chips that external reference voltage is 4.096V, during its output 1V, corresponding digital quantity is 16000, X (n) in (1) is multiplied by 16000, after rounding downwards, with the form writing in files of complement code, complete a sinusoidal truth table, truth table is write in the inside ROM of FPGA, corresponding ROM organizational form is 214x6=26214, i.e. 14 bit address lines, 16 position datawires.As Fig. 3, with a phase accumulator to above-mentioned ROM addressing, the input phase Φ inc of phase accumulator adopts the integer of 32bit to quantize, and input clock is FPGA work clock 14.7456MHz, and the frequency of sine wave output is:
As Φ inc=1,
The resolution of sinusoidal signal generator is 0.00343Hz, the restricted size with ROM resource in FPGA, and high 14 that export with phase accumulator are carried out addressing to ROM.So far, sinusoidal signal generator can output amplitude be the sine wave of 1V, frequency-adjustable.In addition, based on the sine wave that Fig. 3 principle produces, starting point and the starting point in output sinusoidal signal each cycle of each cycle period of phase accumulator are corresponding, therefore, can catch in FPGA module inside the initial time exporting sinusoidal signal each cycle.
As shown in Figure 4, assumed curve 1 is the input of quartz tuning-fork gyro driving tuning fork, and curve 2 is under resonant condition, and quartz tuning-fork gyro drives the output waveform of tuning fork, and two curves are with frequency not homophase.Under series resonance state, the phase differential △ Φ of curve 1 and 2 is definite values, that is, under resonant condition, during T1 moment, the amplitude of curve 2 correspondence is A1=0, from the initial time (T0) in curve 1 each cycle, time delay T1, starts A/D and gathers the output that gyro drives loop, if it is not 0, the then input of control phase totalizer, until export as A1=0.The PI controller that the process regulated adopts increment type integration to be separated, adjustment process starts, and error is larger, pure ratio is used to control, such as formula (4), when control errors is after certain limit, introduce integration control, such as formula (5), make the steady-state error of system be 0, the input that in formula, e (k) is regulator, the i.e. deviation of k moment set-point and actual value, u (k) is the output of k moment regulator, and Kp is scale-up factor, Ti is integration time constant, and T is control cycle.
u(k)-u(k-1)+K
p[e(k)-e(k)-1](1)
For a specific gyro, its quartz tuning-fork gyro drives tuning fork resonance frequency to be 9346.3Hz, the input phase Φ inc=2722307 of phase accumulator is drawn by formula (2), this value is as the input of phase accumulation device, generation frequency is the sine wave of 9346.3Hz by sinusoidal signal generator, this signal drives the input of tuning fork as quartz tuning-fork gyro, then the sample frequency arranging A/D is 460800Hz, gather input signal and output signal that quartz tuning-fork gyro drives tuning fork simultaneously, as shown in Figure 4, curve 1 is input sine wave, curve 2 is sine wave output.By matlab instrument, by function inline () and lsqcurvefit (), carrying out fitted figure 4 two sinusoidal curves is:
Curve 1:y(t)=-sin (2 π × 9346.3 × t+1.7) 10
Curve 2:y(t)=-0.37sin (2 π × 9346.3 × t+0.9)+2.5
So phase differential ΔΦ=0.8 of the two
And then
As Fig. 4, the initial time T0 of each sinusoidal cycles starts, about 200 FPGA frequency of operation cycles of time delay 13.6229us(), start the output valve A1 that AD gathers the quartz tuning-fork gyro driving tuning fork in a T1 moment, after gathering 32 times, do once average, this value is the e (k) in (4) formula, (5) formula, and the output of (4) formula, (5) formula is the input phase Φ inc of phase accumulator.Because after carrying out 32 samplings, perform once the calculating of (4) formula, (5) formula, so the performance period of frequency control algorithm is 32/9346.3x1000 ≈ 3.4ms.
Fig. 5 is full temperature lower frequency control effects figure, in experimentation, is first warming up to 60 DEG C, is then cooled to-40 DEG C, be finally warming up to 60 DEG C, forms a complete temperature cycles.As seen from the figure, gyro series resonance frequency changes along with temperature change, and the output of frequency controller can follow the series resonance frequency of gyro.
The output area of D/A chip is 0-4.096V, formula (1) is changed as shown below:
The output area of the sine wave of amplitude controller is adjusted in 0-4.096, and setting quartz tuning-fork gyro drives the target amplitude of tuning fork sine wave output to be 3.6V, as Fig. 5, namely regulates A value in above formula, makes the amplitude stability of T2 moment sine wave 2 at 3.6V.Adopt increment type integral control algorithm, such as formula (7), the input that in formula, e (k) is regulator, the i.e. deviation of k moment set-point and actual value, u (k) is the output of k moment regulator, and Ti is integration time constant, and T is control cycle.
For a specific gyro, as Fig. 4, the initial time T0 of each sinusoidal cycles starts, about 595 FPGA frequency of operation cycles of time delay 40.3715us(), start the output valve A2 that A/D gathers the gyro driving loop in a T2 moment, after gathering 64 times, do once average, this value and 3.6V poor, be input e (k) of formula (7), output u (k) of formula (7), is A value in formula (6).Because after carrying out 64 samplings, perform once the calculating of (7) formula, so the performance period of amplitude control algolithm is 64/9346.3x1000 ≈ 6.8ms.Prove through several times test, under full temperature, amplitude controller can make quartz tuning-fork gyro drive tuning fork under full temperature environment, do the vibration of constant amplitude.
The content be not described in detail in instructions of the present invention belongs to the known technology of those skilled in the art.
Claims (2)
1. quartz digital tuning fork gyroscope drives a loop control circuit, it is characterized in that: comprise FPGA module, D/A chip, low-pass filter, the driving of quartz tuning-fork gyro tuning fork, amplifilter, A/D chip, power module; Described FPGA module exports digital sine and controls signal to D/A chip, digital sine control signal is converted to analog control signal and is sent to low-pass filter by described D/A chip, high-frequency signal in described low-pass filter elimination analog control signal is also sent to quartz tuning-fork gyro driving tuning fork, makes quartz tuning-fork gyro drive tuning fork vibration; After quartz tuning-fork gyro drives tuning fork that vibration passing to amplifilter is carried out amplification filtering, obtain analog feedback signal and be sent to A/D chip, analog feedback signal is converted to digital feedback signal and is sent to FPGA module by A/D chip, FPGA module carries out Frequency And Amplitude Modulation to digital feedback signal, and send new digital sine and control signal to D/A chip, after low-pass filter, be sent to quartz tuning-fork gyro again drive tuning fork, realize controlling the loop of quartz tuning-fork gyro; Described power module is used for powering to loop control circuit; Described FPGA module comprises instruction module, frequency controller, sinusoidal signal generator, amplitude controller, multiplier, totalizer; Instruction module sends given frequency values to frequency controller, sends to tentering value to amplitude controller simultaneously; Described frequency control module receives given frequency values and after carrying out frequency modulation, is sent to sinusoidal signal generator, and it is the sine wave of 1 that forcing function generator produces amplitude unit; Amplitude controller receives given amplitude and exports target amplitude after carrying out amplitude modulation; Described unit be 1 sine wave after multiplier is multiplied, be sent to totalizer with described target amplitude, totalizer produce biased after obtain digital sine control signal, be sent to D/A chip; Instruction module receives digital feedback signal, and given frequency values, given amplitude and digital feedback signal are sent to totalizer, and the practical frequency in digital feedback signal and given frequency are subtracted each other by totalizer by totalizer, obtain frequency modulation input value e
1k () is also sent to frequency controller and carries out frequency modulation; The frequency modulation result of sinusoidal signal generator receive frequency controller also produces the sine wave that new unit is 1; Actual measurement amplitude in digital feedback signal and given amplitude are subtracted each other by totalizer by totalizer, obtain phase modulation input amplitude e
2k () is also sent to amplitude controller and carries out phase modulation, obtain new target amplitude; New unit be 1 sine wave after multiplier is multiplied, be sent to totalizer with new target amplitude, totalizer produce biased after obtain new digital sine control signal and send, be sent to D/A chip.
2. a kind of quartz digital tuning fork gyroscope according to claim 1 drives loop control circuit, and it is characterized in that: described FPGA module is communicated by RS422 interface with host computer, described FPGA module is also connected with EPCS chip, for storing data.
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| CN111964655B (en) * | 2020-07-15 | 2022-07-15 | 北京自动化控制设备研究所 | Digital driving circuit of quartz tuning fork gyroscope |
| CN114593723B (en) * | 2020-12-04 | 2023-07-18 | 北京晨晶电子有限公司 | Quartz tuning fork gyroscope circuit and gyroscope |
| CN115127534B (en) * | 2022-09-01 | 2022-11-18 | 中国船舶重工集团公司第七0七研究所 | Quartz gyro sine wave phase detection compensation method based on carrier modulation |
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