CN103686186A - Data transmission platform - Google Patents
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- CN103686186A CN103686186A CN201310750022.5A CN201310750022A CN103686186A CN 103686186 A CN103686186 A CN 103686186A CN 201310750022 A CN201310750022 A CN 201310750022A CN 103686186 A CN103686186 A CN 103686186A
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Abstract
The invention provides a data transmission platform which comprises an audio/video decoding chip, a Field Programmable Gate Array (FPGA) chip and a high-speed interface chip. The FPGA chip communicates with the audio/video decoding chip and the high-speed interface chip respectively. The audio/video decoding chip is used for receiving audio/video data sources, making the audio/video data sources to be converted from analog signals to digital signals and outputting the converted digital signals in a preset protocol specification mode. The FPGA chip is used for collecting and processing the digital signals transmitted by the audio/video decoding chip. The high-speed interface chip is used for receiving the signals transmitted by the FPGA chip and converting the received signals to those capable of being recognized by a display terminal. The chips arranged on the data transmission platform ensure integrity of high-speed signals in the transmission process and accuracy of collected signals, and ensures accurate transmission of the high-speed signals.
Description
Technical field
The present invention relates to technical field of data transmission, particularly a kind of data transfer platform.
Background technology
In technical field of data transmission, in order to transmit exactly data, in prior art, there is several data transmission platform.These data transfer platforms can meet the transfer of data that video format is low form.
Due to high speed signal rate block; easily there is the displacement of signal data and signal clock; and in the structural design of data transfer platform of the prior art, do not consider the factors such as the crosstalking of signal, reflection; when in adopting prior art, general data transfer platform comes transmission of video form to be the data source of high form; in high-speed interface image data process; often can when receiving front-end data, there is error code or before receiving clock signal just very poor; thereby the signal error rate that causes interface to gather is high, further causes data transmission fails.
Summary of the invention
In view of this, in order to solve data source high problem of the signals collecting error rate in data transmission procedure that video format is high form, the invention provides a kind of data transfer platform, to guarantee the stable correctly transmission of the data of high form.
In order to solve the problems of the technologies described above, the present invention has adopted following technical scheme:
A data transfer platform, comprises audio/video decoding chip, fpga chip and high-speed interface chip, described fpga chip respectively with described audio/video decoding chip and described high-speed interface chip communication;
Wherein, described audio/video decoding chip, for receiving audio, video data source, and converts described audio, video data source to digital signal by analog signal, also for the formatted output with predetermined protocol standard by the digital signal converting to;
Described fpga chip, for gathering and process the digital signal by described audio/video decoding chip transmission;
Described high-speed interface chip, for receiving the signal being transferred to by described fpga chip, and converts the signal receiving to the signal that can be shown terminal recognition.
Preferably, by audio/video decoding chip to the mode of fpga chip transmission of data signals for parallel.
Preferably, on described audio/video decoding chip, be provided with output interface, described output interface level adopts Transistor-Transistor Logic level standard.
Preferably, on described fpga chip, be provided with input interface, the voltage standard that the input interface configuration on described fpga chip is identical with the output interface on described audio/video decoding chip.
Preferably, be provided with the input interface being connected with described audio/video decoding chip on described fpga chip, the source clock cabling of being drawn by audio/video decoding chip and data cabling equate to the distance of the input interface on described fpga chip.
Preferably, on described audio/video decoding chip, be provided with output interface, on described fpga chip, be provided with the input interface being connected with described audio/video decoding chip, on the output interface on described audio/video decoding chip and the connection line of the input interface on described fpga chip, be provided with resistance.
Preferably, the distance of the input interface of described resistance on described fpga chip is less than described resistance at a distance of the distance of the output interface of described audio/video decoding chip.
Preferably, on described fpga chip, be provided with the input interface being connected with described audio/video decoding chip, described audio/video decoding chip is connected by default draw-in groove with the input interface on described fpga chip, one of described default draw-in groove is provided with public mouthful, other one is provided with female hole, via hole on described public mouthful of pcb board with described audio/video decoding chip is connected, and described female eyelet welding dish clamps on the input interface of described fpga chip.
Preferably, on described fpga chip, be provided with a plurality ofly for receiving the input interface by audio/video decoding chip output data, between adjacent described input interface, by a pair of ground connection, separate.
Preferably, described digital signal comprises at least one in clock signal, rgb signal, HS signal, VS signal and DE signal.
Preferably, described fpga chip inside is provided with high-speed interface LVDS, and the Interface Matching of described high-speed interface LVDS and described high-speed interface chip is used.
Preferably, the form in described audio, video data source is a kind of in VGA, CVBS, HDMI, YPbPr, S-video.
Preferably, described high-speed interface chip is for the signal output of MHL-TX.
Preferably, also comprise, display terminal, for showing the data-signal being transmitted by described high-speed interface chip.
The data transfer platform that the embodiment of the present invention provides, audio/video decoding chip on this data transfer platform can receive the data source of high form, and convert this data source to digital signal, the digital signal of also conversion being come is to meet the audio frequency and video formatted output of predetermined protocol standard, then, the audio frequency and video formatted data that fpga chip meets predetermined protocol standard to this is carried out acquisition and processing, then by high-speed interface chip, received, finally by high-speed interface chip, signal is converted to the signal that can be shown terminal recognition.By this series of transmission path, high form audio, video data source can and finally show by correctly transmission, thereby complete the transmission in high form audio, video data source on display terminal.Each chip on the data transfer platform providing by the embodiment of the present invention has guaranteed the integrality of the signal of high speed signal in transmitting procedure and the accuracy of collection signal, has guaranteed the correct transmission of high speed signal.
Accompanying drawing explanation
In order to be expressly understood the embodiment described in the embodiment of the present invention, the accompanying drawing of using when describing embodiment below carries out brief description.Apparently, the accompanying drawing the following describes is only some embodiments of the present invention, for those of ordinary skills, is not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the data transfer platform topological diagram that the embodiment of the present invention provides;
Fig. 2 is a kind of topological diagram of the FPGA system of the embodiment of the present invention;
Fig. 3 is another topological diagram of the FGPA system of the embodiment of the present invention.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is carried out to clear, complete description, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Just as described in the background section, existing data transfer platform cannot meet for example transmission of the audio, video data of high form of high speed signal.Correct transmission in order to ensure high speed signal, the invention provides a kind of data transfer platform.
The data transfer platform embodiment of the present invention being provided in conjunction with Fig. 1 is elaborated.As shown in Figure 1, the data transfer platform that the embodiment of the present invention provides comprises, audio/video decoding chip 100, fpga chip 200 and high-speed interface chip 300, and wherein, fpga chip 200 communicates with audio/video decoding chip 100 and high-speed interface chip 300 respectively.In order to realize transfer of data, on the audio/video decoding chip 100 on this data transfer platform, fpga chip 200 and high-speed interface chip 300, be provided with input/output interface.This input/output interface can be same interface, also can be respectively independently two interfaces.Wherein, the output interface on upstream chip is connected with the input interface of downstream chip, thereby realizes the transmission of data.
In this data transfer platform, audio/video decoding chip 100 is positioned at the upstream of fpga chip 200, by the input interface on this audio/video decoding chip 100, receive audio, video data source, and because audio, video data source is generally analog signal, so in order to make data source be gathered by fpga chip, audio/video decoding chip 100 is also for converting the audio, video data source receiving to digital signal, and this audio/video decoding chip 100 is also for changing next digital signal to meet the audio frequency and video formatted output of predetermined protocol standard.Described digital signal comprises at least one in clock signal, rgb signal, HS signal, VS signal and DE signal.
In embodiments of the present invention, the video format that audio/video decoding chip 100 is supported comprises that some low speed such as PAL, NTSC, 480P, 720P, 1080i, 1080p, 3D720P, 3D1080P, 4K*2K are to video format at a high speed.Audio/video decoding chip 100 in the embodiment of the present invention can be the audio/video decoding chip of the data source of VGA, CVBS, HDMI, YPbPr, S-video for receiving data source form.The form of being changed the digital signal of output by this audio/video decoding chip 100 can be RGB, HS, VS, DE, and the data compression format that this audio/video decoding chip 100 converts to can be RGB444, YCbCr444, YCbCr422, bt656, bt601 etc.Audio digital signals by these audio/video decoding chip 100 outputs can be IIS or SPDIF.The video format of the digital signal of output can be RGB44430bit, RGB44424bit, YCbCr444 24bit, and YcbCr422 16bit, YcbCr422 8bit, the audio frequency of output can be supported L-PCM, DOLBY, DTS audio format.
In embodiments of the present invention, fpga chip 200 is for gathering and process the digital signal being sent by audio/video decoding chip 100.It should be noted that, in the inside of fpga chip, be provided with high-speed interface LVDS, in order to transmit better data, the high-speed interface LVDS of these fpga chip 200 inside and the Interface Matching of high-speed interface chip are used.
While reaching the input interface of fpga chip by the data (data-signal is digital signal) of audio/video decoding chip 100 transmission, data-signal starts collected and is input to fpga chip pin.The process of the collected processing of data-signal is to complete in the inside of fpga chip 100.The time delay of data-signal from input interface to target devices is identical, and the input of external source clock is dispensed on the global clock pin of fpga chip as far as possible, can guarantee that like this signal is in the sequential accuracy of FPGA inside.
High-speed interface chip 300 is positioned at the downstream of fpga chip 200, for receiving the signal being transmitted by fpga chip 200, and the signal receiving is converted to the data-signal that can be shown terminal recognition.
The data transfer platform providing for the embodiment of the present invention above, this data transfer platform receives data source (data source form can be high form) by audio/video decoding chip 100, and convert this data source to digital signal, the digital signal of also conversion being come is to meet the audio frequency and video formatted output of predetermined protocol standard, then, the audio frequency and video formatted data that fpga chip meets predetermined protocol standard to this is carried out acquisition and processing, then by high-speed interface chip, received, finally by high-speed interface chip, signal is converted to the signal that can be shown terminal recognition.By this series of transmission path, audio, video data source can and finally show by correctly transmission, realize the transmission that audio, video data source comprises high form audio, video data source on display terminal.
Each chip on the data transfer platform that the embodiment of the present invention provides has guaranteed the integrality of the signal of high speed signal in transmitting procedure and the accuracy of collection signal, has guaranteed the correct transmission of high speed signal.
The data transfer platform providing due to above-described embodiment can be guaranteed the correct transmission of high speed signal, therefore this data transfer platform can be for chip functions test and the checking before the clear video chip flow of absolute altitude, this data transfer platform can complete chip functions test in real time, guarantees that the function that chip has realizes.
Further, as another embodiment of the present invention, data transfer platform described above, can also comprise display terminal 400, and this display terminal 400 is for showing audio, video data source signal, with the correctness of real-time verification signal transmission.
On this data transfer platform, for fear of in parallel interface due to electromagnetic compatibility, reflection, ring, bullet, crosstalk and data that via hole parasitic parameter causes and clock between partially mutually and asymmetric, the embodiment of the present invention is also to processing between each chip interface on this data transfer platform.Specifically referring to description.
It should be noted that, the mode that adopts parallel transmission in the embodiment of the present invention by audio/video decoding chip 100 to fpga chip 200 transmission of data signals, i.e. corresponding one group of 30bit data of clock cycle and HS, VS, DE, IIS, SPDIF.
For fear of in parallel interface due to electromagnetic compatibility, reflection, ring, bullet, crosstalk and data and the inclined to one side phase between clock and asymmetric that via hole parasitic parameter causes, output interface level on audio/video decoding chip 100 adopts TTL(transistor-transistor-logic, transistor-transistor-logic voltage) level standard.Further, the voltage standard that the level of the input interface on fpga chip configuration is identical with output interface level on audio/video decoding chip 100, i.e. Transistor-Transistor Logic level standard.
In order to make the synchronous of data-signal and clock signal, the delay that signal transmission is occurred is roughly the same, ensure the correct transmission of data, the source clock cabling of being drawn by the output interface of audio/video decoding chip 100 in the embodiment of the present invention and data cabling equate to the distance of the input interface of fpga chip 200.In addition, in data transmission procedure, conventionally can transmit several data signal simultaneously, receive the synchronism of signal in order to ensure fpga chip 200, the length of the data circuit of these transmission variety classes data-signals also equates.
Further, in order to reduce signal transmission in the reflection of the interface of different chips, the embodiment of the present invention preferably arranges resistance on the connection line of the input interface on the output interface on audio/video decoding chip 100 and described fpga chip 200.And further, the resistance of this setting is less than the distance of the output interface of this resistance on audio/video decoding chip 100 at a distance of the distance of the input interface of fpga chip 200.Further, the resistance of this setting is positioned near the input interface place on fpga chip 200.
In addition, in Design of Digital System, along with improving constantly of wiring density and clock frequency, the problem such as signal integrity and electromagnetic compatibility is further outstanding, this provides higher requirement to hardware designs, in multi-layer PCB board, often adopts via hole to realize the electrical connection between different layers.And in high-frequency circuit, the diameter of via hole can affect the integrality of high speed signal.For fear of via hole, the integrality of the high speed signal of transmission is impacted, under the design of reasonable via diameter, between the audio/video decoding chip 100 of the embodiment of the present invention and the input interface on fpga chip 200, by default draw-in groove, realize and connecting.One of this default draw-in groove is provided with public mouthful, and other one is provided with female hole, and the public mouth of this default draw-in groove welds with the via hole on the pcb board of audio/video decoding chip 100, and female eyelet welding dish pincers of this default draw-in groove are on the input interface of fpga chip 200.By default draw-in groove, connect, can reduce when transmitting high speed video formatted data, due to gap clock signal, the risk that data and clock generation phase deviation meeting cause data can not correctly be gathered at fpga chip interface.It should be noted that, the reasonable via diameter described in the embodiment of the present invention is the via diameter that meets predetermined parasitic parameter.In high-frequency circuit, via hole can produce parasitic series inductance, and via hole stray inductance size is approximately:
In formula, L is via hole inductance, nH;
H is via length, in;
D is via diameter, in.
From formula (1), via length and diameter are very large on the impact of parasitic parameter, even play conclusive effect.Under identical material, via length is longer, and diameter is less, and parasitic parameter is larger, larger on the impact of high-frequency signal transmission.Because stray inductance can weaken the contribution of shunt capacitance, weaken the filter action of whole power-supply system, the high impedance of generation can not be ignored high-frequency signal.Under this prerequisite, need parasitic parameter according to actual needs to select rational via diameter.
Further, based on above-mentioned same reason, the connected mode of the high-speed interface chip in fpga chip and downstream preferably adopts the mode of default draw-in groove to realize connection.Female mouthful of this default draw-in groove joins with the I/O mouth of fpga chip, and the public eyelet welding dish pincers of this default draw-in groove are on the interface of high-speed interface chip 300.
In the design process of the data transfer platform providing in the embodiment of the present invention, in order to ensure the data-signal of being exported by audio/video decoding chip, by fpga chip, correctly gathered, the embodiment of the present invention has been done careful analysis on chip selection, in addition, in the selection of the high speed output interface of fpga chip, also done comparatively careful analysis, based on above-mentioned analysis, the embodiment of the present invention has proposed a kind of preferred implementation.Concrete topological structure shown in Figure 2.
Specific implementation mode is as follows:
As a preferred embodiment of the present invention, it is the chip of ADV7441A or ADV7169 that the audio/video decoding chip in the data transfer platform that the embodiment of the present invention provides can adopt chip model.Wherein, model is that the chip of ADV7441A can be that the video data source of VGA, CVBS, HDMI, PbPr, S-video converts digital signal to by signal format, and the video data source that the chip that model is ADV7169 can be HDMI by form converts digital signal to.
Further, the fpga chip described in the embodiment of the present invention 200 can be Altera Str4FPGA chip.And in order to guarantee that data-signal is correctly gathered in fpga chip inside, thus the sequential correctness of assurance FPGA inside, and the LVDS TX interface on Altera Str4FPGA chip can coordinate the high-speed interface of the high-speed interface chip 300 in downstream to use.
Further, the high-speed interface chip described in the embodiment of the present invention can be LT8818.The effect of chip LT8818 has been that form is the output of the signal source of MHL-TX, and the data-signal of transmission is through high-speed chip interface LT8818, through outputing to display terminal to MHL-RX.It should be noted that, the present embodiment utilizes television set as display terminal.Adopt chip LT8818, can realize transmission rate up to 3Gbps, thereby make this data transfer platform support MHL2.0 standard.
In order to improve the stability of data in interface gatherer process, the embodiment of the present invention can also further be done a little improvement to high-speed interface chip LT8818, for example, on the simulation layer of LT8818, added the adjustment of dynamic clock phase place.
The display terminal that the embodiment of the present invention adopts can be projecting apparatus or television set, sound equipment (being mainly used to detect sound).When transmission of audio data, the selection of television set will be considered the configuration of N and CTS parameter in voice data.
The transmission that it is MHL-TX that data transfer platform described above can complete signal format.On adopting Altera Str4FPGA chip LVDS pin output high-speed data time, then in conjunction with LT8818, can realize the transfer of data of MHL signal, thereby make this data transfer platform support the standard of MHL2.0.
It should be noted that, the data transfer platform that the embodiment of the present invention provides can also be for the transmission of HDMI-TX signal, and when transmission HDMI-TX signal, chip LT8818 as shown in Figure 2 changes chip LT8611 into.The topological diagram of this FPGA system as shown in Figure 3, when transmission HDMI signal, does not just need MHL-RX in FPGA system yet.。
The above is only the preferred embodiment of the present invention; it should be pointed out that for the person of ordinary skill of the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (14)
1. a data transfer platform, is characterized in that, comprises audio/video decoding chip, fpga chip and high-speed interface chip, described fpga chip respectively with described audio/video decoding chip and described high-speed interface chip communication;
Wherein, described audio/video decoding chip, for receiving audio, video data source, and converts described audio, video data source to digital signal by analog signal, also for the formatted output with predetermined protocol standard by the digital signal converting to;
Described fpga chip, for gathering and process the digital signal by described audio/video decoding chip transmission;
Described high-speed interface chip, for receiving the signal being transferred to by described fpga chip, and converts the signal receiving to the signal that can be shown terminal recognition.
2. data transfer platform according to claim 1, is characterized in that, by audio/video decoding chip to the mode of fpga chip transmission of data signals for parallel.
3. data transfer platform according to claim 1, is characterized in that, on described audio/video decoding chip, is provided with output interface, and described output interface level adopts Transistor-Transistor Logic level standard.
4. data transfer platform according to claim 3, is characterized in that, on described fpga chip, is provided with input interface, the voltage standard that the input interface configuration on described fpga chip is identical with the output interface on described audio/video decoding chip.
5. data transfer platform according to claim 1, it is characterized in that, on described fpga chip, be provided with the input interface being connected with described audio/video decoding chip, the source clock cabling of being drawn by audio/video decoding chip and data cabling equate to the distance of the input interface on described fpga chip.
6. data transfer platform according to claim 1, it is characterized in that, on described audio/video decoding chip, be provided with output interface, on described fpga chip, be provided with the input interface being connected with described audio/video decoding chip, on the output interface on described audio/video decoding chip and the connection line of the input interface on described fpga chip, be provided with resistance.
7. data transfer platform according to claim 6, is characterized in that, the distance of the input interface of described resistance on described fpga chip is less than described resistance at a distance of the distance of the output interface of described audio/video decoding chip.
8. data transfer platform according to claim 1, it is characterized in that, on described fpga chip, be provided with the input interface being connected with described audio/video decoding chip, described audio/video decoding chip is connected by default draw-in groove with the input interface on described fpga chip, one of described default draw-in groove is provided with public mouthful, other one is provided with female hole, and the via hole on described public mouthful of pcb board with described audio/video decoding chip is connected, and described female eyelet welding dish clamps on the input interface of described fpga chip.
9. data transfer platform according to claim 1, is characterized in that, is provided with a plurality ofly for receiving the input interface by audio/video decoding chip output data on described fpga chip, between adjacent described input interface, by a pair of ground connection, separates.
10. data transfer platform according to claim 1, is characterized in that, described digital signal comprises at least one in clock signal, rgb signal, HS signal, VS signal and DE signal.
11. data transfer platforms according to claim 1, is characterized in that, described fpga chip inside is provided with high-speed interface LVDS, and the Interface Matching of described high-speed interface LVDS and described high-speed interface chip is used.
12. data transfer platforms according to claim 1, is characterized in that, the form in described audio, video data source is a kind of in VGA, CVBS, HDMI, YPbPr, S-video.
13. data transfer platforms according to claim 1, is characterized in that, described high-speed interface chip is for the signal output of MHL-TX.
14. according to the data transfer platform described in claim 1-13, it is characterized in that, also comprises, display terminal, for showing the data-signal being transmitted by described high-speed interface chip.
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| CN103957381A (en) * | 2014-04-17 | 2014-07-30 | 华为技术有限公司 | Data transmission device, method and system |
| CN105898176A (en) * | 2015-12-03 | 2016-08-24 | 乐视致新电子科技（天津）有限公司 | Signal processing method and signal processor |
| CN106059605A (en) * | 2016-07-27 | 2016-10-26 | 龙迅半导体（合肥）股份有限公司 | Multiplexing receiver of HDMI and MHL |
| CN106126186A (en) * | 2016-08-29 | 2016-11-16 | 北京声智科技有限公司 | A kind of multi-channel audio signal parallel acquisition device |
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| TW395137B (en) * | 1997-06-06 | 2000-06-21 | Matsushita Electric Ind Co Ltd | Image processing device |
| CN201001169Y (en) * | 2007-01-26 | 2008-01-02 | 东南大学 | Video collecting device for vehicle-mounted surrounding |
| CN102186073B (en) * | 2011-04-27 | 2015-07-29 | 浙江大华技术股份有限公司 | HD-SDI video signal transmission system in high speed ball-type camera and method |
| CN203193684U (en) * | 2012-09-29 | 2013-09-11 | 深圳天珑无线科技有限公司 | LVDS circuit and PCB used for mobile terminal |
| CN203192366U (en) * | 2013-01-17 | 2013-09-11 | 西安奇维科技股份有限公司 | SDVO and VGA conversion device based on FPGA |
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| CN103957381A (en) * | 2014-04-17 | 2014-07-30 | 华为技术有限公司 | Data transmission device, method and system |
| CN105898176A (en) * | 2015-12-03 | 2016-08-24 | 乐视致新电子科技（天津）有限公司 | Signal processing method and signal processor |
| CN106059605A (en) * | 2016-07-27 | 2016-10-26 | 龙迅半导体（合肥）股份有限公司 | Multiplexing receiver of HDMI and MHL |
| CN106059605B (en) * | 2016-07-27 | 2018-10-16 | 龙迅半导体（合肥）股份有限公司 | A kind of multiplexing receiver of HDMI and MHL |
| CN106126186A (en) * | 2016-08-29 | 2016-11-16 | 北京声智科技有限公司 | A kind of multi-channel audio signal parallel acquisition device |
| CN110312158A (en) * | 2018-03-27 | 2019-10-08 | 北京市博汇科技股份有限公司 | A kind of monitoring method and device of embedded more pictures |
| CN109548236A (en) * | 2018-12-05 | 2019-03-29 | 大峡谷照明系统（苏州）股份有限公司 | A kind of master controller of LED illumination System and its layout designs on PCB |
| WO2020114206A1 (en) * | 2018-12-05 | 2020-06-11 | 大峡谷照明系统（苏州）股份有限公司 | Master controller for led lighting system, and design for layout of same on pcb |
| WO2021121432A1 (en) * | 2019-12-20 | 2021-06-24 | 威创集团股份有限公司 | Digital audio and video connector and interface thereof |
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