CN103685990A - Linear array CCD real-time detection data USB synchronous transmission circuit - Google Patents
Linear array CCD real-time detection data USB synchronous transmission circuit Download PDFInfo
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- CN103685990A CN103685990A CN201310515614.9A CN201310515614A CN103685990A CN 103685990 A CN103685990 A CN 103685990A CN 201310515614 A CN201310515614 A CN 201310515614A CN 103685990 A CN103685990 A CN 103685990A
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Abstract
Provided is a linear array CCD real-time detection data USB synchronous transmission circuit. The circuit comprises a main chip PIC18F4550. The main chip PIC18F4550 is provided with a clock by a 20 MHz external passive crystal oscillator, the clock is connected with a thirteenth pin and a fourteenth pin, i.e., OSC1 and OSC2, clock signals, after entering the chip, through five frequency division, are inputted to a PLL (phase-locked loop) by 4 MHz, and the PLL generates a 96 MHz frequency, and through two frequency division, obtains a 48 MHz fixed frequency which is respectively used for a CPU clock and a USB2.0 full-speed communication clock. According to the invention, a PIC18F4550 type single-chip microcomputer serves as a lower computer control core of a linear array CCD real-time detection system, and by use of an integrated USB communication module, a hardware circuit and a firmware program for USB synchronous transmission are designed, so that real-time transmission of frame pixel data to a host computer during linear array CCD real-time detection is realized.
Description
Technical field
The present invention relates to a kind of USB synchronous transmission circuit, be specifically related to a kind of line array CCD real-time detector data USB synchronous transmission circuit.
Background technology
For unit light electric device, line array CCD device has the advantages such as high-resolution, is widely used in the real-time online detection fields such as automation equipment, intelligent instrumentation and industrial production.The functions such as the A/D conversion of its driver module, pixel signal and sequencing control are realized by the slave computer being installed in industrial production line, slave computer is to take the microcontroller that single-chip microcomputer is core to build mostly, and in order to improve system accuracy of detection, host computer need have stronger computing capability, complete that pixel data gathers, analyzing and processing and judgement decision-making capability, and consider the real-time of detection, conventionally require solid imaging device to maintain high frame per second output.When CCD resolution reaches 2048 pixel, if will maintain the data collection rate of 25 frames per second and 8 basic A/D conversions, require the data/address bus transmission bandwidth of slave computer and host computer should be not less than 0.4Mb/s.Obviously, the serial communication transmission rate of common single-chip microcomputer cannot meet the requirement of real-time pixel data transmission, and USB(USB) have that transmission rate is high, favorable expandability, support hot plug and low cost and other advantages, and the single-chip microcomputer of part model has USB integration module, sequencing control and the pixel data high-speed transfer that can realize slave computer become the optimal selection addressing this problem simultaneously.
Summary of the invention
The invention provides a kind of line array CCD real-time detector data USB synchronous transmission circuit, its PIC18F4550 type single-chip microcomputer is the slave computer control core of line array CCD real-time detecting system, hardware circuit and the firmware program of USB synchronous transmission that utilized its integrated usb communication modular design, has realized during line array CCD is detected in real time frame pixel data to the real-time Transmission of host computer.
Technical solution of the present invention is:
A kind of line array CCD real-time detector data USB synchronous transmission circuit, comprise master chip PIC18F4550, its special character is: described master chip PIC18F4550 provides clock by 20MHz external passive crystal oscillator, access 13,14 pin OSC1, OSC2, clock signal enters chip internal by 5 frequency divisions, with 4MHz, is input in PLL phase-locked loop, and PLL phase-locked loop produces 96MHz frequency, after 2 frequency divisions, obtain again 48MHz fixed frequency, be respectively used to cpu clock and USB2.0 communication clock at full speed.
Above-mentioned master chip PIC18F4550 comprises master chip reset circuit, button S1, capacitor C 4 and resistance R 3, R4, consists of, and when button S1 presses, master chip detects the low level reset signal horizontal reset of going forward side by side.
The above-mentioned USB electric interfaces to host computer is provided by U2,23 and 24 pin with master chip PIC18F4550, be that usb data transmit port D-, D+ connect, owing to selecting pull-up resistor in the sheet of being controlled by configuration bit to define transmission at full speed, therefore at D+ mouth, do not use pull-up resistor.
In above-mentioned master chip PIC18F4550 port RB, RB0～RB3 mouth provides the choosing of A/D conversion chip sheet and control line in slave computer as output port, RB4-RB7 is as the output port of 4 slave computer state LED display lamps, and port RD is as the data transmission port of 8 A/D.
The invention has the advantages that: adopting PIC18F4550 type single-chip microcomputer is the slave computer control core of line array CCD real-time detecting system, hardware circuit and the firmware program of USB synchronous transmission that utilized its integrated usb communication modular design, has realized during line array CCD is detected in real time frame pixel data to the real-time Transmission of host computer.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present invention.
Embodiment
Referring to Fig. 1, a kind of line array CCD real-time detector data USB synchronous transmission circuit, comprise master chip PIC18F4550, master chip PIC18F4550 provides clock by 20MHz external passive crystal oscillator, access 13,14 pin OSC1, OSC2, and clock signal enters chip internal by 5 frequency divisions, with 4MHz, be input in PLL phase-locked loop, PLL phase-locked loop produces 96MHz frequency, then after 2 frequency divisions, obtains 48MHz fixed frequency, is respectively used to cpu clock and USB2.0 communication clock at full speed.
Master chip PIC18F4550 comprises master chip reset circuit, button S1, capacitor C 4 and resistance R 3, R4, consists of, and when button S1 presses, master chip detects the low level reset signal horizontal reset of going forward side by side.
USB electric interfaces to host computer is provided by U2,23 and 24 pin with master chip PIC18F4550, be that usb data transmit port D-, D+ connect, owing to selecting pull-up resistor in the sheet of being controlled by configuration bit to define transmission at full speed, therefore at D+ mouth, do not use pull-up resistor.
In master chip PIC18F4550 port RB, RB0～RB3 mouth provides the choosing of A/D conversion chip sheet and control line in slave computer as output port, and RB4-RB7 is as the output port of 4 slave computer state LED display lamps, and port RD is as the data transmission port of 8 A/D.
After completing circuit plate processing and fabricating, author adopts the TCD1209D molded line battle array of 2048 pixels of Toshiba as system ccd image sensor, and the AD7875 type A/D conversion chip of output signal JingAD company carries out analog-to-digital conversion, by PIC18F4550, is gathered.Wherein Linear CCD Driver and A/D sequential are produced by the MAX EPM7064 type CPLD of Altrea company.At CCD driving pulse, be 75KHz, when frame frequency is 25Hz, the PC of take has carried out experiment test to the usb communication module of line array CCD real-time detecting system as host computer, respectively at 30 seconds, 60 seconds, in the transmission time of 120 seconds and 180 seconds, the average transmission rate of synchronous transmission is basicly stable at 0.6Mbps, consider the counting error of PC host side data volume, obviously, the performance of the usb data real-time synchronization transport module of the PIC18F4550 type single-chip microcomputer design that adopts in literary composition usb communication module integrated can meet the real-time Data Transmission requirement of TCD1209D under 75KHz driving pulse.
Claims (4)
1. a line array CCD real-time detector data USB synchronous transmission circuit, comprise master chip PIC18F4550, it is characterized in that: described master chip PIC18F4550 provides clock by 20MHz external passive crystal oscillator, access 13,14 pin OSC1, OSC2, clock signal enters chip internal by 5 frequency divisions, with 4MHz, is input in PLL phase-locked loop, and PLL phase-locked loop produces 96MHz frequency, after 2 frequency divisions, obtain again 48MHz fixed frequency, be respectively used to cpu clock and USB2.0 communication clock at full speed.
2. line array CCD real-time detector data USB synchronous transmission circuit according to claim 1, it is characterized in that: described master chip PIC18F4550 comprises master chip reset circuit, by button S1, capacitor C 4 and resistance R 3, R4, formed, when button S1 presses, master chip detects the low level reset signal horizontal reset of going forward side by side.
3. according to line array CCD real-time detector data USB synchronous transmission circuit described in claim 1 or 2, it is characterized in that: the described USB electric interfaces to host computer is provided by U2,23 and 24 pin with master chip PIC18F4550, be that usb data transmit port D-, D+ connect, owing to selecting pull-up resistor in the sheet of being controlled by configuration bit to define transmission at full speed, therefore at D+ mouth, do not use pull-up resistor.
4. line array CCD real-time detector data USB synchronous transmission circuit according to claim 3, it is characterized in that: in described master chip PIC18F4550 port RB, RB0～RB3 mouth provides the choosing of A/D conversion chip sheet and control line in slave computer as output port, RB4-RB7 is as the output port of 4 slave computer state LED display lamps, and port RD is as the data transmission port of 8 A/D.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310515614.9A CN103685990A (en) | 2013-10-28 | 2013-10-28 | Linear array CCD real-time detection data USB synchronous transmission circuit |
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| CN201310515614.9A CN103685990A (en) | 2013-10-28 | 2013-10-28 | Linear array CCD real-time detection data USB synchronous transmission circuit |
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| CN103685990A true CN103685990A (en) | 2014-03-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114184936A (en) * | 2021-11-30 | 2022-03-15 | 上海儒竞智控技术有限公司 | Chip continuous welding self-detection method, system, medium and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114184936A (en) * | 2021-11-30 | 2022-03-15 | 上海儒竞智控技术有限公司 | Chip continuous welding self-detection method, system, medium and chip |
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Application publication date: 20140326 |