CN103681605A - A packaging structure of a low-k chip and a manufacturing method thereof - Google Patents
A packaging structure of a low-k chip and a manufacturing method thereof Download PDFInfo
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- CN103681605A CN103681605A CN201210362067.0A CN201210362067A CN103681605A CN 103681605 A CN103681605 A CN 103681605A CN 201210362067 A CN201210362067 A CN 201210362067A CN 103681605 A CN103681605 A CN 103681605A
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Abstract
The invention discloses a packaging structure of a low-k chip. The packaging structure comprises a substrate, a metallic layer, a TSV, and a bonding pad. A chip is formed on the substrate. The metallic layer is formed on the chip and comprises multiple vias and multiple connecting lines which are mutually and electrically connected, and dielectric layers produced by material with an ultra low-k and filled around the vias and the connecting lines. A dielectric layer at the top covers a connecting line at the top in the metallic layer. The TSV is arranged from the connecting line at the top in the metallic layer to the bottom of the substrate and passes through the substrate. The bonding pad is disposed on the dielectric layer at the top of the metallic layer and is electrically connected with the one end of the TSV on the bottom of the substrate through a metallic line. In the packaging structure, the connecting line at the top is directly guided to the bottom of the substrate via the TSV and then is connected with a bonding gasket through one end of the TSV on the bottom of the substrate without material with an ultra low-k. As a result, the crack of the dielectric layer with an ultralow dielectric constant can be prevented and a CPI problem in the prior art is further improved.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly the manufacture method of a kind of encapsulating structure of low-k chip and this low-k chip-packaging structure.
Background technology
Along with semiconductor critical size (CD, constantly reducing Critical Dimension), IC(Integrated Circuit, integrated circuit) RC producing between the intraconnections (interconnection) in has postponed to have replaced gradually the principal element that transistor self postpones and become the restriction IC speed of service.The speed that in circuit, signal transmits, is the product institute left and right that is subject to resistance R and capacitor C, and RC product is larger, and speed is just slower, and delay is just higher, otherwise RC product is less, and signaling rate just can be faster, postpones just lower.
For intraconnections (as copper interconnects), its resistance R is decided by himself material character, and IC internal structure is very little on the impact of its resistance R; And the capacitor C of intraconnections is mainly subject to the spacing distance between intraconnections, the impact of interval insulant.Therefore, can by modes such as the spacing distance between change intraconnections, interval insulants, reduce the capacitor C of intraconnections, to reduce the RC of intraconnections, postpone, improve the speed of service of IC.The impact postponing for reducing RC, current, adopt ultralow dielectric (ultra low-k) material as the dielectric layer material between intraconnections (being the interval insulant between intraconnections), to reduce the capacitor C of intraconnections, be widely used in the manufacture of IC.
Interval insulant between intraconnections, as interlayer dielectric layer (ILD, Inter Layer Dielectric), in general all there is low-k (low-k), in order to reach the effect of better its dielectric constant of reduction, and then the electric capacity of intraconnections is further reduced, at BEOL(back end ofline, last part technology, finger contacts at contact() involved manufacture of semiconductor technique afterwards) operation stage, current adopted interlayer dielectric layer adopts the ultra-low dielectric constant material of porous (porous) mostly.Because these reasons, the mechanical performance of the dielectric layer of the ultra-low dielectric constant material using is at present poor, again in the further course of processing, as being easy to cracked (crack) in chip package process and then causing the inefficacy of integrated circuit, produce CPI(Chip Package Interaction, chip package interacts) problem, the reliability while causing encapsulating significantly declines.
In existing a kind of chip-packaging structure as shown in Figure 1: there is the line through FEOL(front end of on substrate 1, FEOL) chip 2 being formed by various semiconductor device (comprising active device and passive device) that forms of stage; On described chip 2, there is the metal level forming through the BEOL stage, comprising through hole (via) 4 and connecting line 5, be arranged in the residing same layer of through hole 4 and be arranged in the dielectric layer 6 that the residing same layer of connecting line 5 is formed with the ultralow dielectric that surrounds described through hole 4 and connecting line 5, the bottom through hole 4 in metal level is electrically connected to chip 2 by the contact hole 3 of chip 2.Metal level is connected to the pad (bonding pad) 8 that is positioned at substrate 1 lower curtate by metal wire 7, in this structure, top layer connecting line 5 is connected with metal wire 7 by soldered ball.In welding procedure (Bonding), this syndeton, can be because the reasons such as effect of stress between soldered ball and metal level very easily make the dielectric layer 6 of the ultra-low dielectric constant material in metal level chipping, and then cause the inefficacy of integrated circuit.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of encapsulating structure and this low-k chip-packaging structure of low-k chip, to avoid the inefficacy of low-k chip package.
The application's technical scheme is achieved in that
An encapsulating structure for low-k chip, comprising:
Substrate;
Process formed chip of FEOL stage on described substrate;
Process formed metal level of BEOL stage on described chip; Described metal level comprises at least 1 through hole and at least 1 connecting line of mutual electrical connection, and the dielectric layer that is filled in described through hole and connecting line ultra-low dielectric constant material around; Bottom through hole in described metal level is electrically connected to described chip by the contact hole of described chip; Top layer dielectric layer in described dielectric layer covers the top layer connecting line that is arranged in metal level;
By the top layer connecting line that is arranged in metal level to described substrate bottom, and the TSV hole of substrate described in break-through;
Be positioned at the pad on the top layer dielectric layer of described metal level, one end that described pad is positioned at described substrate bottom by metal wire and described TSV hole is electrically connected to.
Further, described chip is included in the various semiconductor device that the FEOL stage forms.
Further, the material in described TSV hole is Al, Cu, W or their alloy.
A manufacture method for low-k chip-packaging structure, comprising:
Substrate is provided and on described substrate, adopts FEOL technique to form chip;
On described chip, adopt BEOL technique to form metal level, described metal level comprises at least 1 through hole and at least 1 connecting line of mutual electrical connection, and the dielectric layer that is filled in described through hole and connecting line ultra-low dielectric constant material around, bottom through hole in described metal level is electrically connected to described chip by the contact hole of described chip, and the top layer dielectric layer in described dielectric layer covers the top layer connecting line that is arranged in metal level;
On the top layer dielectric layer of described metal level, form pad; And
Form TSV hole, described TSV hole by the top layer connecting line that is arranged in metal level to described substrate bottom substrate described in break-through also.
Further, the step in described formation TSV hole was carried out before described FEOL technical process.
Further, the step in described formation TSV hole is carried out in described FEOL technical process.
Further, the step in described formation TSV hole is carried out after described FEOL technical process, before described BEOL technical process.
Further, the step in described formation TSV hole is carried out in described BEOL technical process.
Further, the step in described formation TSV hole is carried out after described BEOL technical process.
From such scheme, can find out, compared with prior art, the manufacture method of the encapsulating structure of low-k chip provided by the present invention and this low-k chip-packaging structure, adopt TSV hole by the top layer connecting line in metal level, by metal level and substrate, directly guide to substrate bottom, and then connect described weld pad by the one end, substrate bottom that is positioned in TSV hole.Compared with prior art, because substrate bottom does not have the dielectric layer of ultralow dielectric, so connect by TSV hole dielectric layer cracked that weld pad can not produce the ultralow dielectric in metal level in substrate bottom, and then improved the CPI problem occurring in prior art.
Accompanying drawing explanation
Fig. 1 is the chip-packaging structure schematic diagram of prior art;
Fig. 2 is the encapsulating structure schematic diagram of low-k chip of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
As shown in Figure 2, the encapsulating structure of low-k chip of the present invention comprises:
Wherein, described substrate 1 can comprise any can be as the basic material that builds semiconductor device thereon, such as silicon substrate, or make the silicon substrate of an isolated area or the silicon substrate on insulating material etc.Described chip 1 is included in formed various semiconductor device of FEOL stage, as active device, passive device etc.Through the FEOL stage, forming classes of semiconductors device is technology known in the art, repeats no more herein.Structure shown in Fig. 2, only for the use of signal, in reality, can be formed with more multi-layered via layer and connecting line layer, chip 2 also can have a plurality of contact holes 3 to be electrically connected to (Fig. 2 only illustrates 1 contact hole 3) with a plurality of through holes 4, and practical structures is determined according to integrated circuit (IC) design (layout).
Described metal level, comprise a plurality of through holes 4 and the Duo Gen connecting line 5 that are wherein mutually electrically connected to, and the dielectric layer 6 that is filled in described through hole 4 and connecting line 5 ultra-low dielectric constant material around, also can adopt the technique in various BEOL stages known in the art to realize, also do not repeat herein.
In the present invention, combine TSV hole technology, top layer connecting line 5t is connected with pad 8 with the one end in TSV hole 9 that guides to the bottom of substrate 1 being connected of pad 8.Compared with prior art, this structure is not because substrate 1 bottom has the dielectric layer 6 of ultralow dielectric, so connect by TSV hole 9 dielectric layer 6 cracked that pads 8 can not produce the ultralow dielectric in metal level in substrate 1 bottom, and then can improve the CPI problem occurring in prior art.
The encapsulating structure of low-k chip provided by the present invention, its manufacture method comprises:
On described chip 2, adopt BEOL technique to form metal level, described metal level comprises a plurality of through holes 4 and the Duo Gen connecting line 5 of mutual electrical connection, and the dielectric layer 6 that is filled in described through hole 4 and connecting line 5 ultra-low dielectric constant material around, the contact hole 3 of bottom through hole 4b in described metal level by described chip 2 is electrically connected to described chip 2, and the top layer dielectric layer 6t in described dielectric layer 6 will be arranged in the top layer connecting line 5t covering of metal level;
On the top layer dielectric layer 6 of described metal level, form pad 8; And
Form TSV hole 9, described TSV hole 9 by the top layer connecting line 5t that is arranged in metal level to substrate 1 described in described substrate 1 bottom break-through.
In addition, said method also comprises: the one end that utilizes metal wire 7 that described pad 8 and described TSV hole 9 are positioned to described substrate 1 bottom is electrically connected to.
In said method, before the step that forms TSV hole 9 can be interspersed in BEOL and FEOL, between and carry out afterwards, that is: the step in described formation TSV hole can be carried out before described FEOL technical process; Or the step in described formation TSV hole can be carried out in described FEOL technical process; Or the step in described formation TSV hole can be after described FEOL technical process, carry out before described BEOL technical process; Or the step in described formation TSV hole can be carried out in described BEOL technical process; Or the step in described formation TSV hole can be carried out after described BEOL technical process.
Below, the process in conjunction with BEOL technical process, FEOL technical process and formation TSV hole, makes introductions all round to above-mentioned several method.
The step in embodiment mono-, described formation TSV hole was carried out before described FEOL technical process.That is, before FEOL technique, just on substrate, form in advance TSV hole, and in follow-up technical process, progressively make the top layer connecting line in TSV hole and metal level couple together.Its process comprises:
FEOL technique substrate is before provided;
In described substrate, form TSV hole;
Adopt FEOL technique to form chip on described substrate;
Adopt BEOL technique to form metal level, and make described TSV hole extend to top layer connecting line in described metal level and be electrically connected to top layer connecting line.
Please refer to the encapsulating structure of the low-k chip of the present invention shown in Fig. 2.In the present embodiment one, the above-mentioned concrete forming process about TSV hole is.
Then can adopt existing TSV hole 9 formation methods, in substrate 1, form TSV hole 9, the whole substrate 1 of now TSV hole 9 break-through.
Subsequently, on described substrate 1, adopt FEOL technique to form chip 2.In existing technique, after FEOL technique, on substrate 1 surface, also deposit interlayer dielectric layer, therefore, in forming the process of chip 2, TSV hole 9 need to be extended in interlayer dielectric layer, to form the structure that runs through substrate 1 and interlayer dielectric layer.So in FEOL technical process, should be noted that depositing, increase the processing for TSV hole 9 in the technical process such as photoetching.Such as after forming interlayer dielectric layer, need to carry out oldly to the photoetching in TSV hole 9 and deposition process, to form from substrate 1, extend to the TSV hole 9 interlayer dielectric layer.
Afterwards, adopt BEOL technique to form metal level.Wherein metal level is by a plurality of through holes 4 that are mutually electrically connected to and Duo Gen connecting line 5, and the dielectric layer 6 that is filled in described through hole 4 and connecting line 5 ultra-low dielectric constant material around forms.So in prior art, the manufacture of metal level, can adopt the method for successively manufacturing, first deposit one deck dielectric layer 6, in this dielectric layer 6, adopt afterwards the means such as photoetching, deposition to form through hole 4 and connecting line 5, adopting same approach to form again one deck dielectric layer 6 on the architecture basics forming before afterwards, and the through hole 4 and the connecting line 5 that are arranged in this dielectric layer 6, repeatedly carry out this process until form final metal level, the preparation of metal level completes the final circuit of having realized semiconductor device in chip 2 and/or between a plurality of chip and connects.
In the present embodiment one, in preparing the process of metal level, should be noted that depositing, increase the processing for TSV hole 9 in the technical process such as photoetching.Such as forming after dielectric layer 6 each, need to carry out oldly to the photoetching in TSV hole 9 and deposition process, to form from substrate 1, extend to the TSV hole 9 each layer of dielectric layer 6, until TSV hole 9 can be electrically connected to top layer connecting line 5t in metal level.
The step in embodiment bis-, described formation TSV hole is carried out in described FEOL technical process.That is, in FEOL technical process, on substrate, form TSV hole, and in follow-up technical process, progressively make top layer connecting line in TSV hole and metal level couple together.
Because FEOL technique is comprised of multiple working procedure, as STI(Shallow Trench Isolation in substrate 1, shallow trench isolation) formation, the formation of trap, CMOS(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) in device the formation of grid structure, the formation in source/drain region etc.In the present embodiment two, the formation step in TSV hole 9 can be carried out between these operations in FEOL technique as required.Substrate 1 is run through in formed TSV hole 9.In operation subsequently, should be noted that the processing to formed TSV hole 9, need to carry out photoetching for TSV hole 9, deposition process etc. when forming interlayer dielectric layer, and forming in the process of metal level in BEOL technique described in embodiment mono-, processing procedure for TSV hole 9, this process can realize according to embodiment mono-and existing common process, repeats no more herein.
The step in embodiment tri-, described formation TSV hole is carried out after described FEOL technical process, before described BEOL technical process.That is, in the chip layer forming at substrate and FEOL, form TSV hole after FEOL technique completes and before BEOL technique starts, and in follow-up technical process, progressively make the top layer connecting line in TSV hole and metal level couple together.
The manufacture cmos device of take is example, and with reference to figure 2.First on substrate 1, form chip 2, chip 2 consists of cmos device, it has comprised NMOS(N-Metal-Oxide-Semiconductor, N-type metal-oxide semiconductor (MOS)) and PMOS(P-Metal-Oxide-Semiconductor, P-type mos) device, NMOS has comprised its grid structure and source/drain electrode, and same, PMOS has comprised its grid structure and source/drain electrode.In the structure forming, generally also there is the structures such as interlayer dielectric layer that are deposited on cmos device surface after completing FEOL technique, in interlayer dielectric layer, also there is the contact hole being connected with extraneous (as metal level) with source/drain electrode for grid.
In the present embodiment three, after completing FEOL technique, forming TSV hole 9 steps need to carry out in the structure that comprises formed chip 2.Take cmos device equally as example, after forming cmos device, the body structure surface forming after whole FEOL technique (for example, on described interlayer dielectric layer surface) utilizes the method in existing formation TSV hole 9, formation runs through the TSV hole 9 of chip layer and substrate 1, now should be noted that TSV hole 9 can not destroy the structure of chip layer (as cmos device) and make its inefficacy.
Enter subsequently BEOL technique, should be noted that depositing, increase the processing for TSV hole 9 in the technical process such as photoetching.For the processing procedure in TSV hole 9, can realize according to embodiment mono-and existing common process, repeat no more herein.
The step in embodiment tetra-, described formation TSV hole is carried out in described BEOL technical process.That is, in BEOL technical process, form TSV hole in the articulamentum in substrate, chip layer and BEOL technique (as the dielectric layer 6 in metal level), and in follow-up technical process, progressively make the top layer connecting line in TSV hole and metal level couple together.
Such as, please refer to shown in Fig. 2, carrying out among BEOL technical process, after having completed wherein the preparation of certain layer of connecting line 5 and through hole 4, carry out the preparation section in TSV hole 9, as: utilize the method in existing formation TSV hole 9, form from this layer of connecting line 5 and the residing dielectric layer 6(of through hole 4 ultra-low dielectric constant material) break-through is to the TSV hole 9 of substrate 1 bottom.
In the BEOL technique continuing subsequently, should be noted that depositing, increase the processing for TSV hole 9 in the technical process such as photoetching.For the processing procedure in TSV hole 9, can realize according to embodiment mono-and existing common process, repeat no more herein.
The step in embodiment five, described formation TSV hole is carried out after described BEOL technical process.That is, after BEOL technique completes, form TSV hole in the articulamentum in substrate, chip layer and BEOL technique (as the dielectric layer in metal level), and directly from top layer connecting line, be connected to the bottom of substrate.
Please refer to shown in Fig. 2, in the present embodiment five, specifically, treat through after BEOL technique, be formed with and comprised substrate 1, chip 2 and metal level (comprise wherein a plurality of through holes 4 and the Duo Gen connecting line 5 that are mutually electrically connected to, and the dielectric layer 6 that is filled in described through hole 4 and connecting line 5 ultra-low dielectric constant material around).In this structure, utilize the method in existing formation TSV hole 9, form directly the TSV hole 9 from top layer connecting line 5t to substrate 1 bottom.
After forming described TSV hole 9, can on the residing dielectric layer 6 of top layer connecting line 5t, deposit top layer dielectric layer 6t, with top layer connecting line 5t described in covering.
The encapsulating structure of the low-k chip that the invention described above provides and the manufacture method of this low-k chip-packaging structure, adopt TSV hole by the top layer connecting line in metal level, by metal level and substrate, directly guide to substrate bottom, and then connect described weld pad by the one end, substrate bottom that is positioned in TSV hole.Compared with prior art, because substrate bottom does not have the dielectric layer of ultralow dielectric, so connect by TSV hole dielectric layer cracked that weld pad can not produce the ultralow dielectric in metal level in substrate bottom, and then improved the CPI problem occurring in prior art.
In the present invention, do not add the technical process of detailed description and technological parameter etc., those skilled in the art all can, according to existing techniques in realizing, repeat no more herein.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (9)
1. an encapsulating structure for low-k chip, is characterized in that, comprising:
Substrate;
Process formed chip of FEOL stage on described substrate;
Process formed metal level of BEOL stage on described chip; Described metal level comprises at least 1 through hole and at least 1 connecting line of mutual electrical connection, and the dielectric layer that is filled in described through hole and connecting line ultra-low dielectric constant material around; Bottom through hole in described metal level is electrically connected to described chip by the contact hole of described chip; Top layer dielectric layer in described dielectric layer covers the top layer connecting line that is arranged in metal level;
By the top layer connecting line that is arranged in metal level to described substrate bottom, and the TSV hole of substrate described in break-through;
Be positioned at the pad on the top layer dielectric layer of described metal level, one end that described pad is positioned at described substrate bottom by metal wire and described TSV hole is electrically connected to.
2. the encapsulating structure of low-k chip according to claim 1, is characterized in that: described chip is included in the various semiconductor device that the FEOL stage forms.
3. the encapsulating structure of low-k chip according to claim 1, is characterized in that: the material in described TSV hole is Al, Cu, W or their alloy.
4. a manufacture method for low-k chip-packaging structure, comprising:
Substrate is provided and on described substrate, adopts FEOL technique to form chip;
On described chip, adopt BEOL technique to form metal level, described metal level comprises at least 1 through hole and at least 1 connecting line of mutual electrical connection, and the dielectric layer that is filled in described through hole and connecting line ultra-low dielectric constant material around, bottom through hole in described metal level is electrically connected to described chip by the contact hole of described chip, and the top layer dielectric layer in described dielectric layer covers the top layer connecting line that is arranged in metal level;
On the top layer dielectric layer of described metal level, form pad; And
Form TSV hole, described TSV hole by the top layer connecting line that is arranged in metal level to described substrate bottom substrate described in break-through also.
5. the manufacture method of low-k chip-packaging structure according to claim 4, is characterized in that:
The step in described formation TSV hole was carried out before described FEOL technical process.
6. the manufacture method of low-k chip-packaging structure according to claim 4, is characterized in that:
The step in described formation TSV hole is carried out in described FEOL technical process.
7. the manufacture method of low-k chip-packaging structure according to claim 4, is characterized in that:
The step in described formation TSV hole is carried out after described FEOL technical process, before described BEOL technical process.
8. the manufacture method of low-k chip-packaging structure according to claim 4, is characterized in that:
The step in described formation TSV hole is carried out in described BEOL technical process.
9. the manufacture method of low-k chip-packaging structure according to claim 4, is characterized in that:
The step in described formation TSV hole is carried out after described BEOL technical process.
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| CN107946246A (en) * | 2016-10-12 | 2018-04-20 | 中芯国际集成电路制造(上海)有限公司 | Seal ring structure, semiconductor devices and electronic device |
| CN109712963A (en) * | 2018-12-29 | 2019-05-03 | 上海华力集成电路制造有限公司 | CPI tests structure and the failure analysis method based on the structure |
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