CN103681460A - Manufacture method of electronic element - Google Patents

Manufacture method of electronic element Download PDF

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Publication number
CN103681460A
CN103681460A CN201210325572.8A CN201210325572A CN103681460A CN 103681460 A CN103681460 A CN 103681460A CN 201210325572 A CN201210325572 A CN 201210325572A CN 103681460 A CN103681460 A CN 103681460A
Authority
CN
China
Prior art keywords
screen
chip
manufacturing
integrated circuit
electronic elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201210325572.8A
Other languages
Chinese (zh)
Inventor
张钦崇
宋尚霖
郑伟鸣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xinxing Electronics Co Ltd
Unimicron Technology Corp
Original Assignee
Xinxing Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xinxing Electronics Co Ltd filed Critical Xinxing Electronics Co Ltd
Priority to CN201210325572.8A priority Critical patent/CN103681460A/en
Publication of CN103681460A publication Critical patent/CN103681460A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The invention discloses a manufacture method of an electronic element, and provides an integrated circuit chip. The integrated-circuit chip comprises an active surface, a back surface opposite to the active surface, and a side surface connected with the active surface and the back surface. Then, a shielding layer covering the back surface and the side surface comprehensively and directly is formed. As the shielding layer is directly formed on the surface of the integrated circuit chip, an electronic device can be thinned and lightened.

Description

Manufacturing method of electronic elements
Technical field
The present invention relates to a kind of manufacturing method of electronic elements, and particularly relate to a kind of manufacturing method of electronic elements with screen.
Background technology
At present the assembling mode of general electronic component normally by welding electronic elements to circuit board.If run into electromagnetic interference (Electro-Magnetic Interference, EMI), conventionally can add Faraday cage (Faraday cage), to obtain best electrical quality.The principle of Faraday cage is for example, by the interceptor (-ter) of a conduction (crown cap) electric interference do not had to nocuity and reflects or be sent to ground connection.Yet the Faraday cage that is enclosed in electronic component periphery has also increased required space and the weight of configuration electronic component simultaneously, but this is unfavorable for slimming and the lightweight of electronic product.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing method of electronic elements, in order to produce the electronic component with electro-magnetic screen function.
For reaching above-mentioned purpose, the present invention proposes a kind of manufacturing method of electronic elements.One integrated circuit (IC) chip is provided, wherein integrated circuit (IC) chip there is an active face, with respect to the back side of active face and connect the side at active face and the back side.Then, form a screen, wherein screen covers the back side and side comprehensively and directly.
Based on above-mentioned, be compared to existing Faraday cage and take larger space and there is larger weight, the present invention is formed directly into screen on the surface of integrated circuit (IC) chip, therefore be conducive to slimming and the lightweight of electronic installation.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 C be one embodiment of the invention manufacturing method of electronic elements analyse and observe flow chart;
Fig. 2 is the profile that the electronic component of Fig. 1 C is mounted to circuit board;
Fig. 3 A is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board;
Fig. 3 B is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board;
Fig. 4 A is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board;
Fig. 4 B is the enlarged drawing at the X position of Fig. 4 A;
Fig. 5 A is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board;
Fig. 5 B is the local face upwarding stereogram of the electronic component of Fig. 5 A.
Main element symbol description
100a, 100b, 100c, 100d, 100e: electronic component
110: integrated circuit (IC) chip
110a: active face
110b: the back side
110c: side
112: connection pad
114: line stretcher
116: interior guide hole
118: intraconnections
119a: substrate
119b: multiple internal connecting lines structure
120: screen
130: conductive projection
200: circuit board
Embodiment
The flow chart of analysing and observe that Figure 1A to Fig. 1 C is the manufacturing method of electronic elements according to one embodiment of the invention.Please refer to Figure 1A, first, provide an integrated circuit (IC) chip 110, wherein integrated circuit (IC) chip there is an active face 110a, with respect to a back side 110b of this active face 110a and connect this active face 110a and a side 110c of this back side 110b.
In the present embodiment, integrated circuit (IC) chip 110 can be semiconductor integrated circuit (IC) chip, on the wafer of semiconductor material, make integrated circuit after the bare chip that forms of cutting.Aforesaid semiconductor material is for example silicon.With regard to electrical functionality, integrated circuit (IC) chip 110 is the chips that need electromagnetic shielding, such as CPU (CPU) chip, graphics processing unit (GPU) chip and microprocessor (microprocessor) chip etc.
Please refer to Figure 1B, then, form a screen 120, wherein screen 120 covers back side 110b and side 110c comprehensively and directly, in order to electromagnetic shielding to be provided.In the present embodiment, screen 120 can be formed by physical vapor deposition (PVD).Particularly, screen 120 can be formed by sputter (sputtering) or evaporation (evaporating).In addition, the material of screen 120 can comprise metal, such as copper, stainless steel, aluminium or gold etc.
It should be noted that, being compared to existing Faraday cage takies larger space and has larger weight, screen 120 is to be directly formed on all sidedly back side 110b and the side 110c of integrated circuit (IC) chip 110, thereby is conducive to slimming and the lightweight of electronic installation.
Please refer to Fig. 1 C, then, form a plurality of conductive projections 130.Integrated circuit (IC) chip 110 has a plurality of connection pads 112 on active face 110a, and these conductive projections 130 are connected on these connection pads 112.
Fig. 2 is the profile that the electronic component of Fig. 1 C is mounted to circuit board.Please refer to Fig. 2, the electronic component of Fig. 1 C can carry out connecting circuit board 200 by these conductive projections 130, for example motherboard or module board.
Fig. 3 A is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board.Please refer to Fig. 3 A, be compared to the electronic component 100a of Fig. 2, the integrated circuit (IC) chip 110 of the electronic component 100b of the present embodiment also has a line stretcher 114, and it extends to side 110c and connect screen 120 from connection pad 112.Therefore, formed screen 120 can utilize line stretcher 114 to be connected to the earth terminal of integrated circuit (IC) chip 110.
Fig. 3 B is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board.Please refer to Fig. 3 B, be compared to the electronic component 100 of Fig. 2, the integrated circuit (IC) chip 110 of the electronic component 100c of the present embodiment also has an interior guide hole 116, i.e. so-called silicon perforation (Through Silicon Via, TSV), and interior guide hole 116 extend to back side 110b and connect screen 120.Therefore, formed screen 120 can utilize interior guide hole 116 to be connected to the earth terminal of integrated circuit (IC) chip 110.
Fig. 4 A is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board, and Fig. 4 B is the enlarged drawing at the X position of Fig. 4 A.Please refer to Fig. 4 A and Fig. 4 B, be compared to the electronic component 100 of Fig. 2, the integrated circuit (IC) chip 110 of the electronic component 100d of the present embodiment has one or more intraconnections 118, and these intraconnections 118 extend to side 110c and connect screen 120.Therefore, formed screen 120 can utilize these intraconnections 118 to be connected to the earth terminal of integrated circuit (IC) chip 110.Particularly, integrated circuit (IC) chip 110 comprises a substrate 119a and a multiple internal connecting lines structure 119b on substrate 119a, and the part that these intraconnections 118 are multiple internal connecting lines structure 119b.
Fig. 5 A is the profile that the electronic component of another embodiment of the present invention is mounted to circuit board, and Fig. 5 B is the local face upwarding stereogram of the electronic component of Fig. 5 A.Please refer to Fig. 5 A and Fig. 5 B, be compared to the electronic component 100 of Fig. 2, the screen 120 of the electronic component 100e of the present embodiment also covers the active face 110a of integrated circuit (IC) chip 110, but does not cover and expose these connection pads 112.Therefore, formed screen 120 can provide more complete electromagnetic shielding.
In sum, be compared to existing Faraday cage and take larger space and have larger weight, the present invention is formed directly into screen on the surface of integrated circuit (IC) chip, therefore be conducive to slimming and the lightweight of electronic installation.
Although disclosed the present invention in conjunction with above embodiment; yet it is not in order to limit the present invention; under any, in technical field, be familiar with this operator; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.

Claims (11)

1. a manufacturing method of electronic elements, comprising:
One integrated circuit (IC) chip is provided, wherein this integrated circuit (IC) chip there is active face, with respect to the back side of this active face and connect the side at this active face and this back side; And
Form a screen, wherein this screen covers Ji Gai side, this back side comprehensively and directly.
2. manufacturing method of electronic elements as claimed in claim 1, wherein this integrated circuit (IC) chip is semiconductor integrated circuit (IC) chip.
3. manufacturing method of electronic elements as claimed in claim 1, wherein this integrated circuit (IC) chip is a bare chip.
4. manufacturing method of electronic elements as claimed in claim 1, wherein, in forming the step of this screen, forms this screen with physical vapour deposition (PVD).
5. manufacturing method of electronic elements as claimed in claim 1, wherein, in forming the step of this screen, forms this screen with sputter or evaporation.
6. manufacturing method of electronic elements as claimed in claim 1, wherein the material of this screen comprises metal.
7. manufacturing method of electronic elements as claimed in claim 1, wherein the material of this screen comprises copper, stainless steel, aluminium or gold.
8. manufacturing method of electronic elements as claimed in claim 1, wherein this integrated circuit (IC) chip has a plurality of connection pads on this active face.
9. manufacturing method of electronic elements as claimed in claim 8, also comprises:
Form a plurality of conductive projections, be connected on these connection pads.
10. manufacturing method of electronic elements as claimed in claim 8, wherein, in forming the step of this screen, this screen also covers this active face, and this screen does not cover these connection pads.
11. manufacturing method of electronic elements as claimed in claim 8, wherein, in forming the step of this screen, this integrated circuit (IC) chip has a line stretcher, and this line stretcher extends to this side and connects this screen from this connection pad.
CN201210325572.8A 2012-09-05 2012-09-05 Manufacture method of electronic element Pending CN103681460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210325572.8A CN103681460A (en) 2012-09-05 2012-09-05 Manufacture method of electronic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210325572.8A CN103681460A (en) 2012-09-05 2012-09-05 Manufacture method of electronic element

Publications (1)

Publication Number Publication Date
CN103681460A true CN103681460A (en) 2014-03-26

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CN201210325572.8A Pending CN103681460A (en) 2012-09-05 2012-09-05 Manufacture method of electronic element

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090302437A1 (en) * 2008-06-10 2009-12-10 Stats Chippac, Ltd. Semiconductor Device and Method of Connecting a Shielding Layer to Ground Through Conductive Vias
US20120018863A1 (en) * 2010-07-23 2012-01-26 Tessera Research Llc Microelectronic elements with rear contacts connected with via first or via middle structures
CN102473690A (en) * 2009-08-18 2012-05-23 日本电气株式会社 Semiconductor device having shield layer and element-side power supply terminal capacitively coupled therein

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090302437A1 (en) * 2008-06-10 2009-12-10 Stats Chippac, Ltd. Semiconductor Device and Method of Connecting a Shielding Layer to Ground Through Conductive Vias
CN102473690A (en) * 2009-08-18 2012-05-23 日本电气株式会社 Semiconductor device having shield layer and element-side power supply terminal capacitively coupled therein
US20120018863A1 (en) * 2010-07-23 2012-01-26 Tessera Research Llc Microelectronic elements with rear contacts connected with via first or via middle structures

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Application publication date: 20140326