CN103681445A - Groove isolation structure and preparation method thereof - Google Patents
Groove isolation structure and preparation method thereof Download PDFInfo
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- CN103681445A CN103681445A CN201210328477.3A CN201210328477A CN103681445A CN 103681445 A CN103681445 A CN 103681445A CN 201210328477 A CN201210328477 A CN 201210328477A CN 103681445 A CN103681445 A CN 103681445A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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Abstract
The invention discloses a groove isolation structure and a preparation method thereof. The preparation method of the groove isolation structure comprises the following steps: providing a semiconductor substrate, wherein an oxide layer and a barrier layer are formed on the semiconductor substrate; etching the barrier layer, the oxide layer and the semiconductor substrate to form a groove in the semiconductor substrate; filling the groove to from an oxide filling layer; removing the part, on the barrier layer, of the oxide filling layer through a chemical mechanical grinding process; removing part of the oxide filling layer in the groove; forming an isolation layer on the surfaces of the oxide filling layer and the barrier layer; removing the barrier layer and the part, on the barrier layer, of the isolation layer. According to the invention, oxygen in the oxide filling layer is prevented from diffusing into a grid dielectric layer or layers adjacent to the oxide filling layer so as not to affect the electrical properties of the device; the groove isolation structure is conducive to improving the reliability of the semiconductor device.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, relate in particular to a kind of groove isolation construction and preparation method thereof
Background technology
In semiconductor integrated circuit technique, each foundry skill all, reducing voltage, reaches higher integrated level and more high performance product to reduce transistorized power consumption.Reduce gate dielectric thickness and be the wherein easy way that does not cause again extra cost, but when gate dielectric layer thickness is reduced to 5nm when following, increasing electronics is because quantum tunneling effect passes gate dielectric, not only make transistor normally not work, also cause a large amount of electric leakages and meaningless power consumption.In order to address this problem, adopt high K(relative dielectric constant) silica that uses before substituting of medium, can obtain a thinner equivalent silicon oxide isolation thickness (Equivalent Oxide Thickness, be called for short EOT), that is to say, can under the prerequisite that does not increase electrical thickness, allow increases thickness of insulating layer, can guarantee technological requirement, thereby can continue to carry out reduction of device size according to Moore's Law.
Detailed, please refer to Figure 1A to Fig. 1 C, the generalized section of its each step corresponding construction that is existing groove isolation construction manufacturing method.
Shown in Figure 1A, first Semiconductor substrate 101 is provided, in described Semiconductor substrate 101, comprise oxide layer 102 and barrier layer 103.Barrier layer 103 is conduct barrier layers of cmp afterwards, prevents from grinding Shi Dui lower floor and causes damage.
Then, barrier layer 103, oxide layer 102 and Semiconductor substrate 101 form groove in Semiconductor substrate 101 described in etching.
Then, utilize HARP technique to fill groove, form oxide packed layer 104, described oxide packed layer 104 also covers the surface on described barrier layer 103.Conventionally, the material of described oxide packed layer 104 is silica.
Shown in Figure 1B, cmp is carried out in oxide packed layer 104 surfaces, the unnecessary silica that while removing trench fill, 103 surfaces form on barrier layer.
Shown in figure 1C, remove the barrier layer 103 in Semiconductor substrate 101.Conventionally use the method for etching to remove barrier layer 103.
Yet, in actual production, find, utilize in groove isolation construction that said method the forms high-temperature annealing process process after follow-up metal gates forms, oxygen in oxide packed layer is easily diffused in the gate dielectric or adjacent layer on its upper strata, the dielectric constant step-down that causes gate dielectric, the electrical property variation of device, affects reliability and the yield of product.
Summary of the invention
The invention provides a kind of groove isolation construction and preparation method thereof, to solve oxygen element in oxide packed layer, be easily diffused in gate dielectric or adjacent layer, make the problem of the electrical property variation of device.
For addressing the above problem, the present invention discloses a kind of manufacture method of trench isolations, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, is formed with oxide layer and barrier layer; Barrier layer, oxide layer and Semiconductor substrate described in etching form groove in described Semiconductor substrate; Described groove is filled, form oxide packed layer; Utilize chemical mechanical milling tech to remove the oxide packed layer on described barrier layer; Remove the partial oxide packed layer in described groove; At described oxide packed layer and barrier layer surface, form separator; And the separator of removing barrier layer and top, barrier layer.
Optionally, the material of described oxide packed layer is silica.
Optionally, described oxide packed layer is carried out partly removing and utilizing wet-etching technology to realize.
Optionally, it is characterized in that, the etching liquid that described wet-etching technology is used is the hydrofluoric acid of dilution, and etch period is 10 seconds～200 seconds.
Optionally, described separator material is the oxygen-free material that dielectric constant is close or identical with the dielectric constant of oxide packed layer material.
Optionally, it is characterized in that, described separator is formed by physical gas-phase deposition, also can be formed by chemical vapor deposition method.
Optionally, it is characterized in that, described separator material is boron nitride.
Optionally, it is characterized in that, the boron nitride that described separator forms is doped with carbon.
Optionally, described separation layer thickness is
Optionally, with chemical mechanical milling tech, remove the separator of barrier layer and top, barrier layer.
Accordingly, the present invention also provides a kind of groove isolation construction being formed by above-mentioned manufacture method, comprising: be formed at the groove in Semiconductor substrate; Be filled in the oxide packed layer in described groove; And be filled in described groove and cover the separator on oxide packed layer.
Compared with prior art, groove isolation construction of the present invention has comprised oxide packed layer and its surperficial separator, separator plays isolation from oxygen Elements Diffusion to the effect in the gate dielectric of high-k or adjacent layer, prevent that it from impacting device electrical performance, be conducive to improve the reliability of semiconductor device.
Accompanying drawing explanation
Figure 1A～1C is the generalized section of each step corresponding construction of existing groove structure filling;
Fig. 2 is the flow chart of the manufacture method of groove isolation construction provided by the present invention;
Fig. 3 A～3F is the generalized section of each step corresponding construction of groove structure filling provided by the present invention.
Embodiment
Described in background technology, after high-temperature annealing process after metal gates forms, oxygen element in oxide packed layer can be diffused in the gate dielectric or adjacent layer of high-k, makes its relative dielectric constant step-down, and equivalent silicon oxide insulation thickness increases.Make the electrical property variation of device, affect the problem of its effect and reliability.Therefore, the present invention proposes a kind of groove isolation construction and preparation method thereof, described groove isolation construction comprises oxide packed layer and its surperficial separator, separator plays isolation from oxygen Elements Diffusion to the effect in the gate dielectric of high-k or adjacent layer, prevent that it from impacting device electrical performance, be conducive to improve the reliability of semiconductor device.
Please refer to Fig. 2, the flow chart of the manufacture method of the isolation structure that it provides for the embodiment of the present invention, in conjunction with this Fig. 2, the method comprises the following steps:
Step S21, provides Semiconductor substrate, is formed with oxide layer and barrier layer in described Semiconductor substrate;
Step S22, barrier layer, oxide layer and Semiconductor substrate form groove in described Semiconductor substrate described in etching;
Step S23, fills described groove, forms oxide packed layer;
Step S24, utilizes chemical mechanical milling tech to remove the oxide packed layer on described barrier layer;
Step S25, removes the partial oxide packed layer in described groove;
Step S26, forms separator at described oxide packed layer and barrier layer surface;
Step S27, removes the separator of barrier layer and top, barrier layer.
Below in conjunction with generalized section, the present invention is described in more detail, has wherein represented the preferred embodiments of the present invention, should the described those skilled in the art of understanding can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to the restriction of relevant system or relevant business, by an embodiment, change into another embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with reference to accompanying drawing, with way of example, the present invention is more specifically described.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Shown in figure 3A, and integrating step S21, first Semiconductor substrate 301 is provided, in described Semiconductor substrate, be formed with oxide layer 302 and barrier layer 303.Described oxide layer 302 is for reducing the stress between Semiconductor substrate 301 and barrier layer 303; Described barrier layer 303 is conduct barrier layers of cmp afterwards, prevents from grinding Shi Dui lower floor and causes damage.
Continue with reference to figure 3A, integrating step S22, follows, and barrier layer 303, oxide layer 302 and Semiconductor substrate 301 form groove in Semiconductor substrate 301 described in etching.
Continue with reference to figure 3A, integrating step S23, fills groove, forms oxide packed layer 304.Preferably, utilize HARP technique to fill groove, the material of described oxide packed layer 304 is silica.
Shown in figure 3B, and integrating step S24, utilize chemical mechanical milling tech to remove the oxide packed layer 304 on described barrier layer 303.
Shown in figure 3C, and integrating step S25, remove the partial oxide packed layer 304 in described groove, the opening that is removed rear formation is used for forming the separator of isolation from oxygen diffusion in subsequent step.Described oxide packed layer is carried out partly removing and can utilizing wet etching or dry etch process to realize, in the present embodiment, adopt wet-etching technology, the hydrofluoric acid that the etching liquid using preferably dilutes, etch period is 10 seconds～200 seconds.Certainly, wet-etching technology of the present invention is used etching liquid kind and etching technics parameter.
Shown in figure 3D, and integrating step S26, at described oxide packed layer 304 and barrier layer 303 surface deposition separators 305.Described separator 305 materials are preferably the oxygen-free material that dielectric constant is close or identical with the dielectric constant of oxide packed layer material, select boron nitride in the present embodiment.Described separator 305 can be formed by physical vapour deposition (PVD) or chemical vapour deposition (CVD) mode, and described separator 304 thickness are
owing to there being the existence of separator 305, can greatly reducing oxygen in subsequent anneal technical process and be diffused into the gate dielectric of high-k or the probability in adjacent layer.Further, can be in separator 305 materials doping carbon, can capture the oxygen that diffuses to separator, obtain better isolation effect.
Shown in figure 3E, and integrating step S27, remove the separator of barrier layer 303 and 303 tops, barrier layer.The unnecessary separator 305 that can use cmp to deposit in step before removing.Barrier layer 303 is used the method for etching to remove conventionally.Afterwards, enter conventional transistor device manufacturing process, repeat no more herein.
The present invention also provides a kind of groove isolation construction, and shown in Fig. 3 A to Fig. 3 E, the groove isolation construction that the manufacture method based on above-mentioned groove isolation construction forms, comprising:
Be formed at the groove in Semiconductor substrate 301;
Be filled in the oxide packed layer 304 in described groove; And
Be filled in described groove and cover the separator 305 on oxide packed layer 304.
Described oxide packed layer 304 is generally silica, and described separator 305 is preferably close or the identical and oxygen-free material of the dielectric constant of dielectric constant and oxide packed layer 304, and separator described in the present embodiment 305 is boron nitride.Preferably, can be in boron nitride doping carbon, be used for capturing diffusion oxygen so far, to reach better isolation effect.
In sum, the invention provides a kind of groove isolation construction and preparation method thereof, in oxide packed layer surface coverage one deck separator, described separator can play isolation from oxygen Elements Diffusion to the effect in gate dielectric or adjacent layer, prevent that it from impacting device electrical performance, be conducive to improve the reliability of semiconductor device.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (11)
1. a manufacture method for groove isolation construction, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with oxide layer and barrier layer;
Barrier layer, oxide layer and Semiconductor substrate described in etching form groove in described Semiconductor substrate;
Described groove is filled, form oxide packed layer;
Utilize chemical mechanical milling tech to remove the oxide packed layer on described barrier layer;
Remove the partial oxide packed layer in described groove;
At described oxide packed layer and barrier layer surface, form separator; And
Remove the separator of described barrier layer and top, barrier layer.
2. the manufacture method of groove isolation construction as claimed in claim 1, is characterized in that, the material of described oxide packed layer is silica.
3. the manufacture method of groove isolation construction as claimed in claim 2, is characterized in that, utilizes wet-etching technology to remove the partial oxide packed layer in described groove.
4. the manufacture method of groove isolation construction as claimed in claim 3, is characterized in that, the etching liquid that described wet-etching technology is used is the hydrofluoric acid of dilution, and etch period is 10 seconds～200 seconds.
5. the manufacture method of groove isolation construction as claimed in claim 1, described separator is the oxygen-free material that dielectric constant is close or identical with the dielectric constant of described oxide packed layer.
6. the manufacture method of groove isolation construction as claimed in claim 5, is characterized in that, described separator is formed by physical gas-phase deposition or chemical vapor deposition method.
7. the manufacture method of groove isolation construction as claimed in claim 6, is characterized in that, described separator material is boron nitride.
8. the manufacture method of groove isolation construction as claimed in claim 7, is characterized in that, in described boron nitride doped with carbon.
9. the manufacture method of groove isolation construction as claimed in claim 8, is characterized in that, the thickness of described separator is
10. the manufacture method of groove isolation construction as claimed in claim 1, is characterized in that, utilizes chemical mechanical milling tech to remove the separator of barrier layer and top, barrier layer.
11. 1 kinds are utilized the groove isolation construction that in claim 1 to 10, the manufacture method described in any one forms, and it is characterized in that, comprising:
Be formed at the groove in Semiconductor substrate;
Be filled in the oxide packed layer in described groove; And
Be filled in described groove and cover the separator on oxide packed layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210328477.3A CN103681445B (en) | 2012-09-06 | 2012-09-06 | Groove isolation construction and preparation method thereof |
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| CN201210328477.3A CN103681445B (en) | 2012-09-06 | 2012-09-06 | Groove isolation construction and preparation method thereof |
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| CN103681445A true CN103681445A (en) | 2014-03-26 |
| CN103681445B CN103681445B (en) | 2016-11-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113830726A (en) * | 2020-06-23 | 2021-12-24 | 无锡华润上华科技有限公司 | Manufacturing method of semiconductor device and semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825277A (en) * | 1987-11-17 | 1989-04-25 | Motorola Inc. | Trench isolation process and structure |
| US7141485B2 (en) * | 2003-06-13 | 2006-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits |
| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| US20100006975A1 (en) * | 2008-07-08 | 2010-01-14 | Semiconductor Manufacturing International (Shanghai) Corporation | Method of eliminating micro-trenches during spacer etch |
-
2012
- 2012-09-06 CN CN201210328477.3A patent/CN103681445B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825277A (en) * | 1987-11-17 | 1989-04-25 | Motorola Inc. | Trench isolation process and structure |
| US7141485B2 (en) * | 2003-06-13 | 2006-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits |
| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| US20100006975A1 (en) * | 2008-07-08 | 2010-01-14 | Semiconductor Manufacturing International (Shanghai) Corporation | Method of eliminating micro-trenches during spacer etch |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113830726A (en) * | 2020-06-23 | 2021-12-24 | 无锡华润上华科技有限公司 | Manufacturing method of semiconductor device and semiconductor device |
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