CN103676375A - Array substrate and manufacturing method thereof - Google Patents
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- CN103676375A CN103676375A CN201310660914.6A CN201310660914A CN103676375A CN 103676375 A CN103676375 A CN 103676375A CN 201310660914 A CN201310660914 A CN 201310660914A CN 103676375 A CN103676375 A CN 103676375A
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- base palte
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Abstract
The invention discloses an array substrate and a manufacturing method of the array substrate. The array substrate comprises a glass substrate, data lines formed on the glass substrate, grid lines, a thin film transistor and a first insulating layer covering the data lines, the grid lines and the thin film transistor. The array substrate further comprises a conductive shielding layer which is located on the first insulating layer and is electrically connected with a grounding terminal. The conductive shielding layer is located in the area where the data lines, the grid lines and the thin film transistor are located. The array substrate improves display quality.
Description
Technical field
The present invention relates to display technique field, particularly a kind of array base palte and preparation method thereof.
Background technology
The basic structure of thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal display (Liquid Crystal Display, LCD) comprises array base palte, color membrane substrates, and is filled in the liquid crystal layer between two plate bases.
On array base palte, comprise crisscross data line and grid line, these data lines and grid line are staggered to form sub-pix region one by one, in each sub-pix region, are provided with a TFT.
Each TFT is connected with a grid line with a data line, under the acting in conjunction of the gate drive signal of grid line transmission and the data-signal of data line transmission, by pixel electrode and public electrode, at liquid crystal layer, form electric field, and then realize demonstration by the deflection of electric field controls liquid crystal molecule.
Can find, the display performance of TFT-LCD is closely related with electric field, but the real electric field relevant to demonstration is the electric field being produced by pixel electrode and public electrode, and it is undesired signal that electric field in addition all should be considered as, and can cause adverse effect to showing.
For example, when black state shows, the liquid crystal at data line edge not only can be subject to the impact of the electric field of pixel electrode and public electrode generation, simultaneously due to the impact being subject to from the electric field of data line, causes light leakage phenomena.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of array base palte and preparation method thereof, improves display quality.
To achieve these goals, the embodiment of the present invention provides a kind of array base palte, comprising:
Glass substrate;
Be formed at data line, grid line and thin film transistor (TFT) on glass substrate;
Cover the first insulation course of described data line, grid line, thin film transistor (TFT);
Wherein, described array base palte also comprises:
Be positioned at described the first insulation course top, the conductive shielding layer being electrically connected to ground terminal;
Wherein, described conductive shielding layer is positioned at described data line, grid line and thin film transistor (TFT) region.
Above-mentioned array base palte, wherein, described array base palte is horizontal electric field type array base palte, described array base palte also comprises:
The public electrode being covered by described the first insulation course;
Be formed on described the first insulation course, and described public electrode forms the pixel electrode of horizontal component of electric field;
Described pixel electrode and described conductive shielding layer are positioned at same layer, and mutually isolate with described conductive shielding layer.
Above-mentioned array base palte, wherein, described transparency electrode and conductive shielding layer form by a composition technique.
Above-mentioned array base palte, wherein, described array base palte is horizontal electric field type array base palte, described array base palte also comprises:
The pixel electrode being covered by described the first insulation course;
Be formed on described the first insulation course, and described pixel electrode forms the public electrode of horizontal component of electric field;
Cover the second insulation course of described public electrode;
Described conductive shielding layer is formed on described the second insulation course, by described the second insulation course and described public electrode, isolates.
Above-mentioned array base palte, wherein, comprising:
On glass substrate, form data line, grid line and thin film transistor (TFT);
Form the insulation course that covers described data line, grid line and thin film transistor (TFT);
Formation is positioned at described the first insulation course top, the conductive shielding layer being electrically connected to ground terminal;
Wherein, described conductive shielding layer is positioned at described data line, grid line and thin film transistor (TFT) region.
Above-mentioned array base palte, wherein, described array base palte is horizontal electric field type array base palte, described method for making also comprises:
The public electrode that formation is covered by described the first insulation course;
On described the first insulation course, form pixel electrode;
Described pixel electrode and described conductive shielding layer are positioned at same layer, and mutually isolate with described conductive shielding layer.
Above-mentioned array base palte, wherein, described transparency electrode and conductive shielding layer form by a composition technique.
Above-mentioned array base palte, wherein, described array base palte is horizontal electric field type array base palte, described method for making also comprises:
The pixel electrode that formation is covered by described the first insulation course;
On described the first insulation course, form public electrode;
Form the second insulation course that covers described public electrode;
Described conductive shielding layer is formed on described the second insulation course, by described the second insulation course and described public electrode, isolates.
Array base palte of the embodiment of the present invention and preparation method thereof, by the conductive shielding layer of ground connection is set above data line, grid line and thin film transistor (TFT) region, the electric field that the electric signal transmitting on can reduce/block data line, grid line and thin film transistor (TFT) produces is transferred to the ratio of liquid crystal layer, therefore can reduce the electric field of the electric signal generation of transmitting on data line, grid line and thin film transistor (TFT) to the impact showing, improve display quality.
Simultaneously, the electric field producing due to the electric signal transmitting on data line, grid line and thin film transistor (TFT) reduces the impact of liquid crystal layer, therefore the light leakage phenomena under black state also can improve, and no longer needs large-sized black matrix to block light leak, therefore can improve the aperture opening ratio of pixel.
Accompanying drawing explanation
Fig. 1 a-Fig. 1 c represents respectively the conductive shielding layer of the embodiment of the present invention and the relative position relation schematic diagram of grid line, data line and thin film transistor (TFT);
Fig. 2 represents a kind of relative position relation schematic diagram between conductive shielding layer and pixel electrode in the array base palte of reversion ADS pattern of the embodiment of the present invention;
Fig. 3 represents the another kind of relative position relation schematic diagram between conductive shielding layer and pixel electrode in the array base palte of reversion ADS pattern of the embodiment of the present invention;
Fig. 4 a-Fig. 4 j represents the schematic diagram of concrete manufacturing process of the array base palte of the embodiment of the present invention.
Embodiment
Array base palte of the embodiment of the present invention and preparation method thereof, mentions display quality by the conductive shielding layer of ground connection is set above data line, grid line and thin film transistor (TFT) region.
Before the embodiment of the present invention is further elaborated, some concepts that first embodiment of the present invention related to describe, so that better understand the embodiment of the present invention.
A kind of array base palte of the embodiment of the present invention, comprising:
Glass substrate;
Be formed at data line, grid line and thin film transistor (TFT) on glass substrate;
Cover the first insulation course of described data line, grid line, thin film transistor (TFT);
Described array base palte also comprises:
Be positioned at described the first insulation course top, the conductive shielding layer being electrically connected to ground terminal;
Wherein, described conductive shielding layer is positioned at described data line, grid line and thin film transistor (TFT) region.
Array base palte of the embodiment of the present invention and preparation method thereof, by the conductive shielding layer of ground connection is set above data line, grid line and thin film transistor (TFT) region, the electric field that the electric signal transmitting on can reduce/block data line, grid line and thin film transistor (TFT) produces is transferred to the ratio of liquid crystal layer, therefore can reduce the electric field of the electric signal generation of transmitting on data line, grid line and thin film transistor (TFT) to the impact showing, improve display quality.
Simultaneously, the electric field producing due to the electric signal transmitting on data line, grid line and thin film transistor (TFT) reduces the impact of liquid crystal layer, therefore the light leakage phenomena under black state also can improve, and no longer needs large-sized black matrix to block light leak, therefore can improve the aperture opening ratio of pixel.
In specific embodiments of the invention, data line, grid line and thin film transistor (TFT) are as induction source, and liquid crystal layer is as pick-up, when increase the conductive shielding layer of a ground connection between induction source and pick-up, this conductive shielding layer can and induction source between the stray capacitance that produces be shorted to ground, therefore by suppressing the coupling of stray capacitance, reached the object of electric field shielding.
The array base palte of the specific embodiment of the invention can be various types of array base paltes, as TN type arraying bread board, FFS array base palte, ADS type array base palte, reversion ADS type array base palte etc., as long as the last conductive shielding layer forming is positioned at data line, grid line and thin film transistor (TFT) region, conductive shielding layer is positioned between the induction source (data line, grid line and thin film transistor (TFT)) and liquid crystal layer that produces electric interfering field simultaneously.
At this, illustrate that some is as follows:
First, the setting of conductive shielding layer should not shield the electric field of normal driving liquid crystal deflecting element, can not shield the electric field that pixel electrode and public electrode produce, therefore, conductive shielding layer can not be positioned at pixel region, can only be arranged in the region at induction source (data line, grid line and thin film transistor (TFT) one or more) place;
Secondly, in the specific embodiment of the invention, and do not require that conductive shielding layer covers all data lines, grid line and thin film transistor (TFT), for example, in the array base palte of reversion ADS pattern, the pixel that is positioned at upper strata need to be connected with the source electrode of TFT by via hole, and now conductive shielding layer just can not cover the region at via hole place.
Finally, the beneficial effect of the embodiment of the present invention is to weaken electric field that induction source the produces interference effect to liquid crystal molecule, is not to eliminate completely.Therefore,, in the embodiment of the present invention, the relation between conductive shielding layer and induction source can be any one in following various relation:
--as shown in Figure 1a, conductive shielding layer 104 covers a part for grid line 101;
--as shown in Figure 1 b, a part for conductive shielding layer 104 cover data lines 102;
--as shown in Fig. 1 c, conductive shielding layer 104 covers a part of TFT103;
Certainly, can also be to cover grid line and data line simultaneously, or cover grid line and TFT simultaneously, or while cover data line and TFT, or cover the variety of ways such as grid line, data line and TFT simultaneously.
Simultaneously, should be noted that, in order to embody the position relationship between conductive shielding layer and data line/grid line/TFT, in Fig. 1 a, 1b, 1c, conductive shielding layer is a part of cover data line/grid line/TFT only, but also can overlap completely, only otherwise exceed the region as shown in Figure 2 at data line/grid line/TFT place.
Mention before, the array base palte of the embodiment of the present invention can be various types of array base paltes, as TN type arraying bread board, FFS array base palte, ADS type array base palte, reversion ADS type array base palte etc., but during for TN type arraying bread board, need to increase MASK technique one time, need to deposit on the basis of existing technology nesa coating one time, and by etching technics, form the figure of conductive shielding layer.
Therefore, consider and the fusion problem of existing technique, in the embodiment of the present invention, array base palte is preferably pixel electrode and public electrode is all positioned on array base palte, but the horizontal electric field type array base palte that pixel electrode and public electrode different layers arrange.
In the horizontal electric field type array base palte of pixel electrode and the setting of public electrode different layers, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode arranges with layer, and with pixel electrode and public electrode in be positioned at top electrode mutually isolate.
In order to reduce technique, in the embodiment of the present invention, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode forms by a composition technique.
That is to say, in the embodiment of the present invention, when pixel electrode is on public electrode, this conductive shielding layer and pixel electrode arrange with layer, and when pixel electrode is under public electrode, this conductive shielding layer and public electrode arrange with layer.
With regard to both of these case, be respectively described below below.
Owing to itself isolating between each pixel electrode, when pixel electrode forms, the nesa coating itself that is positioned at described data line, grid line and thin film transistor (TFT) region needs etching, and the array base palte of the embodiment of the present invention only need to retain the nesa coating that these need etching to adjust originally, and by isolation between the nesa coating retaining and the nesa coating of formation pixel electrode.
As shown in Figure 2, be the last conductive shielding layer 104 forming and the relative position relation schematic diagram between the pixel electrode 105 of slit-shaped.
In array base palte shown in Fig. 2, described array base palte comprises:
The public electrode (not shown) being covered by described the first insulation course;
Be formed on described the first insulation course, and described public electrode forms the pixel electrode 105 of horizontal component of electric field;
Described pixel electrode 105 is positioned at same layer with described conductive shielding layer 104, and described pixel electrode 105 is isolated mutually with described conductive shielding layer 104.
In specific embodiments of the invention, when pixel electrode 105 and described conductive shielding layer 104 are positioned at same layer, can form pixel electrode and conductive shielding layer by a composition technique.
Certainly, in Fig. 2, conductive shielding layer has covered data line as much as possible, grid line and TFT, but also can cover less, as shown in Figure 3.
In above specific embodiment, pixel electrode is formed by second layer ITO, and public electrode is formed by ground floor ITO.
And when pixel electrode is under public electrode, the embodiment of the present invention can realize by the mode of independent formation above-mentioned conductive shielding layer.Under this implementation, in the array base palte of the embodiment of the present invention, comprising:
The pixel electrode being covered by described the first insulation course;
Be formed on described the first insulation course, and described pixel electrode forms the public electrode of horizontal component of electric field;
Cover the second insulation course of described public electrode;
Described conductive shielding layer is formed on described the second insulation course, by described the second insulation course and described public electrode, isolates.
The embodiment of the present invention also provides a kind of method for making of array base palte, comprising:
On glass substrate, form data line, grid line and thin film transistor (TFT);
Form the insulation course that covers described data line, grid line and thin film transistor (TFT);
Formation is positioned at described the first insulation course top, the conductive shielding layer being electrically connected to ground terminal;
Wherein, described conductive shielding layer is positioned at described data line, grid line and thin film transistor (TFT) region.
Above-mentioned method for making, wherein, described array base palte is that pixel electrode and public electrode are all positioned on array base palte, but the horizontal electric field type array base palte that pixel electrode and public electrode different layers arrange.
Above-mentioned method for making, wherein, in described array base palte, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode arranges with layer, and with pixel electrode and public electrode in be positioned at top electrode mutually isolate.
Above-mentioned method for making, wherein, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode forms by a composition technique.
The ADS array base palte that the array base palte of take is below positioned at public electrode top as pixel electrode describes the forming process of the array base palte of the embodiment of the present invention in detail as example.
Referring to Fig. 4 a～Fig. 4 j, to making the overall process of array base palte, be elaborated.
This step can adopt any prior art that can realize by a composition technique to realize.Wherein, composition technique comprises that exposure, development, etching etc. form the technique of figure; A composition technique, refers to the composition technique of using a mask plate Mask.For example, utilize common mask technique to realize, as shown in Fig. 4 a, by common mask plate (not shown), the gate metal film (not shown) in glass substrate 1 is carried out to patterning, with the figure that comprises grid 2 and grid line (not shown) of the patterning that forms.Particularly, comprising: at the upper deposition of substrate (substrate) grid metallic film, utilize common mask board to explosure, development and etching, obtain comprising the figure of grid 2 and grid line.
Common (routine) mask plate refers to the mask plate with He Fei photic zone, photic zone conventionally using, by this first conventional mask plate, the photoresist layer being formed on gate metal film is carried out after exposure imaging, on the gate metal film that needs to retain, be coated with photoresist, and photoresist on the gate metal film that does not need to retain is removed, pass through etch step, unwanted gate metal film is etched away, and remaining gate metal film is the grid of required patterning.
The technique that forms gate metal film can be sputtering technology, other technique that also can be known to those skilled in the art.
Before execution step two, also should first form gate insulation layer 3 completing on the described substrate 1 of described step 1, as shown in Figure 4 b.
Wherein, the technique that forms gate insulator 3 can be chemical vapor deposition method, can be also other technique known to those skilled in the art.
Can adopt masstone (Multi-tone) mask plate to realize, also can adopt duotone mask plate binding plasma cineration technics to realize, specific implementation process comprises:
First, above described gate insulation layer 3, be formed for successively making the semiconductive thin film 6 of described active layer 4 and for making the metallic film 5 of source electrode 7 and drain electrode 8, as shown in Fig. 4 c.
Secondly, described semiconductive thin film 6 and the metallic film 5 outside the predetermined first area that forms described thin film transistor (TFT) of eating away in the same time.
Preferably, can first be coated with photoresist 12, by duotone mask plate, expose, develop, removal is positioned at TFT regions with the photoresist 12 of exterior domain, in TFT regions, form photoetching agent pattern, as shown in Fig. 4 d, described photoetching agent pattern comprises the half shading region A1 corresponding to channel region, corresponding to the predetermined shading region A2 that forms the first area of thin film transistor (TFT) except channel region, and corresponding to the full exposure region A3 outside the first area of predetermined formation thin film transistor (TFT).
Now, etching completes figure afterwards as shown in Fig. 4 e.
Finally, the described metallic film retaining is carried out to etching processing, form described source electrode and drain electrode.
To completing the substrate of above-mentioned technique, carry out plasma ashing processing, remove the photoresist 12 of channel region, form the photoetching agent pattern as shown in Fig. 4 f.
According to the photoetching agent pattern as shown in Fig. 4 f, channel region is proceeded to etching, etch away the source electrode 7 of channel region, the metallic film 5 of drain electrode 8, form the figure as shown in Fig. 4 g, form source electrode 7 and drain electrode 8.
The process that forms public electrode is also similar to the above process, at this, is not described in detail, and the pattern forming after this step is as shown in Fig. 4 h.
Step 4, forms pixel electrode via hole.
First, form passivation layer 9 on the substrate of completing steps three, particularly, the formation technique of passivation layer 9 can be chemical vapor deposition method, or other technique known to those skilled in the art.
Then, can utilize coating photoresist equally, by duotone mask plate, be exposed, developed, removal need to form the photoresist of pixel electrode layer via area, forms pixel electrode via hole (not shown).
Wherein a kind of implementation method can be, specifically comprises: on described passivation layer 9 and in described pixel electrode via hole 10, form ITO indium tin oxide films etc.; Utilize common mask plate to carry out patterning to described ito thin film, to form the figure that comprises conductive shielding layer 104 and pixel electrode film 11, as shown in Fig. 4 j.
Particularly, the formation technique of pixel electrode film 11 can be sputtering technology, or other technique known to those skilled in the art.
By this common mask plate to after being formed on photoresist layer on indium tin oxide films and exposing, develop, on the pixel electrode film that needs to retain, be coated with photoresist, and photoresist on the pixel electrode film that does not need to retain is removed, pass through etch step, unwanted indium tin oxide films is etched away, and remaining pixel electrode film is conductive shielding layer 104 and the pixel electrode 11 of required patterning.
Should be understood that, above is only a kind of technological process of making the array base palte of the embodiment of the present invention, in the array base palte of the embodiment of the present invention, can use existing maturation process to make except conductive shielding layer, at this, does not describe in detail one by one.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (8)
1. an array base palte, comprising:
Glass substrate;
Be formed at data line, grid line and thin film transistor (TFT) on glass substrate;
Cover the first insulation course of described data line, grid line, thin film transistor (TFT);
It is characterized in that, described array base palte also comprises:
Be positioned at described the first insulation course top, the conductive shielding layer being electrically connected to ground terminal;
Wherein, described conductive shielding layer is positioned at described data line, grid line and thin film transistor (TFT) region.
2. array base palte according to claim 1, is characterized in that, described array base palte is that pixel electrode and public electrode are all positioned on array base palte, but the horizontal electric field type array base palte that pixel electrode and public electrode different layers arrange.
3. array base palte according to claim 1, it is characterized in that, in described array base palte, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode arranges with layer, and with pixel electrode and public electrode in be positioned at top electrode mutually isolate.
4. array base palte according to claim 3, is characterized in that, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode forms by a composition technique.
5. a method for making for array base palte, is characterized in that, comprising:
On glass substrate, form data line, grid line and thin film transistor (TFT);
Form the insulation course that covers described data line, grid line and thin film transistor (TFT);
Formation is positioned at described the first insulation course top, the conductive shielding layer being electrically connected to ground terminal;
Wherein, described conductive shielding layer is positioned at described data line, grid line and thin film transistor (TFT) region.
6. method for making according to claim 5, is characterized in that, described array base palte is that pixel electrode and public electrode are all positioned on array base palte, but the horizontal electric field type array base palte that pixel electrode and public electrode different layers arrange.
7. method for making according to claim 6, it is characterized in that, in described array base palte, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode arranges with layer, and with pixel electrode and public electrode in be positioned at top electrode mutually isolate.
8. method for making according to claim 7, is characterized in that, the electrode that is positioned at top in described conductive shielding layer and pixel electrode and public electrode forms by a composition technique.
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