CN103646955A - Charge residue reducing backside imaging sensor structure and manufacturing method thereof - Google Patents
Charge residue reducing backside imaging sensor structure and manufacturing method thereof Download PDFInfo
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- CN103646955A CN103646955A CN201310700061.4A CN201310700061A CN103646955A CN 103646955 A CN103646955 A CN 103646955A CN 201310700061 A CN201310700061 A CN 201310700061A CN 103646955 A CN103646955 A CN 103646955A
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Abstract
The invention discloses a charge residue reducing backside imaging sensor structure and a manufacturing method thereof. The imaging sensor at least comprises a photodiode which is arranged inside a semiconductor substrate, a charge transferring transistor which is connected with the photodiode, a float active area which is connected with the charge transferring transistor and a shallow groove isolation area which is filled between photodiodes which have adjacent pixel; a grid electrode polycrystalline silicon with the preset length inside the charge transferring transistor is arranged inside the shallow groove isolation area. According to the charge residue reducing backside imaging sensor structure and the manufacturing method thereof, the transferring speed of charges inside the photodiode is improved, and accordingly the charge residue problem can be solved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of residual back side illumination image sensor of electric charge and manufacture method thereof of reducing.
Background technology
Imageing sensor has been widely used in digital camera, cell phone, medicine equipment, automobile and other application scenarios.Particularly manufacture CMOS(CMOS (Complementary Metal Oxide Semiconductor)) fast development of image sensor technologies, make people have higher requirement to the output image quality of imageing sensor.
In the prior art, from structure, distinguish, cmos image sensor generally has two kinds: front according to formula structure and back-illuminated type structure, back-illuminated type structure is more suitable for small-sized pixel, for example 1.4um pixel.Compare according to formula structure with front, lenticule and colored filter in back-illuminated type structure are arranged at chip back, there is no metal barrier incident ray, and photodiode can receive more light, and then has improved the optical sensitivity of imageing sensor.
As shown in Figure 1, it is a kind of 4T dot structure schematic diagram of back-illuminated cmos image sensors of prior art, comprise photodiode 101, the photodiode 101 ' of neighbor, charge pass transistor 102, floating active area 103, the photodiode 103 ' of neighbor, the shallow trench isolation region 104 in pixel; Also comprise circuit diagram, reset transistor 105, transistor 106 is followed in source, row selecting transistor 107, and row bit line 108.When practical application, photodiode 101 detects light signal and produces photoelectricity electric charge, and by opening charge pass transistor 102, the transmission of photoelectricity electric charge is caused to floating active area 103, and then source follows the variation that transistor 106 has detected 103 electromotive forces before and after electric charge transmission, the variable quantity of this electromotive force is photosignal value.
As shown in Figure 2, be the tangent plane schematic diagram of tangent position shown in Fig. 1, comprising photodiode 201, charge pass transistor 202, shallow trench isolation region 204, colorized optical filtering section 205, lenticule 206, and the photodiode 201 ' in neighbor.
The defect that above-mentioned prior art exists is: the degree of depth of back-illuminated photodiode 201 is slightly less than silicon substrate thickness conventionally, and because production technology restriction silicon substrate thickness is conventionally thicker, is greater than 3um; In putting the electric charge at A place (as shown in Figure 2) compared with deep-seated away from the raceway groove of charge pass transistor 202, so A place electric charge is difficult for being transferred away, and then produces electric charge residue problem.
Summary of the invention
The object of this invention is to provide a kind of residual back side illumination image sensor of electric charge and manufacture method thereof of reducing, improve the transfer velocity of electric charge in photodiode, and then solve electric charge residue problem.
The object of the invention is to be achieved through the following technical solutions:
Reduce the residual back side illumination image sensor of electric charge, at least comprise the shallow trench isolation region between the photodiode that is placed in the photodiode of semiconductor substrate, the charge pass transistor being connected with described photodiode, the floating active area being connected with described charge pass transistor, is filled in neighbor; Wherein, in described charge pass transistor, the grid polycrystalline silicon of predetermined length is placed in described shallow trench isolation region.
A manufacture method that reduces the residual back side illumination image sensor of electric charge, the method comprises:
In chip front side, apply certain thickness silicon nitride protective layer, and with shallow trench isolation region lap, opening is being set;
Utilize energetic ion etching technique from shallow trench isolation region described in described opening part etching;
Remove described silicon nitride protective layer, and to depositing polysilicon in the groove etching, form charge transfer transistor gate polysilicon.
As seen from the above technical solution provided by the invention, in shifting photodiode during the operation of electric charge, by the grid polycrystalline silicon being placed in described shallow trench isolation region, be conducive to shift the electric charge of photodiode depths, thereby improved the speed of transfer charge, also reduced the residual amount of electric charge in photodiode, and then improved the image quality of back side illumination image sensor simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain other accompanying drawings according to these accompanying drawings.
Plane and the circuit diagram of four transistors (4T) active pixel of the back-illuminated cmos image sensors of the prior art that Fig. 1 provides for background technology of the present invention;
Fig. 2 is photodiode and charge pass transistor and the tangent plane schematic diagram around thereof of the back-illuminated cmos image sensors of prior art;
The back-illuminated cmos image sensors structure tangent plane schematic diagram that Fig. 3 provides for the embodiment of the present invention one;
The schematic diagram of development step during back-illuminated cmos image sensors manufacture method that Fig. 4 provides for the embodiment of the present invention two;
The schematic diagram of the back-illuminated cmos image sensors manufacture method energetic ion etch step that Fig. 5 provides for the embodiment of the present invention two;
The back-illuminated cmos image sensors manufacture method that Fig. 6 provides for the embodiment of the present invention two is removed the schematic diagram of silicon nitride protective layer step;
The schematic diagram of the back-illuminated cmos image sensors manufacture method depositing polysilicon step that Fig. 7 provides for the embodiment of the present invention two;
The back-illuminated cmos image sensors manufacture method that Fig. 8 provides for the embodiment of the present invention two forms the schematic diagram of transistor gate polysilicon step.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on embodiments of the invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to protection scope of the present invention.
Embodiment mono-
The embodiment of the present invention provides a kind of residual back side illumination image sensor of electric charge that reduces, at least comprise the shallow trench isolation region between the photodiode that is placed in the photodiode of semiconductor substrate, the charge pass transistor being connected with described photodiode, the floating active area being connected with described charge pass transistor, is filled in neighbor, wherein, in described charge pass transistor, the grid polycrystalline silicon of predetermined length is placed in described shallow trench isolation region.
Further, in described shallow trench isolation region, the degree of depth of the grid polycrystalline silicon of predetermined length is less than the degree of depth of described shallow trench isolation region.
In addition, the degree of depth of described shallow trench isolation region is generally 0.4um～0.5um.
For convenience of explanation, below in conjunction with accompanying drawing 3, be described in detail.The back-illuminated cmos image sensors structure tangent plane schematic diagram that Fig. 3 provides for the present embodiment, its tangent plane is the tangent plane of tangent position shown in Fig. 1.As shown in Figure 3,301 is photodiode, and for sensitization and generate photoelectricity electric charge, its upper and lower scope approaches respectively silicon substrate surface; 302 is charge pass transistor, for shifting electric charge in photodiode 301 to floating active area; 301 ' is the photodiode of neighbor; 304 is 301 and 301 ' two shallow trench isolation regions between photodiode, and packing material is silicon phosphorus glass, and the degree of depth is 0.4um～0.5um; 305 is colorized optical filtering section, 306 microlens region; B point characterizes 301 compared with the electric charge of depths, and B point is greater than 2.8um conventionally apart from chip silicon substrate front surface.Wherein, charge pass transistor 302 is arranged at chip front side with shallow trench isolation region 304; 305He microlens region, colorized optical filtering section 306 is arranged at chip back.
The grid polycrystalline silicon extension of charge pass transistor shown in Fig. 3 302 causes in shallow trench isolation region, has shortened the distance of B district electric charge and charge pass transistor 302 grids.When opening the operation of charge pass transistor 302 transfer photodiode 301 interior electric charges, B district electric charge is easy to be adsorbed in charge pass transistor 302 raceway grooves, thereby shortened the interior electric charge of photodiode 301, shift the time that causes floating active area, improved the operating rate of imageing sensor; And charge pass transistor structure of the present invention has reduced even to eliminate the residue problem of 301 interior electric charges, further promoted the picture quality of imageing sensor.
Embodiment bis-
The embodiment of the present invention provides a kind of manufacture method that reduces the residual back side illumination image sensor of electric charge, comprises the step shown in accompanying drawing 4-accompanying drawing 8, concrete:
1) as shown in Figure 4, in chip front side, apply certain thickness silicon nitride protective layer, and with shallow trench isolation region lap, opening is being set.This step belongs to the development part in back side illumination image sensor manufacture method.Wherein, 401 is silicon nitride protective layer, and the thickness of silicon nitride is generally 150nm～200nm; 304 is shallow trench isolation region, and its degree of depth is 0.4um～0.5um, and its filler is megohmite insulant silicon phosphorus glass.
2) as shown in Figure 5, utilize energetic ion etching technique etching shallow trench isolation region, energetic ion generally adopts inert element, for example helium; The degree of depth that shallow trench isolation region is etched approaches but is less than the degree of depth of shallow trench isolation region filler silicon phosphorus glass.
3) as shown in Figure 6, remove silicon nitride protective layer.After removing silicon nitride, at exposed silicon face, produce one deck grid oxide layer, the manufacture craft of this grid oxide layer is identical with traditional logic technique, at this, does not repeat.
4) as shown in Figure 7, to the groove depositing polysilicon etching.Wherein 701 is transistor gate and line polysilicon used thereof, and the thickness of this polysilicon is identical with traditional handicraft.This polysilicon needs chemical mechanical milling tech operation before formation, and object is that polysilicon is polished, even thickness; And polysilicon has filled up the part that shallow trench isolation region 304 is etched.
5) as shown in Figure 8, form transistor gate polysilicon 302, this transistor gate polysilicon is charge transfer transistor.Form in this step transistor gate polysilicon process identical with traditional handicraft operation.
The above; be only the present invention's embodiment preferably, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (9)
1. one kind is reduced the residual back side illumination image sensor of electric charge, at least comprise and be placed in the photodiode of semiconductor substrate, the charge pass transistor being connected with described photodiode, the floating active area being connected with described charge pass transistor, be filled in the shallow trench isolation region between the photodiode between neighbor, it is characterized in that, in described charge pass transistor, the grid polycrystalline silicon of predetermined length is placed in described shallow trench isolation region.
2. imageing sensor according to claim 1, is characterized in that, in described shallow trench isolation region, the degree of depth of the grid polycrystalline silicon of predetermined length is less than the degree of depth of described shallow trench isolation region.
3. imageing sensor according to claim 1 and 2, is characterized in that, the degree of depth of described shallow trench isolation region is 0.4um～0.5um.
4. a manufacture method that reduces the residual back side illumination image sensor of electric charge, is characterized in that, the method comprises:
In chip front side, apply certain thickness silicon nitride protective layer, and with shallow trench isolation region lap, opening is being set;
Utilize energetic ion etching technique from shallow trench isolation region described in described opening part etching;
Remove described silicon nitride protective layer, and to depositing polysilicon in the groove etching, form charge transfer transistor gate polysilicon.
5. manufacture method according to claim 4, is characterized in that, described in the degree of depth of the groove that etches be less than the degree of depth of described shallow trench isolation region.
6. according to the manufacture method described in claim 4 or 5, it is characterized in that, the degree of depth of described shallow trench isolation region is 0.4um～0.5um.
7. manufacture method according to claim 4, is characterized in that, the thickness of described silicon nitride protective layer is 150nm～200nm.
8. manufacture method according to claim 4, is characterized in that, described energetic ion comprises: inert element; Described inert element comprises: helium element.
9. manufacture method according to claim 4, is characterized in that, in the described groove to etching, after depositing polysilicon, utilizes chemical mechanical milling tech to process.
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| CN104134677B (en) * | 2014-08-15 | 2017-02-15 | 北京思比科微电子技术股份有限公司 | Imaging sensor preventing image dispersion and manufacturing method of imaging sensor |
| CN108281436A (en) * | 2018-01-15 | 2018-07-13 | 德淮半导体有限公司 | Cmos image sensor and forming method thereof |
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Application publication date: 20140319 |