CN103646867A - A method for improving a wafer peeling defect - Google Patents
A method for improving a wafer peeling defect Download PDFInfo
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- CN103646867A CN103646867A CN201310630281.4A CN201310630281A CN103646867A CN 103646867 A CN103646867 A CN 103646867A CN 201310630281 A CN201310630281 A CN 201310630281A CN 103646867 A CN103646867 A CN 103646867A
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- peels
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- 230000007547 defect Effects 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 105
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000000227 grinding Methods 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 31
- 238000005406 washing Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for improving a wafer peeling defect. After an active region etching step of online wafer technology, silicon substrate residing on the edge of the substrate of a wafer is removed by using chemical mechanical grinding. Therefore, a peeling defect fountainhead is prevented from generating on the exposed surface of the residual silicon substrate in following technology. The method has advantages of fundamentally eliminating a critical factor forming the peeling defect fountainhead, preventing the formation of the peeling defect fountainhead, further improving the wafer defect, and increasing wafer yield.
Description
Technical field
The present invention relates to integrated circuit fabrication process field, relate in particular to a kind of method that wafer peels off defect of improving.
Background technology
In semiconductor integrated circuit is manufactured; each technical process can be introduced because of a variety of causes particulate or defect; along with very lagre scale integrated circuit (VLSIC) high integration and high performance demand are increased gradually; semiconductor technology is towards less characteristic size development, and these particulates or defect are on the impact of integrated circuit quality also increasingly significant.
Fig. 1 a and 1b are that a kind is peeled off the defect source image under light microscope and electron microscope respectively in line products.The reason of its formation is as shown in Fig. 2 a-2f, and concrete steps are as follows:
Step S01: as shown in Fig. 2 a and 2b, in wafer substrate 100, be coated with one deck bottom anti-reflection layer 200, this bottom anti-reflection layer 200 is covered on wafer substrate 100 completely, then chooses certain distance and carry out side washing to remove part bottom anti-reflection layer 200;
Step S02: as Fig. 2 c, 2d and 2e, deposit one deck photoresist 300 in above-mentioned bottom anti-reflection layer 200, develops and this wafer substrate 100 of etching to wafer substrate 100, wherein, on the crystal edge of this wafer substrate 100, can remain unnecessary silicon substrate 100 ';
Step S03: as shown in Fig. 2 f, when deposit one layer insulating 400 in wafer substrate 100, can form on the exposed surface of residual silicon substrate 100 ' on the crystal edge of this wafer substrate 100 and peel off defect source 500 as shown in Fig. 1 a and 1b.
In prior art, for avoiding the defect source of peeling off on the crystal edge of wafer substrate to exert an influence to wafer yield, often by cleaning the mode of crystal edge, the possible source of peeling off is removed, in case class defect is fallen into inside wafer and affected yield here.But the drawback of these class methods is to peel off defect source and is generally just found at metal deposition layer, if can causing, less cleaning position or overclean more peel off defect, even cause serious metallic pollution.
Therefore, how fundamentally remove and form the key factor of peeling off defect source, to avoid peeling off the formation in defect source, and then improve wafer and peel off defect, the yield that promotes wafer just seems very important.
Summary of the invention
Object of the present invention is, for the problems referred to above, a kind of method that wafer peels off defect of improving has been proposed, after the method proceeds to the etch step of active area by online wafer by technique, adopt cmp to remove the residual silicon substrate on wafer substrate crystal edge, avoid on the exposed surface of residual silicon substrate, generating and peeling off defect source in subsequent technique, fundamentally except forming the key factor of peeling off defect source, avoid peeling off the formation in defect source, and then improved wafer and peel off defect, promoted the yield of wafer.
For achieving the above object, the present invention is a kind of improves the method that wafer peels off defect, comprising:
One wafer substrate is provided;
In described wafer substrate, be sequentially coated with bottom anti-reflection layer and photoresist;
To described wafer substrate develop and etching described in wafer substrate, wherein, on the crystal edge of described wafer substrate, remain unnecessary silicon substrate;
Grind the crystal edge of described wafer substrate to remove described residual silicon substrate.
Preferably, after the described bottom anti-reflection layer of coating and before the described photoresist of coating, also comprise the side washing technique to described wafer substrate.
Preferably, described side washing technique is to remove the part bottom anti-reflection layer on the crystal edge that is positioned at described wafer substrate with certain side washing distance.
Preferably, described wafer substrate has the residual of part bottom anti-reflection layer after developing.
Preferably, described residual bottom anti-reflection layer can cause the residual of unnecessary silicon substrate in the process of wafer substrate described in subsequent etching.
Preferably, the crystal edge of described grinding crystal wafer substrate is that the residual silicon substrate on the crystal edge of described wafer substrate is ground.
Preferably, described wafer substrate is fixed and grinds by being adsorbed on tumbler
Preferably, described in, be ground to cmp.
Preferably, remove described residual silicon substrate, on the exposed surface of described residual silicon substrate, form and peel off defect source avoiding in subsequent technique, improve wafer and peel off defect.
From technique scheme, can find out, the present invention is a kind of improves the method that wafer peels off defect, after technique being proceeded to the etch step of active area by online wafer, adopt cmp to remove the residual silicon substrate on wafer substrate crystal edge, avoid on the exposed surface of residual silicon substrate, generating and peeling off defect source in subsequent technique, fundamentally except forming the key factor of peeling off defect source, avoid peeling off the formation in defect source, and then improved wafer and peel off defect, promoted the yield of wafer.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention is described in detail, wherein:
Fig. 1 a and 1b are that a kind is peeled off the defect source image schematic diagram under light microscope and electron microscope respectively in line products;
Fig. 2 a-2f is that a kind is peeled off the generation schematic diagram in defect source in line products;
To be that the present invention is a kind of improve the schematic diagram of a specific embodiment that wafer peels off the method for defect to Fig. 3 a-3f;
To be that the present invention is a kind of improve wafer in the process of lapping of a specific embodiment of method that wafer peels off defect and arrange schematic diagram Fig. 4;
To be that the present invention is a kind of improve the flow chart of a specific embodiment that wafer peels off the method for defect to Fig. 5.
Embodiment
Some exemplary embodiments that embody feature & benefits of the present invention will describe in detail in the explanation of back segment.Be understood that the present invention can have various variations in different examples, it neither departs from the scope of the present invention, and explanation wherein and be shown in the use that ought explain in essence, but not in order to limit the present invention.
Above-mentioned and other technical characterictic and beneficial effect, improve to the present invention the preferred embodiment that wafer peels off the method for defect in connection with accompanying drawing 3a-3f, Fig. 4 and Fig. 5 and be elaborated.
To be that the present invention is a kind of improve the flow chart of a specific embodiment that wafer peels off the method for defect to Fig. 5.By illustrating, the present invention is a kind of improves the method that wafer peels off defect below, and it comprises the steps:
Step S01 a: wafer substrate is provided.
Particularly, this wafer substrate can be the semi-conducting material wafer substrate of original or extension, as monocrystalline silicon/germanium silicon/germanium or other known semi-conducting material wafer substrate, with monocrystalline silicon/germanium silicon/strained silicon/Germanium of insulating buried layer/or other known semi-conducting material wafer substrate etc., and described semi-conducting material wafer substrate surface original or extension can also comprise well region or the active area of semiconductor doping.In the present embodiment, this wafer substrate 101 is silicon substrate.
Step S02: be sequentially coated with bottom anti-reflection layer and photoresist in above-mentioned wafer substrate.
Refer to Fig. 3 a, 3b and 3c, particularly, in above-mentioned wafer substrate 101, by plasma reinforced chemical vapour deposition, be coated with one deck bottom anti-reflection layer 201, then after being coated with bottom anti-reflection layer 201, according to certain side washing distance, the crystal edge of this wafer substrate 101 is carried out to side washing technique, to remove the part bottom anti-reflection layer 201 being positioned on described wafer substrate 101 outward flanges.In above-mentioned bottom anti-reflection layer 201, be coated with one deck photoresist 301 afterwards.
Step S03: above-mentioned wafer substrate is developed and this wafer substrate of etching, wherein, remain unnecessary silicon substrate on the crystal edge of this wafer substrate.
Refer to Fig. 3 d and 3e, specifically, above-mentioned wafer substrate 101 is developed to remove the photoresist 301 being positioned in this wafer substrate 101, wafer substrate 101 is come out.Wherein, after this wafer substrate 101 is developed, some bottom anti-reflection layer 201 ' remains on the crystal edge of this wafer substrate 101, and it causes the residual of unnecessary silicon substrate 101 ' in the process of the above-mentioned wafer substrate 101 of subsequent etching.
Then, the above-mentioned wafer substrate 101 of etching, also comprise and remove above-mentioned residual part bottom anti-reflection layer 201 ', wherein, in the technical process of the above-mentioned wafer substrate 101 of etching, because the residual of part bottom anti-reflection layer 201 ' makes after etching is complete, make to remain unnecessary silicon substrate 101 ' on the crystal edge of this wafer substrate 101.
Step S04: grind the crystal edge of this wafer substrate to remove above-mentioned residual silicon substrate.
Refer to Fig. 3 f and Fig. 4, specifically, the above-mentioned crystal edge with the wafer substrate 101 of residual silicon substrate 101 ' is ground, to remove this residual silicon substrate 101 '.In the present embodiment, the crystal edge of above-mentioned grinding crystal wafer substrate 101 is by regulating grinding head to grind the specified distance of wafer substrate 101, wherein said specified distance is the position of residual silicon substrate 101 ' on the crystal edge of this wafer substrate 101, by detecting the position of residual silicon substrate 101 ' on the crystal edge of above-mentioned wafer substrate 101, only the residual silicon substrate 101 ' in the specific range region of above-mentioned wafer substrate 101 crystal edges is ground, and can grind other wafer substrate 101 regions, also can not grind, wherein, the above-mentioned cmp that is ground to.When grinding, above-mentioned wafer substrate is carried on the back to be adsorbed on tumbler by crystalline substance and is fixed and grinds, and the arrangement of wafer substrate on tumbler can arrange as digital 1-9 region, as shown in Figure 4.
Afterwards, by being increased to one grinding technics, above-mentioned wafer crystal edge 101 removing residual silicon substrate 101 ', avoided on the exposed surface of this residual silicon substrate 101 ', forming and peeling off defect source in subsequent technique, and then prevent from peeling off defect source and fall into inside wafer, improve wafer and peel off defect, improve wafer yield.
In sum, the present invention is a kind of improves the method that wafer peels off defect, after technique being proceeded to the etch step of active area by online wafer, adopt cmp to remove the residual silicon substrate on the crystal edge of wafer substrate, avoid on the exposed surface of residual silicon substrate, generating and peeling off defect source in subsequent technique, fundamentally, except forming the key factor of peeling off defect source, avoid peeling off the formation in defect source, and then improved wafer defect, promoted the yield of wafer.
Above-described is only the preferred embodiments of the present invention; described embodiment is not in order to limit scope of patent protection of the present invention; therefore the equivalent variations that every utilization specification of the present invention and accompanying drawing content are done, in like manner all should be included in protection scope of the present invention.
Claims (9)
1. improve the method that wafer peels off defect, it is characterized in that, comprising:
One wafer substrate is provided;
In described wafer substrate, be sequentially coated with bottom anti-reflection layer and photoresist;
To described wafer substrate develop and etching described in wafer substrate, wherein, on the crystal edge of described wafer substrate, remain unnecessary silicon substrate;
Grind the crystal edge of described wafer substrate to remove described residual silicon substrate.
2. a kind of method that wafer peels off defect of improving according to claim 1, is characterized in that, after the described bottom anti-reflection layer of coating and before the described photoresist of coating, also comprises the side washing technique to described wafer substrate.
3. a kind of method that wafer peels off defect of improving according to claim 2, is characterized in that, described side washing technique is to remove the part bottom anti-reflection layer on the crystal edge that is positioned at described wafer substrate with certain side washing distance.
4. a kind of method that wafer peels off defect of improving according to claim 1, is characterized in that, described wafer substrate has the residual of part bottom anti-reflection layer after developing.
5. a kind of method that wafer peels off defect of improving according to claim 4, is characterized in that, described residual bottom anti-reflection layer can cause the residual of unnecessary silicon substrate in the process of wafer substrate described in subsequent etching.
6. a kind of method that wafer peels off defect of improving according to claim 1, is characterized in that, the crystal edge of described grinding crystal wafer substrate is that the residual silicon substrate on the crystal edge of described wafer substrate is ground.
7. a kind of method that wafer peels off defect of improving according to claim 1, is characterized in that, described wafer substrate is fixed and grinds by being adsorbed on tumbler.
8. a kind of method that wafer peels off defect of improving according to claim 7, is characterized in that, described in be ground to cmp.
9. a kind of method that wafer peels off defect of improving according to claim 1, is characterized in that, removes described residual silicon substrate, forms and peels off defect source avoiding in subsequent technique on the exposed surface of described residual silicon substrate, improves wafer and peels off defect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310630281.4A CN103646867B (en) | 2013-11-29 | 2013-11-29 | Improve the method for wafer scaling defects |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310630281.4A CN103646867B (en) | 2013-11-29 | 2013-11-29 | Improve the method for wafer scaling defects |
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| Publication Number | Publication Date |
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| CN103646867A true CN103646867A (en) | 2014-03-19 |
| CN103646867B CN103646867B (en) | 2016-04-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047535A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Method for preventing peeling defect of wafer edges |
| CN105093821A (en) * | 2014-05-13 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method and processing chamber |
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| CN101625968A (en) * | 2009-08-04 | 2010-01-13 | 上海集成电路研发中心有限公司 | Method for improving wet etching performance |
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2013
- 2013-11-29 CN CN201310630281.4A patent/CN103646867B/en active Active
Patent Citations (8)
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| TW449832B (en) * | 1999-01-04 | 2001-08-11 | United Microelectronics Corp | Removing method of polysilicon defect |
| CN1539560A (en) * | 2002-10-03 | 2004-10-27 | 尔必达存储器株式会社 | Machine and method for coating |
| CN1521814A (en) * | 2002-12-06 | 2004-08-18 | 硅绝缘体技术有限公司 | Method for recycling a substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105093821A (en) * | 2014-05-13 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method and processing chamber |
| CN105047535A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Method for preventing peeling defect of wafer edges |
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| CN103646867B (en) | 2016-04-06 |
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