CN103645980A - Monitoring method for embedded system timer - Google Patents
Monitoring method for embedded system timer Download PDFInfo
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- CN103645980A CN103645980A CN201310710110.2A CN201310710110A CN103645980A CN 103645980 A CN103645980 A CN 103645980A CN 201310710110 A CN201310710110 A CN 201310710110A CN 103645980 A CN103645980 A CN 103645980A
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Abstract
The invention discloses a monitoring method for an embedded system timer. The monitoring method is characterized by comprising the steps: setting the minimum time granularity in a timer of a main kernel to be A, setting the minimum time granularity of a timer of a coprocessor or an auxiliary kernel to be B, reading the times N that the timer of the coprocessor or the auxiliary kernel implements B when the timer of the main kernel implements A for M times in reference to the minimum time granularity A of the timer of the main kernel, and judging values of MA and N*B; comparing a value obtained by summing an S-times recorded value of the main kernel with a value of the coprocessor or the auxiliary kernel to monitor a working state of the embedded system timer. By the method disclosed by the invention, the monitoring method disclosed by the invention has the advantages that 1, the conventional embedded chip replaces a watchdog circuit to realize a regular protection function; 2, the timing function is detected in real time, so that the timing function is stable and reliable.
Description
Technical field
The present invention relates to the application of embedded system, particularly a kind of method for supervising of embedded system timer.
Background technology
In current embedded system, for encryption, generally only considering that protection task itself is not overtime, there is not endless loop in the CPU of embedded system, and generally the mode by watchdog circuit realizes.
Timing dog-feeding when described watchdog circuit designs in embedded system each tasks carrying, does not obtain if watchdog circuit surpasses the time of one section of setting the feeding-dog signal of estimating, fault has occurred in illustrative system operation, restarts system.These setting and each timed tasks of feeding the dog time all need timer to trigger in the predetermined moment.But in this process, whether timer itself is working properly and provide accurately regularly and do not monitored.Along with the development of chip technology and more and more higher to electronics, requirement electric and programming device functional safety, in embedded chip field, there is the master chip with enhancement mode timing coprocessor or multi-core, this chip can have a plurality of independently timer operations, drive independently mission thread, for the functional safety of timer itself, monitor possibility is provided.How to utilize existing embedded chip to replace existing watchdog circuit to realize encryption functional purpose and remain a technical barrier.
For above-mentioned problem, a kind of novel method for supervising is provided, making existing embedded chip replace existing watchdog circuit to realize encryption function and detect is in real time the problem that prior art need to solve.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method for supervising of embedded system timer, to reach the object of utilizing existing embedded chip to replace watchdog circuit to realize encryption function and detect in real time.
For achieving the above object, technical scheme of the present invention is, a kind of method for supervising of embedded system timer, it is characterized in that: described method for supervising is at the set timer minimum time granularity A of main core, timer minimum time granularity in coprocessor or inferior core is B, and the main core timer minimum time granularity A of take is benchmark, when main core timer completes the cycle of M A, the timer that reads coprocessor or inferior core completes the times N of B, and the value of M * A and N * B is judged; And after S record value of main core is added, compare with the value of coprocessor or inferior core, the duty of embedded system timer is monitored.
First described method for supervising judges whether the absolute value of M * A and N * B difference is greater than maximum allowable offset value D, if be greater than maximum allowable offset value D, reports to the police, otherwise judgement timer is working properly.
Described method for supervising is compared with the value of coprocessor or inferior core after S record value of main core is added, if be greater than the average detected maximum allowable offset value S_D of setting, think and timer generation problem by the set of relevant error zone bit, otherwise judge that timer is working properly.
Described embedded system timer adopts the master chip with enhancement mode timing coprocessor or multi-core.
The model of described master chip is the SPC563M chip of ST Microelectronics.
A method for supervising for embedded system timer, owing to adopting above-mentioned method, the invention has the advantages that: 1, utilize existing embedded chip to replace watchdog circuit to realize encryption function; 2, timing function is detected in real time, guarantee that timing function is reliable and stable.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation;
Fig. 1 is the process flow diagram of the method for supervising of a kind of embedded system timer of the present invention;
Embodiment
The invention provides and a kind ofly can have the timer method for supervising of realizing on coprocessor or multi-core embedded system master chip, its coprocessor of the feature of this kind of master chip or multi-core possess can move independently timer.Concrete steps are as follows:
(1) the timer minimum time granularity that main core is set is A;
(2) the timer minimum time granularity that coprocessor or inferior core is set is B;
(3) take main core timer minimum time granularity A is benchmark, and when main core timer completes the cycle of M A, the timer that reads coprocessor or inferior core completes the times N of B;
(4) value that compares M * A and N * B is as a single timer monitor and detection, if the absolute value of the difference of M * A-N * B is greater than the single of setting and detects maximum allowable offset value D, think timer generation problem, by the set of relevant error zone bit, for system, carry out next step fault handling;
(5) M * A and the N * B that each sense cycle are obtained record, and continuous recording S time, as an average detected cycle, and adds up the value of this S M * A and N * B, that is:
S_M×A=M×A(1)+M×A(2)+…M×A(S-1)+M×A(S)；
S_N×B=N×B(1)+N×B(2)+…N×B(S-1)+N×B(S)；
(6) relatively the value of S_M * A and S_N * B as average timer monitor and detection once, if the absolute value of the difference of S_M * A-S_N * B is greater than the average detected maximum allowable offset value S_D of setting, think timer generation problem, by the set of relevant error zone bit, for system, carry out next step fault handling
(6) reset each M * A, N * B and S_M * A, S_N * B is initial value, enters next timer monitoring circulation.
Compare with currently available technology, the present invention can to the work of timer itself whether normal, regularly whether accurately monitor.One of innovative point of the present invention is to monitor timer itself.Two of innovative point is to the monitoring of single timer and average sense cycle monitoring, the monitoring of single timer can be found the timer mistake that single deviation is larger as early as possible, although average detected cycle monitoring can find that each single detection error is within allowed band, but deviation has same tropism, the off-limits situation of deviation after accumulation after a while.
Specifically as shown in Figure 1, it is example that chip of the present invention be take the SPC563M chip that ST Microelectronics provides, this chip, except main core, also has regularly coprocessor unit of an enhancement mode, and this coprocessor can be independent of main processor unit and carry out timed task processing.
The timer minimum time granularity A that the present invention arranges main core is 2ms; The timer minimum time granularity B that coprocessor is set is 3ms; It is the minimum time granularity 2ms of 30 times during the cycle that the timer that main core is set completes M, reads the times N of the minimum time granularity period 3ms that the timer of coprocessor completes.It is 3ms that single detection maximum allowable offset value D is set;
If the N reading be 19,20 or the absolute difference of 21, M * A and N * B be respectively 3,0,3, being not more than single, to detect maximum allowable offset value D be 3ms, belong to normal, if the N value reading is other values outside 19,20,21, absolute difference will, over D, belong to fault.
The present invention arrange average detected in the cycle continuous recording number of times S be 3 times, average detected maximum allowable offset value S_D is 6ms;
If continuous 3 singles detect the N reading and are respectively 19,21,19,
S_M×A=M×A(1)+M×A(2)+…M×A(S-1)+M×A(S)=30×2+30×2+30×2=180
S_N×B=N×B(1)+N×B(2)+…N×B(S-1)+N×B(S)=19×3+21×3+19×3=177
The absolute value of the difference of S_M * A-S_N * B is 3, is less than the value 6ms of S_D, belongs to normal.
If continuous 3 singles detect the N reading and are respectively 19,19,19,
S_N×B=N×B(1)+N×B(2)+…N×B(S-1)+N×B(S)=19×3+19×3+19×3=171
The absolute value of the difference of S_M * A-S_N * B is 9, is greater than the value 6ms of S_D, belongs to fault.
By reference to the accompanying drawings the present invention is exemplarily described above; obviously specific implementation of the present invention is not subject to the restrictions described above; as long as the various improvement that adopted technical solution of the present invention to carry out, or directly apply to other occasion without improvement, all within protection scope of the present invention.
Claims (5)
1. the method for supervising of an embedded system timer, it is characterized in that: described method for supervising is at the set timer minimum time granularity A of main core, timer minimum time granularity in coprocessor or inferior core is B, the main core timer minimum time granularity A of take is benchmark, when main core timer completes the cycle of M A, the timer that reads coprocessor or inferior core completes the times N of B, and the value of M * A and N * B is judged; And after S record value of main core is added, compare with the value of coprocessor or inferior core, the duty of embedded system timer is monitored.
2. the method for supervising of a kind of embedded system timer according to claim 1, it is characterized in that: first described method for supervising judges whether the absolute value of M * A and N * B difference is greater than maximum allowable offset value D, if be greater than maximum allowable offset value D, report to the police, otherwise judgement timer is working properly.
3. the method for supervising of a kind of embedded system timer according to claim 1, it is characterized in that: described method for supervising is compared with the value of coprocessor or inferior core after S record value of main core is added, if be greater than the average detected maximum allowable offset value S_D of setting, think timer generation problem, by the set of relevant error zone bit, otherwise judgement timer is working properly.
4. the method for supervising of a kind of embedded system timer according to claim 1, is characterized in that: described embedded system timer adopts the master chip with enhancement mode timing coprocessor or multi-core.
5. the method for supervising of a kind of embedded system timer according to claim 1, is characterized in that: the SPC563M chip that the model of described master chip is ST Microelectronics.
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| CN201310710110.2A CN103645980A (en) | 2013-12-19 | 2013-12-19 | Monitoring method for embedded system timer |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04182842A (en) * | 1990-11-19 | 1992-06-30 | Fujitsu Ltd | Timer monitor system |
| CN1952904A (en) * | 2006-11-23 | 2007-04-25 | 北京中星微电子有限公司 | A testing method and system for timer in embedded system |
| CN101216798A (en) * | 2008-01-14 | 2008-07-09 | 浙江大学 | Periodic task reliability control method based on watchdog and timer |
| CN101464822A (en) * | 2007-12-21 | 2009-06-24 | 中兴通讯股份有限公司 | Test method for CPU timer accuracy |
-
2013
- 2013-12-19 CN CN201310710110.2A patent/CN103645980A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04182842A (en) * | 1990-11-19 | 1992-06-30 | Fujitsu Ltd | Timer monitor system |
| CN1952904A (en) * | 2006-11-23 | 2007-04-25 | 北京中星微电子有限公司 | A testing method and system for timer in embedded system |
| CN101464822A (en) * | 2007-12-21 | 2009-06-24 | 中兴通讯股份有限公司 | Test method for CPU timer accuracy |
| CN101216798A (en) * | 2008-01-14 | 2008-07-09 | 浙江大学 | Periodic task reliability control method based on watchdog and timer |
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Application publication date: 20140319 |
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