CN103633843B - A kind of digital power and output voltage control method thereof - Google Patents
A kind of digital power and output voltage control method thereof Download PDFInfo
- Publication number
- CN103633843B CN103633843B CN201310629372.6A CN201310629372A CN103633843B CN 103633843 B CN103633843 B CN 103633843B CN 201310629372 A CN201310629372 A CN 201310629372A CN 103633843 B CN103633843 B CN 103633843B
- Authority
- CN
- China
- Prior art keywords
- information
- current
- school
- digital power
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides a kind of digital power and output voltage control method thereof, state detection circuit is added in existing digital power, the process corner of state detection circuit detection digital power and the temperature information of this digital power place environment, generate school according to process corner and temperature information and adjust information, high-ranking officers adjust information to be compiled as numeral school and adjust information, the dutycycle of the output pulse signal of information adjustment pulse width modulator is adjusted according to numeral school, the power tube turn-off time of driver is adjusted according to the pulse signal after adjusting, ensure that digital power output voltage control is in the range of nominal tension, avoid and be powered circuit due to digital power output voltage inaccuracy, thus its function is affected, produce unpredictable consequence.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly, it relates to a kind of digital power and defeated
Go out voltage control method.
Background technology
Along with the progress of semiconductor process technique, the power consumption that it is desirable to semiconductor chip is more and more less, and
Processing speed is increasingly faster, and this just requires that the supply voltage of chip is more and more less, thus to voltage controller
Accuracy propose the highest requirement.In order to tackle the required precision improved constantly, chip designs
Person proposes the concept of digital power control circuit, compares traditional analog voltage controller, digital power
Control circuit has the advantage that 1, is easier to realize complexity, be accurately controlled algorithm；2, have more
Good motility and programmability；3, there is higher capacity of resisting disturbance.
But in integrated circuit production process, owing to being affected by process deviation etc., same circuit sets
Also can there is little bit different at aspects such as performances in meter, such as, near the performance indications of the chip of inside wafer
It is distinguishing with the performance indications near crystal round fringes.For digital power, this deviation and
Its place variation of ambient temperature can affect the accuracy for output voltage, if deviation and variations in temperature mistake
Greatly, also can have influence on the function being powered circuit further, produce unpredictable consequence.
Summary of the invention
In view of this, the present invention provides a kind of digital power and output voltage control method thereof, at numeral electricity
Source adds state detection circuit, makes supply voltage output more accurate, stable.
For achieving the above object, the present invention provides following technical scheme:
A kind of digital power, including induction apparatus, analog-digital converter and digital power main circuit, this numeral
Power supply also includes: state detection circuit, pulse width modulator, driver, wherein:
Described state detection circuit is for detecting process corner and the temperature of its place environment of described digital power
Degree information, and generate school tune information according to described process corner and described temperature information, information is adjusted in described school
It is compiled as numeral school and adjusts information；
Described pulse width modulator is for the dutycycle adjusting information to adjust pulse signal according to described numeral school；
Described driver for adjusting the merit of described driver according to the pulse signal after described adjustment dutycycle
The rate pipe turn-off time, it is ensured that described digital power main circuit output voltage is in the range of nominal tension.
Preferably, described state detection circuit includes: the first current source, the second current source, a PMOS
Pipe, the first NMOS tube, voltage-current converter, current comparator, bank of latches, school adjust information to translate
Code device, wherein:
The current value of described first current source and described second current source is equal；
Described first current source is connected with the source electrode of described first PMOS, described first PMOS
Grid is connected earth terminal with drain electrode, and the voltage of described first PMOS source electrode is as the first voltage；
The input of described voltage-current converter is connected with the source electrode of described first PMOS, and being used for will
Described first voltage is converted to the first electric current；
Described second current source is connected with the drain electrode of described first NMOS tube, described first NMOS tube
Source electrode connects earth terminal, and described first NMOS tube drain and gate is connected, described first NMOS tube
Drain current is as the second electric current；
The first input end of described current comparator is connected with the outfan of described voltage-current converter, institute
The grid of the second input and described first NMOS tube of stating current comparator is connected, for by described the
One electric current carries out scaled mirror, obtains first image current of n and described first current in proportion, with
And described second electric current is carried out scaled mirror, a n obtained and the second of described second current in proportion
Image current, and by individual with n for n described first image current described second image current corresponding the
Two image currents compare, and obtain n output of n comparative result output extremely described current comparator
End obtains school and adjusts information；
N input of described bank of latches is corresponding with n outfan of described current comparator to be connected,
For described school tune information is latched；
Described school adjusts information decoder input to be connected with the outfan of described bank of latches, for by described
School is adjusted information to be compiled as numeral school and is adjusted information.
Preferably, described numeral school adjusts information to be parallel binary signal.
Preferably, described first PMOS and described first NMOS tube have identical breadth length ratio.
Preferably, described voltage-current converter includes: the second PMOS, the second NMOS tube,
Wherein:
The grid of described second NMOS tube is the input of described voltage-current converter, described second
The source electrode of NMOS tube connects earth terminal, the drain electrode of described second NMOS tube and described second PMOS
Grid be connected；
The source electrode of described second PMOS connects power supply, the grid of described second PMOS and described the
The drain electrode of two PMOS is connected, and the grid of described second PMOS is described voltage-current converter
Outfan.
Preferably, described current comparator includes: n PMOS, n NMOS tube, n is for being more than
The integer of 2, wherein:
The source electrode of described n PMOS is all connected with power supply, the grid phase continuous cropping of described n PMOS
For the first input end of current comparator, it is used for described first electric current received is carried out scaled mirror,
Obtain first image current of n and described first current in proportion；
The source electrode of described n NMOS tube is all connected with earth terminal, and the grid of described n NMOS tube is connected
As the second input of described current comparator, for by the second electric current in described first NMOS tube
Carry out scaled mirror, individual the second image current with described second current in proportion of the n obtained；
The NMOS tube that the drain electrode of described n PMOS is corresponding with described n NMOS tube respectively
Drain electrode be connected as n outfan of described current comparator.
Preferably, the topological classification of described digital power main circuit includes: buck topology, Boost topology,
Buck-boost topology, buck or boost topology, SEPIC topology or reverse exciting topological.
A kind of digital power output voltage control method, is applied to digital power, and this digital power includes shape
State testing circuit, pulse width modulator, driver, digital power main circuit, induction apparatus and analog digital conversion
Device, the method comprising the steps of:
The process corner of state detection circuit detection digital power and the temperature of described digital power place environment
Information, generates numeral school according to described process corner and described temperature information and adjusts information；
Dutycycle according to the output pulse signal that described numeral school adjusts information to adjust described pulse width modulator；
The power tube turn-off time of driver is adjusted according to the pulse signal after described adjustment dutycycle, it is ensured that
Described digital power main circuit output voltage is in the range of nominal tension.
Preferably, described generate numeral school according to described process corner and described temperature information and adjust information to include:
Generating school according to described process corner and described temperature information and adjust information, high-ranking officers adjust information to be compiled as number
Information is adjusted in word school.
Compared with prior art, technical scheme provided by the present invention has the advantage that
Digital power provided by the present invention and output voltage control method thereof, add shape in digital power
State testing circuit, the process corner of state detection circuit detection digital power and this digital power place environment
Temperature information, generate school according to process corner and temperature information and adjust information, high-ranking officers adjust information to be compiled as number
Information is adjusted in word school, adjusts the dutycycle of the output pulse signal of information adjustment pulse width modulator according to numeral school,
The power tube turn-off time of driver is adjusted, it is ensured that digital power output electricity according to the pulse signal after adjusting
Voltage-controlled system is in the range of nominal tension, it is to avoid be powered circuit due to digital power output voltage inaccuracy,
Thus its function is affected, produce unpredictable consequence.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below,
Accompanying drawing in description is only some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is embodiment of the present invention digital power structure chart；
Fig. 2 is the circuit structure diagram of embodiment of the present invention state detection circuit；
Fig. 3 is embodiment of the present invention digital power main circuit structure figure；
Fig. 4 is digital power output voltage control method flow chart in the embodiment of the present invention.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the application, below in conjunction with
Accompanying drawing in the embodiment of the present application, clearly and completely retouches the technical scheme in the embodiment of the present application
State, it is clear that described embodiment is only some embodiments of the present application rather than whole enforcement
Example.Based on the embodiment in the application, those of ordinary skill in the art are not before making creative work
Put the every other embodiment obtained, all should belong to the scope of the application protection.
As described in background, digital power output voltage may produce deviation with rated value.Invention
People studies discovery, and one of reason causing this defect exists aberrations in property for digital power internal circuit.
Owing to digital power is affected by process corner and its place ambient temperature, cause the internal electricity of digital power
Road aberrations in property so that digital power output voltage inaccuracy.
Present embodiments provide a kind of digital power, including induction apparatus, analog-digital converter and digital power
Main circuit, state detection circuit, pulse width modulator, driver, as it is shown in figure 1, wherein:
State detection circuit 101 is for detecting process corner and the temperature of its place environment of described digital power
Degree information, and generate school tune information according to described process corner and described temperature information, information is adjusted in described school
It is compiled as numeral school and adjusts information.
Wherein, for the corresponding relation preset between process corner and temperature information and school tune information.Information is adjusted in school
With process corner, the foundation of vs. temperature, it is by PMOS P1-Pn reasonable in design and NMOS
The breadth length ratio of pipe N1-Nn so that the school under different process corner with ambient temperature adjusts information different.
Pulse width modulator 102 is for the dutycycle adjusting information to adjust pulse signal according to described numeral school.
Concrete, pulse width modulator includes APU and pulse signal module two parts, described numeral
The algorithm of information adjustment algorithm processor is adjusted in school, after pulse signal module adjusts according to described APU
Algorithm adjust the dutycycle of pulse signal generated.
Driver 103 for adjusting the power of driver 103 according to the pulse signal after described adjustment dutycycle
The pipe turn-off time, it is ensured that digital power main circuit 104 output voltage is in the range of nominal tension.
When the temperature increases, state detection circuit 101 detects temperature information, believes according to variations in temperature
Breath generates school and adjusts information, and high-ranking officers adjust information to be compiled as numeral school and adjust information, the algorithm in pulse width modulator 102
Processor receives the digital school of state detection circuit 101 output and adjusts information to be adjusted algorithm, after adjustment
Algorithm improves the dutycycle of pulse signal of pulse width modulator 102, offset driver 103 when high temperature by
Decline and power tube turn-off time of bringing elongated problem in driving force, improve digital power main circuit
The efficiency of 104, it is ensured that digital power main circuit 104 output voltage control is in the range of nominal tension.
Present embodiment discloses a kind of state detection circuit, circuit structure is as in figure 2 it is shown, specifically include that the
One current source the 201, second current source the 202, first PMOS Pt, the first NMOS tube Nt, voltage-to-current
Information decoder 206 is adjusted in transducer 203, current comparator 204, bank of latches 205, school.
Wherein:
The current value It of the first current source 201 and the second current source 202 is equal.
First current source 201 is connected with the source electrode of the first PMOS Pt, the grid of the first PMOS Pt
Pole is connected earth terminal with drain electrode, and the voltage of the first PMOS Pt source electrode is as the first voltage Vgspt.
Second current source 202 is connected with the drain electrode of the first NMOS tube Nt, the source of the first NMOS tube Nt
Pole connects earth terminal, and the first NMOS tube Nt drain and gate is connected, the first NMOS tube Nt drain electrode
Electric current is as the second electric current In0.
Wherein, the first PMOS Pt and the first NMOS tube Nt can have identical breadth length ratio.
The input of voltage-current converter 203 and the source electrode of the first PMOS Pt are connected, for by the
One voltage Vgspt is converted to the first electric current Ip0.
Concrete, voltage-current converter 203 includes: the second PMOS P0, the second NMOS tube
N0, wherein:
The grid of the second NMOS tube N0 is the input of voltage-current converter 203, the 2nd NMOS
The source electrode of pipe N0 connects earth terminal, the drain electrode of the second NMOS tube N0 and described second PMOS P0
Grid be connected；
The source electrode of the second PMOS P0 connects power supply, the grid of the second PMOS P0 and the 2nd PMOS
The drain electrode of pipe P0 is connected, and the grid of the second PMOS P0 is the output of voltage-current converter 203
End.
The first input end of current comparator 204 is connected with the outfan of voltage-current converter 203, electricity
Second input of stream comparator 204 and the grid of the first NMOS tube Nt are connected, for by the first electric current
Ip0 carries out scaled mirror, obtains n and described first the first proportional for electric current Ip0 image current
Ip1-Ipn, and the second electric current In0 is carried out scaled mirror, the n obtained with the second current in proportion
Second image current In1-Inn, and by n the first image current Ip1-Ipn Yu n the second image current
The second image current In1-Inn corresponding in In1-Inn compares, and obtains n comparative result and exports to institute
N the outfan stating current comparator 204 obtains school tune information C1-Cn.
Concrete, current comparator 204 includes: n PMOS P1-Pn, n NMOS tube N1-Nn,
N is the integer more than 2, and n is the biggest, and the precision that school is adjusted is the highest.
The source electrode of n PMOS P1-Pn is all connected with power supply, and the grid of P1-Pn is connected as current ratio relatively
The first input end of device, for the described first electric current Ip0 received is carried out scaled mirror, obtains n
Individual and described first image current Ip1-Ipn proportional for electric current Ip0, i.e. Ip1=K1*Ip0, Ip2=K2*
Ip0 ... Ipn=Kn*Ip0, wherein Proportional coefficient K 1 is together decided on by the breadth length ratio of P1 and P0, in like manner
K2 is together decided on by the breadth length ratio of P2 and P0, and Kn is together decided on by the breadth length ratio of Pn and P0
The source electrode of n NMOS tube N1-Nn is all connected with earth terminal, the grid of n NMOS tube N1-Nn
It is connected as the second input of described current comparator 204, for by the in the first NMOS tube Nt
Two electric current In0 carry out scaled mirror, a n obtained and described second the second proportional for electric current In0 mirror image
Electric current In1-Inn；
The NMOS that the drain electrode of n PMOS P1-Pn is corresponding with n NMOS tube N1-Nn respectively
Connected n the outfan as current comparator 204 of drain electrode of pipe N1-Nn.
N input of bank of latches 205 is corresponding with n outfan of current comparator 204 to be connected,
Information C1-Cn is adjusted to latch for high-ranking officers.
School adjusts information decoder 206 input to be connected with the outfan of bank of latches 205, adjusts for high-ranking officers
Information C1-Cn is compiled as numeral school and adjusts information b1-bn, and this numeral school adjusts information b1-bn to be parallel binary
Signal.
The operation principle of above-mentioned state detection circuit is:
When digital power is energized, the first current source 201 is with the second current source 202 output current value
It, is obtained the first voltage Vgspt by the first PMOS Pt, and this first voltage Vgspt passes through PMOS
Pipe P0 and NMOS tube N0 are converted to the first electric current Ip0, and Ip0 enters through n PMOS P1-Pn
Row scaled mirror, obtains n the first image current Ip1-Ipn proportional for electric current Ip0 to first；
Second electric current In0 of the first NMOS tube Nt drain electrode, In0 enters through n NMOS tube N1-Nn
Row scaled mirror obtains the second image current In1-Inn proportional for electric current In0 to second；
Electric current Ip1-Ipn in n PMOS P1-Pn respectively with in n NMOS tube N1-Nn
Electric current In1-Inn correspondence compares, and obtains n comparative result, i.e. Ip1 with In1 and compares the comparison knot obtained
Really C1, and export from the first outfan (drain electrode of P1 and N1)；Ip2 with In2 compares, the ratio obtained
Relatively result C2 exports from the second outfan (drain electrode of P2 and N2)；The like, Ipn with Inn ratio
Relatively, obtain comparative result Cn, export from the n-th outfan (drain electrode of Pn and Nn).
It is input in bank of latches 205 latch by the comparative result C1-Cn that current comparator produces, to obtain final product
Information is adjusted in school to n position, and wherein, n is the integer more than 2, and n is the biggest, and the precision that school is adjusted is the highest, school
Adjusting information decoder 206 high-ranking officers to adjust information to be compiled as numeral school and adjust information b1-bn, wherein, information is adjusted in school
If the power level that C1-Cn is less than 0.1 times, it is logic digital " 0 ", if the power supply electricity higher than 0.9 times
Flat then be logic numeral " 1 ".
Such as: assume that in state detection circuit, the value of n is 4.
A, process corner are that normal digital power place ambient temperature is initially room temperature (25 degrees Celsius),
Now, Ip1<In1, Ip2<In2, Ip3>In3, Ip4>In4 in state detection circuit, then C1, C2, C3,
C4 is output as low level, low level, high level, high level, and numeral school adjusts information to be 0011.Work as institute
State (assuming that temperature is 125 degrees Celsius) when digital power place ambient temperature raises, the first PMOS
Pt and the first NMOS tube Nt performance all change, and amplitude of variation is different, it is assumed that Pt Yu Nt performance changes
After, Ip1 < In1, Ip2 < In2, Ip3 < In3, Ip4 < In4 in state detection circuit, then C1, C2,
C3, C4 output is all " low level ", and this numeral school adjusts information to be 0000, say, that numeral school
Tune information becomes 0000 from 0011, the analog voltage V after digital to analog converter conversionOUTDiminish.
When B, ambient temperature are room temperature (25 degrees Celsius), take the first digital power and the second digital power,
Wherein, the process corner of the first digital power is PMOS normal, NMOS normal, now, first
Ip1<In1, Ip2<In2, Ip3>In3, Ip4>In4 in first state detection circuit in digital power, then
C1, C2, C3, C4 are output as low level, low level, high level, high level, and the first numeral school is adjusted
Information is 0011；The process corner of the second digital power is PMOS normal, NMOS slow, due to
Process corner NMOS process corner is that the threshold voltage of slow, Nt is higher, now, in the second digital power
Ip1 < In1, Ip2 < In2, Ip3 < In3, Ip4 < In4 in two-state testing circuit, then C1, C2, C3,
C4 output is all low level, and numeral school adjusts information to be 0000.
The open a kind of digital power main circuit of the present embodiment, including diode, inducer and capacitor, as
Shown in Fig. 3, wherein:
It is defeated that the cut-off end of the input of inducer 301 and diode 302 is connected as digital power main circuit
Enter end to be connected with the outfan of driver, one end phase continuous cropping of the outfan of inducer 301 and capacitor 303
It is connected with the input of induction apparatus for the outfan of digital power main circuit.
The conduction terminal of diode 302 is connected with the other end of capacitor 304 and is followed by earth terminal.
The electric source topology type of the digital power main circuit provided in the present embodiment is voltage-dropping type, will drive
The voltage waveform of device input exports after being adjusted, and final output voltage value is less than input voltage.
Digital power main circuit described in above-described embodiment is one of them example in the present invention, this
It is voltage-dropping type that invention digital power main circuit is not limited in electric source topology type, digital power master of the present invention
The electric source topology type of circuit includes: Boost topology, buck-boost topology, buck or boost topology, SEPIC
Topology (single ended primary inductor converter) or reverse exciting topological etc..
Corresponding to above-mentioned digital power, present invention also offers a kind of digital power output voltage control side
Method, is applied to digital power, this digital power include state detection circuit, pulse width modulator, driver,
Digital power main circuit, induction apparatus and analog-digital converter, the method comprising the steps of, as shown in Figure 3:
401, the state detection circuit detection process corner of digital power and described digital power place environment
Temperature information, generates numeral school according to described process corner and described temperature information and adjusts information.
It should be noted that this detection is circulation.First be the detection process corner of digital power and its
The temperature information of place environment, generates numeral school according to described process corner and described temperature information and adjusts information；
Then determine that due to process corner, predominantly detect this digital power place ambient temperature information so follow-up,
This detection process is cyclic process.
Wherein, step 401 generates numeral school according to described process corner and described temperature information and adjust information
Including: generating school according to described process corner and described temperature information and adjust information, high-ranking officers adjust information to be compiled as
Information is adjusted in numeral school.
402, the duty of the output pulse signal adjusting information to adjust described pulse width modulator according to described numeral school
Ratio.
It should be noted that first numeral school to be adjusted the APU that information is sent in pulse width modulator,
APU adjusts information to adjust its algorithm, then the pulse signal mould in pulse width modulator according to numeral school
Tuber adjusts the dutycycle of pulse signal according to the algorithm after adjusting.
403, the power tube turn-off time of driver is adjusted according to the pulse signal after described adjustment dutycycle,
Ensure that described digital power main circuit output voltage is in the range of nominal tension.
Said method is used to control digital power output voltage, it is ensured that digital power output voltage control exists
In the range of nominal tension, it is to avoid be powered circuit due to digital power output voltage inaccuracy, thus its
Function is affected, and produces unpredictable consequence.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses
The present invention.Multiple amendment to these embodiments will be aobvious and easy for those skilled in the art
See, generic principles defined herein can without departing from the spirit or scope of the present invention,
Realize in other embodiments.Therefore, the present invention is not intended to be limited to the embodiments shown herein,
And it is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (7)
1. a digital power, including induction apparatus, analog-digital converter and digital power main circuit, it is special
Levying and be, this digital power also includes: state detection circuit, pulse width modulator, driver, wherein:
Described state detection circuit is for detecting process corner and the temperature of its place environment of described digital power
Degree information, and generate school tune information according to described process corner and described temperature information, information is adjusted in described school
It is compiled as numeral school and adjusts information, wherein, corresponding for preset between process corner and temperature information with school tune information
Relation；Information and process corner, the foundation of vs. temperature are adjusted in school, be by PMOS P1-Pn and
The breadth length ratio of NMOS tube N1-Nn so that information is adjusted not in the school under different process corner and ambient temperature
With；
Described pulse width modulator is for the dutycycle adjusting information to adjust pulse signal according to described numeral school；
Described driver for adjusting the merit of described driver according to the pulse signal after described adjustment dutycycle
The rate pipe turn-off time, it is ensured that described digital power main circuit output voltage is in the range of nominal tension；
Described state detection circuit includes: the first current source, the second current source, the first PMOS,
Information decoder is adjusted in one NMOS tube, voltage-current converter, current comparator, bank of latches, school,
Wherein:
The current value of described first current source and described second current source is equal；
Described first current source is connected with the source electrode of described first PMOS, described first PMOS
Grid is connected earth terminal with drain electrode, and the voltage of described first PMOS source electrode is as the first voltage；
The input of described voltage-current converter is connected with the source electrode of described first PMOS, and being used for will
Described first voltage is converted to the first electric current；
Described second current source is connected with the drain electrode of described first NMOS tube, described first NMOS tube
Source electrode connects earth terminal, and the drain current of described first NMOS tube is as the second electric current；
The first input end of described current comparator is connected with the outfan of described voltage-current converter, institute
The grid of the second input and described first NMOS tube of stating current comparator is connected, for by described the
One electric current carries out scaled mirror, obtains first image current of n and described first current in proportion, with
And described second electric current is carried out scaled mirror, a n obtained and the second of described second current in proportion
Image current, and n described first image current is compared with n described second image current,
Obtain n comparative result output to n outfan of described current comparator and obtain school tune information, wherein,
N is the integer more than 2；
N input of described bank of latches is corresponding with n outfan of described current comparator to be connected,
For described school tune information is latched；
Described school adjusts information decoder input to be connected with the outfan of described bank of latches, for by described
School is adjusted information to be compiled as numeral school and is adjusted information.
Digital power the most according to claim 1, it is characterised in that described numeral school tune information is
Parallel binary signal.
Digital power the most according to claim 1, it is characterised in that described first PMOS and
Described first NMOS tube has identical breadth length ratio.
Digital power the most according to claim 1, it is characterised in that described voltage-current converter
Including: the second PMOS, the second NMOS tube, wherein:
The grid of described second NMOS tube is the input of described voltage-current converter, described second
The source electrode of NMOS tube connects earth terminal, the drain electrode of described second NMOS tube and described second PMOS
Grid be connected；
The source electrode of described second PMOS connects power supply, the grid of described second PMOS and described the
The drain electrode of two PMOS is connected, and the grid of described second PMOS is described voltage-current converter
Outfan.
Digital power the most according to claim 1, it is characterised in that described current comparator includes:
N PMOS, n NMOS tube, wherein:
The source electrode of described n PMOS is all connected with power supply, the grid phase continuous cropping of described n PMOS
For the first input end of current comparator, it is used for described first electric current received is carried out scaled mirror,
Obtain first image current of n and described first current in proportion；
The source electrode of described n NMOS tube is all connected with earth terminal, and the grid of described n NMOS tube is connected
As the second input of described current comparator, for by the second electric current in described first NMOS tube
Carry out scaled mirror, individual the second image current with described second current in proportion of the n obtained；
The NMOS tube that the drain electrode of described n PMOS is corresponding with described n NMOS tube respectively
Drain electrode be connected as n outfan of described current comparator.
Digital power the most according to claim 1, it is characterised in that described digital power main circuit
Topological classification include: buck topology, Boost topology, buck-boost topology, SEPIC topology or flyback
Formula topology.
7. a digital power output voltage control method, is applied to digital power, it is characterised in that should
Digital power includes state detection circuit, pulse width modulator, driver, digital power main circuit, sensing
Device and analog-digital converter, the method comprising the steps of:
The process corner of state detection circuit detection digital power and the temperature of described digital power place environment
Information, generates numeral school according to described process corner and described temperature information and adjusts information, wherein, process corner
And for the corresponding relation preset between temperature information and school tune information；School adjusts information and process corner, temperature corresponding
The foundation of relation, is the breadth length ratio by PMOS P1-Pn and NMOS tube N1-Nn so that not
Same process corner adjusts information different with the school under ambient temperature；
Dutycycle according to the output pulse signal that described numeral school adjusts information to adjust described pulse width modulator；
The power tube turn-off time of driver is adjusted according to the pulse signal after described adjustment dutycycle, it is ensured that
Described digital power main circuit output voltage is in the range of nominal tension；
Described generate numeral school according to described process corner and described temperature information and adjust information to include:
Generating school according to described process corner and described temperature information and adjust information, high-ranking officers adjust information to be compiled as number
Information is adjusted in word school.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310629372.6A CN103633843B (en) | 2013-11-28 | 2013-11-28 | A kind of digital power and output voltage control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310629372.6A CN103633843B (en) | 2013-11-28 | 2013-11-28 | A kind of digital power and output voltage control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103633843A CN103633843A (en) | 2014-03-12 |
| CN103633843B true CN103633843B (en) | 2016-09-14 |
Family
ID=50214559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310629372.6A Active CN103633843B (en) | 2013-11-28 | 2013-11-28 | A kind of digital power and output voltage control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103633843B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620450A (en) * | 2009-08-12 | 2010-01-06 | 绿达光电(苏州)有限公司 | High-precision constant flow source circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100589058C (en) * | 2007-12-27 | 2010-02-10 | 北京中星微电子有限公司 | Current limitation circuit as well as voltage regulator and DC-DC converter including the same |
-
2013
- 2013-11-28 CN CN201310629372.6A patent/CN103633843B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620450A (en) * | 2009-08-12 | 2010-01-06 | 绿达光电(苏州)有限公司 | High-precision constant flow source circuit |
Non-Patent Citations (1)
| Title |
|---|
| 温度工艺补偿技术的研究;陈华;《中国优秀硕士学位论文全文数据库》;20090415;第21-23，29，37，38页，图5.1，图3.2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103633843A (en) | 2014-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103675426B (en) | Inductive current zero-crossing detection method, circuit and switch power supply with circuit | |
| KR101158651B1 (en) | Current sensing circuit and switching regulator including the same | |
| CN103956884B (en) | Reference compensation unit and switching type voltage adjustment circuit | |
| CN104300792B (en) | Current detection circuit and the current loop control circuit including the current detection circuit | |
| CN102916579B (en) | Switching converter circuit and control method thereof | |
| CN103378617B (en) | Lithium battery charging circuit | |
| CN103605035B (en) | The no load detection circuit structure of self-adaption switch electric power source | |
| CN101895246A (en) | Control pulse generating circuit and regulating system and method of direct current brushless motor speed | |
| CN103701321B (en) | A kind of fast transient response buck synchronous rectified DC-DC converter | |
| CN103268134B (en) | The low difference voltage regulator of transient response can be improved | |
| CN104901534B (en) | A kind of slope compensation circuit and DC DC conversion equipments | |
| CN103631294B (en) | A kind of supply voltage automatic regulating apparatus and method | |
| CN103647440A (en) | Soft-start circuit and DC-DC circuit including soft-start circuit | |
| US10164537B2 (en) | Switching regulator | |
| US9819191B1 (en) | Maximum power point tracking for low power energy harvesting | |
| CN104467416B (en) | DC-DC switching circuit | |
| Das et al. | Design architecture for continuous-time control of dual active bridge converter | |
| CN105871207B (en) | Power supply changeover device | |
| CN103592990B (en) | A kind of linear stabilized power supply and voltage adjusting method thereof | |
| Saravanan et al. | Buck converter with a variable number of predictive current distributing method | |
| CN106647911A (en) | Multifunctional LDO circuit applicable to low-power-consumption RFID reader | |
| CN103633843B (en) | A kind of digital power and output voltage control method thereof | |
| CN106774609B (en) | Maximum working point tracking control circuit for space | |
| CN204859602U (en) | LED driver chip's zero passage current detection circuit and use thereof | |
| CN103634001B (en) | A kind of voltage controlled oscillator and output frequency control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |